CN114242660B - A method for manufacturing a rectifier circuit, a rectifier circuit, a voltage conversion circuit and a power supply - Google Patents
A method for manufacturing a rectifier circuit, a rectifier circuit, a voltage conversion circuit and a power supply Download PDFInfo
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- CN114242660B CN114242660B CN202111230621.5A CN202111230621A CN114242660B CN 114242660 B CN114242660 B CN 114242660B CN 202111230621 A CN202111230621 A CN 202111230621A CN 114242660 B CN114242660 B CN 114242660B
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
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- 230000003071 parasitic effect Effects 0.000 claims abstract description 13
- 238000005457 optimization Methods 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 141
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 69
- 229920005591 polysilicon Polymers 0.000 claims description 65
- 239000011229 interlayer Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 30
- 238000000151 deposition Methods 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 19
- OLBVUFHMDRJKTK-UHFFFAOYSA-N [N].[O] Chemical compound [N].[O] OLBVUFHMDRJKTK-UHFFFAOYSA-N 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 18
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 15
- 238000002360 preparation method Methods 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 11
- 239000001301 oxygen Substances 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 9
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
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- 239000000126 substance Substances 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
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- 230000006872 improvement Effects 0.000 abstract description 7
- 238000011084 recovery Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000004377 microelectronic Methods 0.000 abstract description 2
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- 239000000758 substrate Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention belongs to the technical field of microelectronics, and discloses a rectifying circuit manufacturing method, a rectifying circuit, a voltage conversion circuit and a power supply corresponding to the rectifying circuit, wherein the manufacturing method is based on the performance optimization of a rectifying unit in a direct-direct converter circuit, improves the manufacturing process of a MOSFET rectifying unit, obtains good electrical characteristics, integrates a Schottky rectifying area and a MOSFET parasitic body diode in parallel connection on the existing structure, can replace a MOSFET and a freewheel diode parallel connection structure and obtains lower reverse recovery characteristics, thereby reducing the conduction power consumption under high frequency. In addition, the invention does not need additional new photomask in the process realization process, does not increase the cost of the process, ensures high continuity of the process improvement and is beneficial to improving the efficiency of the process improvement.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a rectifying circuit manufacturing method, a rectifying circuit, a voltage conversion circuit and a power supply.
Background
The rectifier circuit is one of important circuit structures of the electronic circuit, and with the deep application of the electronic circuit, more and more subdivided technical requirements are put on the rectifier circuit, so that the rectifier circuit not only needs to have excellent performance, but also has higher technical and economic values.
Disclosure of Invention
The invention improves the manufacturing process of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) rectifying unit based on the performance optimization of the rectifying unit in the direct-direct converter circuit, obtains good electrical characteristics, integrates a Schottky rectifying area and a MOSFET parasitic body diode in parallel on the existing structure, can replace the parallel structure of the MOSFET and a freewheel diode and obtains lower reverse recovery characteristic, thereby reducing the conduction power consumption under high frequency.
In addition, the invention does not need additional new photomask in the process realization process, does not increase the cost of the process, ensures high continuity of the process improvement and is beneficial to improving the efficiency of the process improvement.
And preparing the first photomask and the second photomask until the Nth photomask through a photomask presetting step, wherein N is a positive integer larger than 10, and preparing the N+1th photomask and the N+2th photomask until the Mth photomask, wherein M is a positive integer larger than 12.
And through a photomask optimization step, sequentially using a first photomask, a second photomask, an N-th photomask, an (n+1) -th photomask and an M-th photomask, wherein M is greater than N, and converting a preset circuit pattern to a preset target position.
The manufacturing method comprises the steps of setting a grid structure manufacturing step to manufacture a shielding grid structure, wherein M photomasks are used in the manufacturing of the shielding grid, a first characteristic pattern of a Schottky rectifying circuit is manufactured on an R-th photomask, a second characteristic pattern of the Schottky rectifying circuit is manufactured on an R+1st photomask, N is not less than or equal to R and not more than M, M is not equal to N, a last characteristic pattern required for manufacturing the Schottky rectifying circuit is manufactured on an S-th photomask, N is not less than or equal to R and not more than S, M is not equal to N, R and S are positive integers, and the steps are optimized after being integrated with the existing technology of the shielding grid, and no other photomasks are required to be added to process the characteristic patterns.
The manufacturing method comprises the steps of manufacturing a grid structure, adjusting the technological parameters in the manufacturing step of the grid structure, enabling a Schottky rectifying circuit to be connected with a parasitic diode of a shielding grid in parallel, wherein the shielding grid is of a groove structure, an ILD interlayer dielectric body and a polysilicon grid are introduced into the groove structure, the interlayer dielectric body is used for isolating the polysilicon grid filled in the groove, and further connecting a source electrode, a grid electrode and a drain electrode of the rectifying circuit to pins of the rectifying circuit, and connecting the source electrode and the grid electrode to a metal layer through contact holes to realize circuit topology.
In order to improve the performance, the freewheel portion generation step connects the source and gate electrodes through contact holes, which pass through the ILD interlayer dielectric and communicate with the source, gate and drain electrodes.
The source electrode of the Schottky rectifying circuit is directly and electrically connected with the metal layer, one end of the source electrode of the rectifying circuit, which is far away from the metal layer, is electrically connected with the drain electrode through a groove structure, the groove structure obtains the characteristic pattern between the R-th photomask and the S-th photomask, all the photomasks improve the characteristic pattern on the basis of the original process, a new photomask process is not required to be introduced, the cost of the process is not increased, the improvement continuity of the process is high, and the improvement efficiency of the process is improved.
In order to further improve the association between the gate structure and the rectifying structure, the invention also discloses a functional region optimizing step, wherein the functional region optimizing layer is prepared, the film structure obtained by deposition, electroplating and/or other film processes is prepared, and the MOSFET functional region graph and the Schottky rectifying region graph of the functional region optimizing layer are transferred to a target position under the action of the same photomask or the same series of photomasks.
After the schottky rectifying region is transferred through the nth mask, the feature pattern of at least two contact holes is transferred on the rectifying region drain to improve circuit characteristics.
Further, the working window of the gate oxide layer of the MOSFET and the rectifying unit is defined or etched through the removing process of the oxygen-nitrogen interlayer mask, the working window is used for preparing the gate oxide layer through an oxidation process, and the gate oxide layer is used for isolating the gate polysilicon layer and other related layers and obtaining related circuit units.
The oxygen-nitrogen interlayer comprises a first mask, a second mask and a third mask, wherein the first mask is a first oxide layer or a thermal oxide layer, the second mask is a nitride layer, and the third mask is a second oxide layer.
Further, the process of the oxygen-nitrogen interlayer mask before the removal of the shielding gate region further comprises trench group etching, thick oxygen deposition, polysilicon source back etching, polysilicon groove back etching, HDP (High-DENSITY PLASMA) chemical vapor deposition and oxide CPM (ChemicalMechanicalPolishing ). Specifically:
The etching step of the groove group is to obtain a first type substrate layer through epitaxy, and etch the first type substrate layer to obtain a gate groove group, wherein the gate groove group comprises at least three grooves, and the depth of each groove in the gate groove group is not smaller than the depth of a preset source electrode first groove.
And depositing a third silicon oxide layer on the bottom surface and the side elevation of the grid groove group through a thick oxygen deposition step, wherein the third oxide layer and the second oxide layer can be provided with the same or different oxide materials.
And depositing polycrystalline silicon on the third oxide layer through a polycrystalline silicon source deposition step until filling the grid electrode groove and the surface layer of the workpiece to form source polycrystalline silicon, namely a first polycrystalline silicon layer.
And etching back the first polysilicon layer where the polysilicon source is located through a polysilicon source etching back step, and reserving a thick oxygen layer side wall of the grid electrode groove group to obtain a second groove group covered by the thick oxygen side wall, wherein the depth of the second groove group is larger than that of the oxygen-nitrogen interlayer mask.
And at least two third groove groups which are closer to the Schottky rectifying circuit are obtained by combining the step of etching the polysilicon grooves with the photoresist.
Further, the first polysilicon layer is capped by obtaining a fourth oxide layer by high density plasma CVD (Chemical Vapor Deposition ) in an oxide HDP step.
And (3) obtaining the flush workpiece surface by using the second mask as a stop layer through an oxide CMP step and adopting a chemical mechanical polishing process.
Further, the method of the present invention also discloses an improvement in obtaining SBR (Super Barrier Rectifier ) circuits.
The process after the oxygen-nitrogen interlayer mask is removed from the shielding gate region further comprises the steps of gate electrode oxidation, gate polysilicon deposition, gate polysilicon CMP and etching, nitrogen oxide removal, P-well photoetching implantation and functional region isolation.
And through a gate electrode oxidation step, after removing the oxygen-nitrogen interlayer mask and etching to obtain a gate electrode groove, oxidizing to generate an oxide layer covering the MOSFET region, and connecting the first oxide layer in the gate electrode groove and filling the gate electrode oxide layer of the SBR region groove, wherein the gate electrode oxide layer is combined with the original oxide layer to form a fifth oxide layer.
Polysilicon is deposited into the gate trench by a gate polysilicon deposition step and further covers the entire device surface to a predetermined thickness.
And (3) through the steps of gate polysilicon CMP and etching, taking the fifth oxide layer as a stop layer, adopting a CMP method to obtain a bare oxide layer in the MOSFET region and reserving polysilicon in the source region, wherein the polysilicon in the MOSFET region is lower than the surface of the bare oxide layer after the polysilicon is subjected to the etching process, so that the polysilicon layer in the SBR region is flush with other materials.
And removing nitrogen oxides in the SBR region through a nitrogen oxide removing step to obtain the polysilicon workpiece which is positioned in the source electrode groove and protrudes out of the oxide layer.
Through P-well lithography and implantation steps, P-wells are constructed and electrode contacts are implanted into the MOSFET regions.
Filling each groove on the surface of the workpiece with an interlayer dielectric body and covering the whole workpiece through a functional area isolation step.
Further, a metal film is formed outside the interlayer dielectric body through the improved metal layer preparation step and the contact hole communication step, so that the metal film is communicated with the MOSFET region and the SBR region through the contact hole.
An improved approach is to make the first mask not thicker than 50a and the second oxide not thicker than 1000 a.
And a rectifying circuit, corresponding rectifying circuits, voltage converters, power supplies and other circuits or devices can be obtained by adopting the method.
The manufacturing process of the circuit comprises M photomasks, wherein the Nth photomask is a step mark photomask, the R-S photomasks are used for synchronizing with the transfer process of the shielding grid characteristic pattern and forming the characteristic pattern of the Schottky rectifying circuit, R is not less than R is not more than M, M is not more than N, and M, N, R and S are positive integers.
The method is used for preparing the core rectifying unit, and the rectifying and/or freewheeling unit is realized by the method or the rectifying circuit disclosed by the invention is used for carrying out chopping treatment.
Furthermore, the rectifying circuits arranged in the low-side MOSFET of the converter can be replaced by the circuits disclosed by the invention to obtain optimized performance, wherein the rectifying circuits further comprise external auxiliary circuits for completing the step-up or step-down conversion, and the rectifying circuits comprise Schottky rectifying circuits integrated in the converter and MOSFET parasitic body diodes manufactured in a synchronous integrated manner, and the Schottky rectifying circuits are connected with the parasitic body diodes in parallel.
The invention integrates the Schottky rectifying area and the parasitic body diode of the MOSFET in parallel connection on the existing structure, can replace the parallel connection structure of the MOSFET and the freewheel diode and obtain lower reverse recovery characteristic, thereby reducing the conduction power consumption under high frequency.
It should be noted that, the terms "first", "second", and the like are used herein merely to describe each component in the technical solution, and are not limited to the technical solution, nor should they be construed as indicating or implying importance of the corresponding component, and the component with the terms "first", "second", and the like is indicated in the corresponding technical solution, and at least one component is included in the corresponding technical solution.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the technical effects, technical features and objects of the present invention will be further understood, and the present invention will be described in detail below with reference to the accompanying drawings, which form a necessary part of the specification, and together with the embodiments of the present invention serve to illustrate the technical solution of the present invention, but not to limit the present invention.
Like reference numerals in the drawings denote like parts, in particular:
FIG. 1 is a schematic diagram of trench etching in an embodiment of the present invention;
FIG. 2 is a schematic diagram of thick oxygen layer deposition according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a first (source) polysilicon (layer) deposition according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a first (source) polysilicon (layer) etch-back in accordance with an embodiment of the present invention;
FIG. 5 is a schematic diagram of etching a recess in source polysilicon with photoresist according to an embodiment of the present invention;
FIG. 6 is a schematic illustration of a high density plasma vapor deposition of a (third) oxide layer according to an embodiment of the present invention;
FIG. 7 is a schematic illustration of the chemical mechanical polishing of a third oxide (layer) according to an embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating the gate channel and the rectifying region according to an embodiment of the present invention;
FIG. 9 is a schematic illustration of mask removal for an oxygen-nitrogen interlayer according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of gate oxidation according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a second (gate) polysilicon (layer) deposition according to an embodiment of the present invention;
FIG. 12 is a schematic illustration of chemical mechanical polishing and etching of a second (gate) polysilicon layer according to an embodiment of the present invention;
FIG. 13 is a schematic diagram illustrating the removal of a second mask (nitride layer) according to an embodiment of the present invention;
FIG. 14 is a schematic illustration of P-well lithography and ion implantation according to an embodiment of the present invention;
FIG. 15 is a schematic view of source lithography/ion implantation and interlayer dielectric deposition according to an embodiment of the present invention;
FIG. 16 is a schematic diagram of a parallel structure of MOS and SBR according to an embodiment of the present invention;
FIG. 17 is a schematic diagram of a voltage conversion circuit according to an embodiment of the present invention;
FIG. 18 is a flow chart of an embodiment of the method of the present invention;
FIG. 19 is a schematic flow chart of a modification of the method of the present invention;
FIG. 20 is a schematic flow chart of a second modification of the method of the present invention;
Wherein:
10-shielding grid, 20-Schottky rectifying circuit;
100-drain (layer), 101- (deep) set of gate trenches,
102-A first mask (first oxide layer) or thermal oxide layer,
104-A third mask (second oxide layer),
105-Thick oxide layer (third oxide layer),
106-A second mask (nitride layer),
108-Source polysilicon (first polysilicon layer),
109-A second set of grooves,
110-A first photoresist (layer),
111-A third set of grooves,
112-A fourth oxide layer of the silicon oxide,
114-Functional division mask (layer),
115-A fifth oxide layer of the semiconductor device,
116-Second (gate) polysilicon (layer),
118-A second photoresist (layer),
120-P well (implant) (layer),
A 122-ILD inter-layer dielectric layer,
124-The electrode contact body is provided with a contact hole,
1000-Low side MOSFET and accessory circuitry,
2000-A voltage conversion output terminal, which is connected with a power supply,
A 3000-type inductance unit, which is provided with a capacitor,
3200-High side low side interface point,
4000-High-side MOSFET and accessory circuitry,
A 5000-voltage conversion input terminal,
6000-The power supply end of the control circuit,
7000-Power supply control circuits.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. Of course, the following specific examples are set forth only to illustrate the technical solution of the present invention, and are not intended to limit the present invention. Furthermore, the parts expressed in the examples or drawings are merely illustrative of the relevant parts of the present invention, and not all of the present invention.
Fig. 18 is a schematic flow chart of a method for manufacturing a MOSFET rectifying circuit according to an embodiment of the present invention, wherein the steps of the gate structure preparation 300, the structure association 400 and the freewheel part generation 500 are performed between the preceding step 200 and the following step 600.
The method comprises the steps of preparing a first photomask and a second photomask until an N-th photomask, wherein N is a positive integer greater than 10, and preparing an N+1th photomask and an N+2th photomask until an M-th photomask, wherein M is a positive integer greater than 12.
The method further comprises a photomask optimization step of sequentially using the first photomask, the second photomask, the N-th photomask and the (n+1) -th photomask to the M-th photomask, wherein M is greater than N, and the preset circuit pattern is converted to a preset target position through the use of the first photomask to the M-th photomask.
As shown in fig. 18 and 16, the gate structure manufacturing step 300 is performed by manufacturing the shielding gate 10 to complete the manufacturing of the device switch circuit core, wherein M photomasks are used in total for manufacturing the shielding gate 10, the first feature pattern for manufacturing the schottky rectifying circuit 20 is formed on the R-th photomask, the second feature pattern for manufacturing the schottky rectifying circuit 20 is formed on the r+1st photomask, N is not less than R and not more than M, M is not more than N, the last feature pattern required for manufacturing the schottky rectifying circuit 20 is formed on the S-th photomask, N is not less than R and not more than M, M is not more than N, and R and S are positive integers.
In the structure association step, as shown in fig. 16, the process parameters in the gate structure preparation step are adjusted to connect the schottky rectifying circuit 20 with the parasitic body diode of the shielding gate 10 in parallel, the shielding gate 10 is in a trench structure, including an ILD interlayer dielectric 122 and a polysilicon gate 116, the interlayer dielectric 122 is used to isolate the polysilicon gate 116 filled in the trench, and the source 108, the gate 116 and the drain 100 of the rectifying circuit are connected to the pins of the rectifying circuit, wherein the source 108 and the gate 116 are connected to the metal layer 128 through the contact hole 126.
In the step of generating the flywheel portion shown in fig. 16 and 17, the source electrode 108 and the gate electrode 116 are connected by the contact hole 126, and the contact hole 126 passes through the ILD interlayer dielectric 122 and is connected to the source electrode 108, the gate electrode 116 and the drain electrode 100, wherein the source electrode 108 of the schottky rectifying circuit 20 is directly electrically connected to the metal layer 128, and one end of the source electrode 108 of the rectifying circuit 20, which is far away from the metal layer 128, is electrically connected to the drain electrode 100 by a trench structure, and the trench structure obtains a feature pattern between the R-th mask and the S-th mask.
Further, as shown in fig. 16 and 17, a functional region optimizing layer is prepared in a functional region optimizing step, wherein the functional region optimizing layer is in a film structure and is prepared by deposition, electroplating and/or other film processes, the feature pattern of the functional region optimizing layer comprises a MOSFET functional region pattern and a schottky rectifying region pattern, and the MOSFET functional region pattern and the schottky rectifying region pattern are transferred to a target position under the action of the same photomask or the same series of photomasks.
After the schottky rectifying region 20 is transferred through the nth mask, the feature pattern of at least two contact holes is transferred on the drain electrode of the rectifying region.
The gate oxide working window of the MOSFET and the rectifying unit is defined or etched through the removing process of the oxygen-nitrogen interlayer mask shown in figure 1, the working window is used for preparing the gate oxide through an oxidation process, and the gate oxide is used for isolating a gate polysilicon layer and other related layers and obtaining related circuit units.
The oxygen-nitrogen interlayer shown in fig. 1 includes a first mask 102, a second mask 106 and a third mask 104, wherein the first mask 102 is a first oxide layer or a thermal oxide layer, the second mask 106 is a nitride layer, and the third mask is the second oxide layer 104.
Further, as shown in fig. 1 to 7 and 19, the process of removing the oxynitride interlayer mask in the region of the shielding gate 10 further includes:
the trench group etching step 302 is as shown in fig. 1, the first type substrate 100 is obtained by an epitaxial process, and the gate trench group 101 is etched in the first type substrate 100, where the gate trench group 101 includes at least three trenches, and the depth of each trench is not less than the depth of the preset source first trench.
As shown in fig. 2 and 19, in the thick oxygen deposition step 304, a third oxide layer 105 of silicon is deposited on the bottom surface and the side elevation of the gate trench set 101, wherein the third oxide layer 105 and the second oxide layer 104 may have the same or different oxide materials.
As shown in fig. 3 and 19, a polysilicon source deposition step 306 is performed to form a source polysilicon layer 108 by depositing polysilicon on the third oxide layer 105 until the gate trench and the workpiece surface are filled.
As shown in fig. 4 and fig. 19, in the polysilicon source etching back step 308, the thick oxygen layer sidewall of the gate trench set 101 is reserved by etching back the first polysilicon layer 108 where the polysilicon source is located, so as to obtain a second trench set 109 covered by the thick oxygen sidewall, where the depth of the second trench set 109 is greater than the thickness of the oxygen-nitrogen interlayer mask.
As shown in fig. 5 and 19, the step 310 of etching the polysilicon grooves with photoresist is combined to obtain at least two third groove groups 111 closer to the schottky rectifying circuit 20.
As shown in fig. 6 and 19, an oxide HDP step 312 is performed to deposit oxide using high density plasma CVD to obtain the fourth oxide layer 112, which plugs the first polysilicon layer 108.
In an oxide CMP step 314, shown in FIGS. 7 and 19, a chemical mechanical polishing process is performed to obtain a flush workpiece surface using the second mask 106 as a stop layer.
Further, as shown in FIGS. 8 to 16 and 20, the preparation of the SBR circuit of the present embodiment includes the following steps, wherein the process of removing the oxygen-nitrogen interlayer mask in the shielding gate 10 region further includes:
In the gate oxidation step 402 shown in fig. 8-10 and fig. 20, after removing the oxygen-nitrogen interlayer mask and etching to obtain the gate trench, the oxide layer covering the MOSFET region and the gate oxide layer in the gate trench, which is connected to the first oxide layer and fills the trench in the SBR region, are oxidized to form the fifth oxide layer 115, wherein the fifth oxide layer is combined with the original oxide layer.
The SBR region generally needs to define a specific region corresponding to a mask plate and match related process steps to realize corresponding device functions, the embodiment of the invention can achieve the same effect by simplifying a multi-step process by utilizing a self-alignment process, and in FIG. 8, the SBR region can be defined while a grid groove is obtained by utilizing a mask and etching.
A gate polysilicon deposition step 404, shown in fig. 11 and 20, deposits polysilicon into the gate trench and further covers the entire device surface to a predetermined thickness.
In the gate polysilicon CMP and etching step 406 shown in fig. 12 and 20, the fifth oxide layer 115 is used as a stop layer, and a CMP method is used to obtain a bare oxide layer in the MOSFET region and to reserve polysilicon in the source region, wherein the polysilicon in the MOSFET region is lower than the surface of the bare oxide layer after the etching process, and the polysilicon layer in the SBR region is made to be level with other materials.
In the oxynitride removal step 408 shown in fig. 13 and 20, the oxynitride in the SBR region is removed to obtain the polysilicon workpiece film 116 in the source trench and protruding from the oxide layer.
As shown in fig. 14 and 20, P-well lithography and implantation step 410 is performed by constructing P-well 120 and implanting electrode contact 124 into the MOSFET region.
As shown in fig. 15 and 20, the functional region isolation step 412 fills the trenches in the surface of the workpiece with the interlayer dielectric 122 and covers the entire workpiece.
As shown in fig. 16, the metal layer preparation step constructs a metal film 128 outside the interlayer dielectric 122, and the metal film 128 communicates with the MOSFET region and the SBR region through the contact hole 126.
Through process optimization, the thickness of the first mask can be controlled to be not more than 50A, and the thickness of the second oxide layer can be controlled to be not more than 1000A.
As shown in fig. 17, a schematic circuit diagram of the rectifying circuit and the voltage converting circuit of the present invention is shown, in which:
the characteristic patterns of the grid structure unit and the Schottky rectifying unit are transferred to a workpiece by the same or the same series of photomasks.
Further, the preparation process of the circuit can comprise M photomasks, wherein the Nth photomask is a step mark photomask, the R-S photomasks are used for synchronizing with the transfer process of the shielding grid characteristic patterns and forming the characteristic patterns of the Schottky rectifying circuit, N is more than or equal to R is more than or equal to M, M is more than or equal to N, and M, N, R and S are positive integers.
The voltage converting circuit shown in fig. 17 is subjected to chopper processing by the rectifying circuit disclosed by the invention, wherein the rectifying circuit arranged in a MOSFET at the low side 1000 of the converter or the rectifying circuit directly obtained according to the method of the invention further comprises an external auxiliary circuit shown in fig. 17 for completing the step-up or step-down conversion, the rectifying circuit comprises a schottky rectifying circuit integrated in the converter and a MOSFET parasitic body diode manufactured by synchronous integration, the schottky rectifying circuit is connected with the parasitic body diode in parallel, the auxiliary circuit comprises a voltage converting output end 2000, an inductance unit 3000, a high-side low-side junction point 3200 of the auxiliary circuit is connected to the voltage converting output end 2000 through an inductance 3200, one end of the high-side MOSFET4000 is connected with the voltage converting input end 5000, the other end is connected with the high-side low-side junction point 3200, and the control circuit power end 6000 is a power control circuit 7000.
The power supply adopting the circuit has similar switching characteristics and working performances based on the principle, and the specific technical scheme is not repeated.
It should be noted that the foregoing examples are merely for clarity of illustration of the technical solution of the present invention, and those skilled in the art will understand that the embodiments of the present invention are not limited to the foregoing, and that obvious changes, substitutions or alterations made herein do not depart from the scope of the present invention without departing from the spirit of the present invention.
Claims (11)
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| CN103400840A (en) * | 2013-07-01 | 2013-11-20 | 中航（重庆）微电子有限公司 | Super barrier rectifier and preparation method thereof |
| CN106601811A (en) * | 2015-10-19 | 2017-04-26 | 大中积体电路股份有限公司 | Trench type power transistor |
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| US8148749B2 (en) * | 2009-02-19 | 2012-04-03 | Fairchild Semiconductor Corporation | Trench-shielded semiconductor device |
| CN109742141A (en) * | 2018-12-03 | 2019-05-10 | 北京大学深圳研究生院 | A kind of GaN-based HEMT device and preparation method thereof |
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| CN103400840A (en) * | 2013-07-01 | 2013-11-20 | 中航（重庆）微电子有限公司 | Super barrier rectifier and preparation method thereof |
| CN106601811A (en) * | 2015-10-19 | 2017-04-26 | 大中积体电路股份有限公司 | Trench type power transistor |
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