TWI859673B - Semiconductor device - Google Patents

Abstract

This invention provides a semiconductor device which comprises an active layer, a first semiconductor layer, a first strain-release structure positioned between the active layer and the first semiconductor layer, and an intermediate layer positioned between the first strain-release structure and the active layer. The strain-release structure comprises plural first sub-layers and plural second sub-layers alternately stacked. The band gap of the second sub-layer is smaller than the band gap of the first sub-layer. The intermediate layer comprises a first portion connected to the first strain-release layer and a second portion connected to the active layer, wherein the second portion and the second sub-layer each comprises an indium composition and the indium composition of the second portion is smaller than that of the second sub-layer.

Description

Semiconductor components

The present invention relates to a semiconductor device, and in particular to a semiconductor device having an intermediate layer.

III-V compound semiconductors have been widely developed and applied in various electronic devices, such as high electron-mobility transistors (HEMT), high-efficiency photovoltaic devices, and light-emitting diodes (LED).

Take LEDs as an example. LEDs have been considered as one of the best solutions to replace traditional light sources. In order to further achieve the effect of energy saving and carbon saving, brightness improvement has been a long-term research topic for researchers in this field. The brightness improvement of LEDs is mainly divided into two parts. One is the improvement of internal quantum efficiency (IQE), which is mainly achieved by improving the structure of epitaxial thin films to enhance the electron-hole combination efficiency. The other is the improvement of light extraction efficiency (LEE), which mainly focuses on enabling the light emitted by the active layer to effectively penetrate the outside of the device and reduce the light absorption by the internal structure of the LED.

The present invention aims to improve the quality of the epitaxial thin film structure of III-V compound semiconductor devices, thereby improving the performance of semiconductor devices, such as improving the internal quantum efficiency of light-emitting diodes.

The present invention provides a semiconductor element, which includes an active layer, a first semiconductor layer, a first stress buffer structure located between the active layer and the first semiconductor layer, and an intermediate layer located between the first stress buffer structure and the active layer, wherein the first stress buffer structure includes a plurality of first sublayers and a plurality of second sublayers overlapping each other, the energy gap of the second sublayer is smaller than the energy gap of the first sublayer, the intermediate layer includes a first portion adjacent to the first stress buffer structure and a second portion adjacent to the active layer, the second portion and the second sublayer each include an indium content, and the indium content of the second portion is smaller than the indium content of the second sublayer. In another embodiment of the present invention, the semiconductor device further comprises a second stress buffer structure located between the second portion and the active layer, wherein the second stress buffer structure comprises a plurality of third sub-layers and a plurality of fourth sub-layers overlapping each other, and the energy gap of the fourth sub-layer is smaller than the energy gap of the third sub-layer.

1, 2: Semiconductor components

10: Substrate

20: First semiconductor layer

31: First stress buffer structure

311: First sublayer

312: Second sublayer

32: Second stress buffer structure

321: The third sublayer

322: The fourth sublayer

40: Middle layer

401: Part 1

402: Part 2

50: Active layer

501: Barrier layer

502: Well layer

60: Second semiconductor layer

71: First electrode

72: Second electrode

Figure 1 is a schematic diagram showing the first embodiment of the semiconductor device according to the present invention.

Figure 2 is a schematic diagram showing a second embodiment of the semiconductor device according to the present invention.

FIG. 1 discloses a first embodiment of a semiconductor device according to the present invention. The semiconductor device 1 includes a substrate 10, a first semiconductor layer 20 formed on the substrate 10, a first stress buffer structure 31 formed on the first semiconductor layer 20, an intermediate layer 40 formed on the first stress buffer structure 20, an active layer 50 formed on the intermediate layer 40, a second semiconductor layer 60 formed on the active layer 50, a first electrode 71 electrically connected to the first semiconductor layer 20, and a second electrode 72 electrically connected to the second semiconductor layer 60. In one embodiment of the present invention, the first semiconductor layer 20 includes a first region and a second region, the first stress buffer layer 31 is formed on the first region, and the first electrode 71 is formed on the second region, thereby being electrically connected to the first semiconductor layer 20; wherein, there is no first stress buffer structure 31, intermediate layer 40, active layer 50, and second semiconductor layer 60 between the second region and the first electrode 71.

x

0.25)並具有一厚度介於1~5nm之間，阻障層501例如包含摻 雜或非故意摻雜之GaN及/或Al_xGa_1-xN(0.01

x

0.1)並且具有一厚度介於5~15nm之間。 In one embodiment of the present invention, the substrate 10, the first semiconductor layer 20, the first stress buffer structure 31, the intermediate layer 40, the active layer 50 and the second semiconductor layer 60 all include single crystal epitaxial structures. Each epitaxial structure is preferably formed by metal organic vapor deposition (MOCVD), and the material composition of each epitaxial structure can be adjusted by changing the flow rate of each reactant introduced into the reactor when forming the epitaxial structure and/or the temperature of the reactor. The difference between the lattice constant of the substrate 10 and the lattice constant of the first semiconductor layer 20 is not less than 1% of the lattice constant of the substrate 10, wherein the material of the substrate 10 includes sapphire, for example. The first semiconductor layer 20 includes a III-V compound with a first conductivity type, such as n-type gallium nitride (GaN) and an n-type dopant (such as silicon) and an n-type dopant concentration between 1*10 ¹⁸ and 5*10 ¹⁸ cm ^-3 . The second semiconductor layer 60 includes a III-V compound with a second conductivity type, such as p-type GaN and a p-type dopant (such as magnesium) and a p-type dopant concentration between 1*10 ¹⁹ and 5*10 ²⁰ cm ^-3 , wherein the second conductivity type is opposite to the first conductivity type. When the semiconductor device 1 is a light emitting diode (LED), the active layer 50 includes, for example, a III-V compound and a multiple quantum well (MQW) structure, wherein the multiple quantum well structure includes a plurality of barrier layers 501 and a plurality of well layers 502 stacked alternately, and emits visible light or invisible light when driven, wherein the number of overlapping pairs is between 3 and 15 pairs. The material of the well layer 502 has an energy band gap corresponding to the wavelength of the emitted light and smaller than the energy band gap of the barrier layer 501, and the well layer 502 includes, for example, unintentionally doped In _x Ga _1-x N (0.05

x

0.25) and has a thickness between 1 and 5 nm. The barrier layer 501 may include, for example, doped or unintentionally doped GaN and/or Al _x Ga _1-x N (0.01

x

0.1) and has a thickness between 5 and 15 nm.

x

0.03)；第一子層311之材料包含第一導電型的III-V族化合物，例如包含n型GaN或n型In_xGa_1-xN(0.001

x

0.01)且具有一n型摻雜質(例如為矽)以及一n型摻雜濃度介於10¹⁷cm^-3~10¹⁸cm^-3之間，其中，第一子層311不包含銦或包含一銦含量小於第二子層312之銦含量。第一子層311具有一厚度介於10~50nm之間；第二子層312具有一厚度介於0.5~3nm之間；第一應力緩衝結構31具有一厚度介於50~500nm之間。 In one embodiment of the present invention, the first stress buffer structure 31 includes, for example, a plurality of first sub-layers 311 and a plurality of second sub-layers 312 alternately stacked to form a superlattice structure, wherein the number of overlapping pairs is between 3 and 10 pairs; wherein the second sub-layer 312 closest to the middle layer 40 is directly connected to the middle layer 40; wherein the material of the second sub-layer 312 includes an unintentionally doped III-V compound, such as In _x Ga _1-x N (0.01

x

0.03); the material of the first sublayer 311 includes a III-V compound of the first conductivity type, such as n-type GaN or n-type In _x Ga _1-x N (0.001

x

0.01) and having an n-type dopant (e.g., silicon) and an n-type dopant concentration between 10 ¹⁷ cm ^-3 and 10 ¹⁸ cm ^-3 , wherein the first sublayer 311 does not contain indium or contains an indium content less than that of the second sublayer 312. The first sublayer 311 has a thickness between 10 and 50 nm; the second sublayer 312 has a thickness between 0.5 and 3 nm; and the first stress buffer structure 31 has a thickness between 50 and 500 nm.

0.01)；第二部分402直接與第一部分401相接，其材料例如包含In_xGa_1-xN(0.001

x

0.02)且具有一銦含量大於第一部分401之銦含量。於本發明之一實施例，第二部分402之銦含量小於第二子層312之銦含量以降低第一應力緩衝結構31與主動層50之間所產生的壓應力(piezoelectric strain)。中間層40具有一厚度小於100nm；較佳地介於30nm至90nm之間；其中，第一部分401具有一厚度介於10nm至50nm之間，第二部分402具有一厚度介於0.5nm至15nm之間；其中，第二部分402之厚度與中間層40厚度之比值介於0.1至0.5之間。於本發明之一實施例，第二部分402之銦含 量小於第二子層312之銦含量，且第二部分402之厚度大於或等於第二子層312之厚度以進一步降低第一應力緩衝結構31與主動層50之間所產生的壓應力。第一部分401及第二部分402各具有一n型摻雜質(例如為矽)以及一n型摻雜濃度介於10¹⁸cm^-3及10¹⁹cm^-3之間。較佳地，第二部分402之n型摻雜濃度大於第一部分401之n型摻雜濃度。於本發明之一實施例，中間層40之厚度小於第一應力緩衝結構31之厚度。 In one embodiment of the present invention, the intermediate layer 40 includes a first portion 401 adjacent to the first stress buffer structure 31 and a second portion 402 adjacent to the active layer 50; the first portion 401 does not contain indium or contains an indium content less than that of the second portion 402, for example, GaN or In _x Ga _1-x N (0<x

0.01); the second portion 402 is directly connected to the first portion 401, and its material includes, for example, _{InxGa1 -xN} (0.001

x

0.02) and has an indium content greater than that of the first portion 401. In one embodiment of the present invention, the indium content of the second portion 402 is less than that of the second sublayer 312 to reduce the piezoelectric strain generated between the first stress buffer structure 31 and the active layer 50. The intermediate layer 40 has a thickness less than 100 nm; preferably between 30 nm and 90 nm; wherein the first portion 401 has a thickness between 10 nm and 50 nm, and the second portion 402 has a thickness between 0.5 nm and 15 nm; wherein the ratio of the thickness of the second portion 402 to the thickness of the intermediate layer 40 is between 0.1 and 0.5. In one embodiment of the present invention, the indium content of the second portion 402 is less than the indium content of the second sub-layer 312, and the thickness of the second portion 402 is greater than or equal to the thickness of the second sub-layer 312 to further reduce the compressive stress generated between the first stress buffer structure 31 and the active layer 50. The first portion 401 and the second portion 402 each have an n-type dopant (e.g., silicon) and an n-type dopant concentration between 10 ¹⁸ cm ^-3 and 10 ¹⁹ cm ^-3 . Preferably, the n-type dopant concentration of the second portion 402 is greater than the n-type dopant concentration of the first portion 401. In one embodiment of the present invention, the thickness of the intermediate layer 40 is less than the thickness of the first stress buffer structure 31.

0.02)，第四子層322之材料例如包含In_xGa_1-xN(0.03

x

0.1)，其中，第四子層322之銦含量大於第二子層312之銦含量。其中，第三子層321具有一n型摻雜質(例如為矽)以及一n型摻雜濃度介於10¹⁷cm^-3~10¹⁸cm^-3之間。中間層之第二部分402之n型摻雜濃度大於第三子層321之n型摻雜濃度以降低第一應力緩衝結構31與主動層50之間所產生的壓應力。較佳地，第二部分402之n型摻雜濃度大於第一部分401之n型摻雜濃度以及第二部402之n型摻雜濃度大於第三子層321之n型摻雜濃度以進一步降低第一應力緩衝結構31與主動層50之間所產生的壓應力。第三子層321具有一厚度介於5~10nm之間；第四子層322具有一厚度介於0.5~3nm之間；第二應力緩衝結構32具有一厚度介於30~80nm之間。於本發明之一實施例，中間層40之厚度相當於或大於第二應力緩衝結構32之厚度，並且中間層40之厚度小於第一應力緩衝結構31之厚度。本實施例其餘結構之描述相同於實施例一，即第2圖與第1圖具有相同標號之結構代表彼此為相同之結構，並已詳細描述於實施例一，不在此贅述。 FIG. 2 discloses a second embodiment of the semiconductor device according to the present invention. The semiconductor device 2 includes a substrate 10, a first semiconductor layer 20 formed on the substrate 10, a first stress buffer structure 31 formed on the first semiconductor layer 20, an intermediate layer 40 formed on the first stress buffer structure 20, a second stress buffer structure 32 formed on the intermediate layer 40, an active layer 50 formed on the second stress buffer structure 32, a second semiconductor layer 60 formed on the active layer 50, a first electrode 71 electrically connected to the first semiconductor layer 20, and a second electrode 72 electrically connected to the second semiconductor layer 60. In one embodiment of the present invention, the first semiconductor layer 20 includes a first region and a second region, the first stress buffer layer 31 is formed on the first region; the first electrode 71 is formed on the second region, thereby being electrically connected to the first semiconductor layer 20; wherein, the first stress buffer structure 31, the intermediate layer 40, the second stress buffer structure 32, the active layer 50, and the second semiconductor layer 60 are not provided between the second region and the first electrode 71. The difference between the second embodiment and the first embodiment is that the semiconductor device 2 includes not only all the structures of the semiconductor device 1, but also a second stress buffer structure 32 formed between the intermediate layer 40 and the active layer 50, wherein the second stress buffer structure 32 includes a single crystal epitaxial structure, and the second stress buffer structure 32 includes, for example, a plurality of third sub-layers 321 and a plurality of fourth sub-layers 322 alternately stacked to form a super lattice structure, wherein the number of overlapping pairs is between 3 and 10 pairs. In one embodiment of the present invention, the fourth sublayer 321 closest to the active layer 50 is directly connected to a barrier layer 501 of the active layer 50; the third sublayer 321 closest to the intermediate layer 40 is directly connected to the second portion 402 of the intermediate layer 40. The indium content of the fourth sublayer 322 of the second stress buffer structure 32 is greater than the indium content of the second sublayer 322 of the first stress buffer structure 31, wherein the third sublayer 321 does not contain indium or contains an indium content less than the indium content of the fourth sublayer 322; the material of the third sublayer 321, for example, includes GaN or In _x Ga _1-x N (0<x

0.02), the material of the fourth sub-layer 322 includes, for example, _{InxGa1 -xN} (0.03

x

0.1), wherein the indium content of the fourth sublayer 322 is greater than the indium content of the second sublayer 312. wherein the third sublayer 321 has an n-type dopant (e.g., silicon) and an n-type dopant concentration between 10 ¹⁷ cm ^-3 and 10 ¹⁸ cm ^-3 . the n-type dopant concentration of the second portion 402 of the intermediate layer is greater than the n-type dopant concentration of the third sublayer 321 to reduce the compressive stress generated between the first stress buffer structure 31 and the active layer 50. Preferably, the n-type doping concentration of the second portion 402 is greater than the n-type doping concentration of the first portion 401 and the n-type doping concentration of the second portion 402 is greater than the n-type doping concentration of the third sublayer 321 to further reduce the compressive stress generated between the first stress buffer structure 31 and the active layer 50. The third sublayer 321 has a thickness between 5 and 10 nm; the fourth sublayer 322 has a thickness between 0.5 and 3 nm; and the second stress buffer structure 32 has a thickness between 30 and 80 nm. In one embodiment of the present invention, the thickness of the intermediate layer 40 is equal to or greater than the thickness of the second stress buffer structure 32, and the thickness of the intermediate layer 40 is less than the thickness of the first stress buffer structure 31. The description of the remaining structures of this embodiment is the same as that of the first embodiment, that is, the structures with the same reference numerals in FIG. 2 and FIG. 1 represent the same structures and have been described in detail in the first embodiment, which will not be repeated here.

The present invention can effectively reduce the compressive stress of semiconductor components, reduce the forward voltage and improve the luminous efficiency. The various embodiments listed in the present invention are only used to illustrate the present invention and are not used to limit the scope of the present invention. Any obvious modifications or changes made by anyone to the present invention do not deviate from the spirit and scope of the present invention.

1:Semiconductor components

10: Substrate

20: First semiconductor layer

31: First stress buffer structure

311: First sublayer

312: Second sublayer

40: Middle layer

401: Part 1

402: Part 2

50: Active layer

501: Barrier layer

502: Well layer

60: Second semiconductor layer

71: First electrode

72: Second electrode

Claims (10)

A semiconductor element, comprising: an active layer; a first semiconductor layer; a first stress buffer structure, located between the active layer and the first semiconductor layer, the first stress buffer structure comprising one or more first sublayers and one or more second sublayers, and the one or more first sublayers comprising an indium content less than an indium content of the one or more second sublayers; an intermediate layer, located between the first stress buffer structure and the active layer, comprising an indium content less than the indium content of the one or more second sublayers; and A second stress buffer structure is located between the intermediate layer and the active layer, wherein the second stress buffer structure includes a plurality of third sublayers and a plurality of fourth sublayers overlapping each other, the plurality of third sublayers contain an indium content less than an indium content contained in the plurality of fourth sublayers, and the indium content contained in the plurality of fourth sublayers is greater than the indium content of the one or more second sublayers. The semiconductor device as described in claim 1, wherein the intermediate layer includes a first portion adjacent to the first stress buffer structure and a second portion adjacent to the second stress buffer structure, and the indium content included in the second portion is greater than the indium content included in the first portion. A semiconductor device as described in claim 2, wherein the second portion comprises an indium content that is less than the indium content of the one or more second sub-layers. The semiconductor device as claimed in claim 1, wherein the intermediate layer comprises an n-type doping concentration between 10 ¹⁸ cm ^{-3 and} 10 ¹⁹ cm ^-3 . A semiconductor device as described in claim 1, wherein the intermediate layer comprises a thickness less than a thickness of the first stress buffer structure. As described in claim 1, the plurality of first sub-layers and the plurality of second sub-layers of the first stress buffer structure overlap each other, and the number of overlapping pairs is between 3 and 10 pairs. As described in claim 6, the plurality of first sub-layers each have a thickness between 10 and 50 nm, and the plurality of second sub-layers each have a thickness between 0.5 and 3 nm. In the semiconductor device as described in claim 1, the intermediate layer comprises a thickness less than 100 nm. The semiconductor device as claimed in claim 1, wherein the second stress buffer structure comprises an n-type doping concentration between 10 ¹⁷ cm ^{-3 and} 10 ¹⁸ cm ^-3 . The semiconductor element as described in item 1 of the patent application scope includes a second semiconductor layer formed on the active layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the second semiconductor layer, wherein the first semiconductor layer includes a first region and a second region, the first stress buffer structure is formed on the first region, the first electrode is formed on the second region, and the first stress buffer structure is not provided between the second region and the first electrode.