CN110854246A - Light-emitting diode and light-emitting diode manufacturing method - Google Patents

Abstract

The application provides a light-emitting diode and a preparation method thereof. Each sub-layer structure includes a first quantum well structure and a plurality of second quantum well structures. The first quantum well structure replaces a conventional quantum barrier layer structure. The second quantum well structures are arranged on the first quantum well structure to form a deeper quantum well structure. And the thickness of each second quantum well structure is less than the thickness of the first quantum well structure, such that the second quantum well structures form a narrow quantum well structure compared to the first quantum well structure. At this time, the quantum barrier in the conventional structure is replaced with the first quantum well structure. A plurality of sub-layer deep and narrow multi-quantum well structures are formed in the multi-quantum well layer through the plurality of second quantum well structures, and compared with the traditional quantum well, the multi-quantum well structure is deeper, so that the quantum well has better limiting capacity on electrons and holes, the half width of the light-emitting wavelength is reduced, and a specified waveband with purer wave color and stronger light-emitting intensity is generated.

Description

Light-emitting diode and light-emitting diode manufacturing method

technical field

The present application relates to the technical field of semiconductors, and in particular, to a light-emitting diode and a method for manufacturing the light-emitting diode.

Background technique

Light-Emitting Diode (LED) is a semiconductor electronic component that can convert electrical energy into light energy. It is very popular due to its advantages of small size, low energy consumption, long life, and low driving voltage. Epitaxial wafers are the basic structures for preparing light-emitting diodes. The structure of a conventional light emitting diode epitaxial wafer includes a substrate and a low temperature buffer layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, and a P-type GaN layer sequentially grown on the substrate. The multi-quantum well layer includes alternately grown InGaN well layers and GaN barrier layers. Under the action of current, electrons in the N-type GaN layer and holes in the P-type GaN layer will migrate to the multi-quantum well layer and conduct Compound luminescence.

However, due to the small effective mass and high mobility of electrons, electrons can easily cross the GaN barrier and reach the P-type layer for non-radiative recombination with holes. The concentration and injection efficiency of holes are reduced, making the light-emitting diodes luminous efficiency decreased.

SUMMARY OF THE INVENTION

Based on this, it is necessary to provide a light-emitting diode and a method for fabricating a light-emitting diode in order to solve the problem of reducing the luminous efficiency caused by the reduction of hole concentration and injection efficiency in the conventional light-emitting diode epitaxial wafer.

The application provides a light-emitting diode including a substrate, a buffer layer, a gallium nitride layer, an N-type semiconductor layer, a multiple quantum well layer, and a P-type semiconductor layer. The buffer layer, the gallium nitride layer, the N-type semiconductor layer and the P-type semiconductor layer are sequentially stacked on the surface of the substrate. The multiple quantum well layer is stacked between the N-type semiconductor layer and the P-type semiconductor layer. The multiple quantum well layer includes at least one sublayer structure. The sub-layer structure is disposed on the surface of the N-type semiconductor layer away from the gallium nitride layer. Each of the sub-layer structures includes a first quantum well structure and a plurality of second quantum well structures, the first quantum well structures are disposed on the surface of the N-type semiconductor layer away from the gallium nitride layer, the plurality of A plurality of second quantum well structures are sequentially disposed on the surface of the first quantum well structure away from the N-type semiconductor layer, and the thickness of each of the second quantum well structures is smaller than that of the first quantum well structure.

In one embodiment, the first quantum well structure includes a quantum barrier layer. The quantum barrier layer is disposed on the surface of the N-type semiconductor layer away from the gallium nitride layer. The first potential well layer is disposed on the surface of the quantum barrier layer away from the N-type semiconductor layer.

In one embodiment, the quantum barrier layer is Al _m In _n Ga _1-mn N, wherein 0<m<0.6 and 0<n<0.2. The first potential well layer is In _x Ga _1-x N, where 0.2<x<0.22.

In one embodiment, the quantum barrier layer has a thickness of 100 nm to 140 nm. The thickness of the first potential well layer is 2 nm˜6 nm.

In one embodiment, each of the second quantum well structures includes a first potential barrier layer and a second potential well layer. The first potential barrier layer is disposed on the surface of the first potential well layer away from the quantum barrier layer. The second potential well layer is disposed on a surface of the first potential barrier layer away from the first potential well layer.

In one embodiment, the first barrier layer is In _y Ga _1-y N, where 0<y<0.1. The second potential well layer is In _x Ga _1-x N, where 0.2<x<0.22.

In one embodiment, the thickness of the first barrier layer is 4 nm˜8 nm. The thickness of the second potential well layer is 2 nm˜6 nm.

In one embodiment, a method for fabricating a light-emitting diode includes:

S10, providing a substrate, and sequentially preparing a buffer layer, a gallium nitride layer and an N-type semiconductor layer on the surface of the substrate;

S20, setting the growth temperature to be 850°C to 950°C, and preparing a quantum barrier layer on the surface of the N-type semiconductor layer away from the gallium nitride layer;

S30 , setting the growth temperature to be 700° C.˜800° C., and preparing a first potential well layer on the surface of the quantum barrier layer away from the N-type semiconductor layer;

S40 , setting the growth temperature to be 750° C.˜850° C., preparing a first potential barrier layer on the surface of the first potential well layer away from the quantum barrier layer, and on the surface of the first potential well layer away from the first potential barrier layer preparing a second potential well layer on the surface of the well layer; and

S50 , according to the step S40 , on the surface of the second potential well layer far from the first potential barrier layer, the second quantum well structure is prepared by cycling 3 to 6 times in sequence.

In one embodiment, the quantum barrier layer and the first potential well layer form a first quantum well structure, the first potential barrier layer and the second potential well layer form a second quantum well structure, and the The first quantum well structure and the plurality of second quantum well structures form a sublayer structure. The light-emitting diode manufacturing method further includes:

S60, according to the steps S20-S50, prepare 8-15 layers of the sub-layer structure on the surface of the N-type semiconductor layer away from the gallium nitride layer;

Wherein, a plurality of the sub-layer structures form a multiple quantum well layer.

In one embodiment, the light-emitting diode manufacturing method further includes:

S70 , setting the growth temperature to be 900° C.˜1000° C., and preparing a magnesium-doped high-temperature P-type semiconductor layer on the surface of the multiple quantum well layer away from the N-type semiconductor layer.

The present application provides the above-mentioned light emitting diode. The multiple quantum well layer is disposed on the surface of the N-type semiconductor layer away from the gallium nitride layer. The multiple quantum well layer includes one or more of the sub-layer structures, and the multiple quantum well layer can be formed at a deeper level on the surface of the N-type semiconductor layer. Meanwhile, each of the sub-layer structures includes a first quantum well structure and a plurality of second quantum well structures. The first quantum well structure replaces the traditional quantum barrier layer structure. The plurality of second quantum well structures are disposed on the first quantum well structures to form deeper quantum well structures. Also, the thickness of each of the second quantum well structures is smaller than the thickness of the first quantum well structures, so that the second quantum well structures form a narrow quantum well structure compared to the first quantum well structures.

At this time, the quantum barrier in the conventional structure is replaced with the first quantum well structure. At the same time, a plurality of sub-layer deep and narrow multiple quantum well structures are formed in the multiple quantum well layer through the multiple second quantum well structures. Therefore, the multiple quantum well layer includes a plurality of deep and narrow multiple quantum well structures. Furthermore, compared with the traditional quantum well, the multiple deep and narrow multiple quantum well structure becomes deeper, so that the quantum well can better confine electrons and holes, reduce the half-width of the emission wavelength, and generate purer wavelengths. , the specified band with stronger luminous intensity.

Description of drawings

1 is a schematic structural diagram of a light-emitting diode provided by the application;

2 is a schematic structural diagram of a sublayer structure provided by the present application;

3 is a schematic structural diagram of a multiple quantum well layer provided by the present application;

4 is a schematic diagram of the alternate stacking of multiple quantum well layers provided by the present application;

FIG. 5 is a schematic flowchart of a method for manufacturing a light emitting diode provided by the present application.

Description of reference numerals

Light emitting diode 100, substrate 10, buffer layer 20, gallium nitride layer 30, N-type semiconductor layer 40, multiple quantum well layer 50, sublayer structure 501, first quantum well structure 510, second quantum well structure 520, quantum well The barrier layer 511 , the first potential well layer 512 , the first potential barrier layer 521 , the second potential well layer 522 , and the P-type semiconductor layer 60 .

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application will be further described in detail below through embodiments and in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

The serial numbers themselves, such as "first", "second", etc., for the components herein are only used to distinguish the described objects, and do not have any order or technical meaning. The "connection" and "connection" mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections). In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", The orientation or positional relationship indicated by "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description , rather than indicating or implying that the referred device or element must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as a limitation on the present application.

In this application, unless otherwise expressly stated and defined, a first feature "on" or "under" a second feature may be in direct contact with the first and second features, or the first and second features indirectly through an intermediary touch. Also, the first feature being "above", "over" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is level higher than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.

Referring to FIGS. 1-4 , the present application provides a light emitting diode 100 including a substrate 10 , a buffer layer 20 , a gallium nitride layer 30 , an N-type semiconductor layer 40 , a multiple quantum well layer 50 and a P-type semiconductor layer 60 . The buffer layer 20 , the gallium nitride layer 30 , the N-type semiconductor layer 40 and the P-type semiconductor layer 60 are sequentially stacked on the surface of the substrate 10 . The multiple quantum well layer 50 is stacked between the N-type semiconductor layer 40 and the P-type semiconductor layer 60 . The multiple quantum well layer 50 includes at least one sublayer structure 501 . The sub-layer structure 501 is disposed on the surface of the N-type semiconductor layer 40 away from the gallium nitride layer 30 . Each of the sub-layer structures 501 includes a first quantum well structure 510 and a plurality of second quantum well structures 520 . The first quantum well structure 510 is disposed on the surface of the N-type semiconductor layer 40 away from the gallium nitride layer 30 . The plurality of second quantum well structures 520 are sequentially disposed on the surface of the first quantum well structure 510 away from the N-type semiconductor layer 40 . And the thickness of each of the second quantum well structures 520 is smaller than the thickness of the first quantum well structures 510 .

The multiple quantum well layer 50 is disposed on the surface of the N-type semiconductor layer 40 away from the gallium nitride layer 30 . The multiple quantum well layer 50 includes one or more of the sub-layer structures 501 , and the multiple quantum well layer 50 can be formed at a deeper level on the surface of the N-type semiconductor layer 40 . Meanwhile, each of the sub-layer structures 501 includes a first quantum well structure 510 and a plurality of second quantum well structures 520 . The first quantum well structure 510 replaces the traditional quantum barrier layer structure. The plurality of second quantum well structures 520 are disposed on the first quantum well structure 510 to form deeper quantum well structures. In addition, the thickness of each of the second quantum well structures 520 is smaller than the thickness of the first quantum well structures 510 , so that the second quantum well structures 520 form narrow quantum well structures compared with the first quantum well structures 510 well structure.

At this time, the quantum barrier in the conventional structure is replaced with the first quantum well structure 510 . At the same time, through the plurality of second quantum well structures 520 , a plurality of sub-layer deep and narrow multi-quantum well structures are formed in the multi-quantum well layer 50 . Therefore, the multiple quantum well layer 50 includes a plurality of deep and narrow multiple quantum well structures. Furthermore, compared with the traditional quantum well, the multiple deep and narrow multiple quantum well structure becomes deeper, so that the quantum well can better confine electrons and holes, reduce the half-width of the emission wavelength, and generate purer wavelengths. , the specified band with stronger luminous intensity.

Referring to FIG. 2 , in one embodiment, the first quantum well structure 510 includes a quantum barrier layer 511 and a first potential well layer 512 . The quantum barrier layer 511 is disposed on the surface of the N-type semiconductor layer 40 away from the gallium nitride layer 30 . The first potential well layer 512 is disposed on the surface of the quantum barrier layer 511 away from the N-type semiconductor layer 40 .

The quantum barrier layer 511 is disposed on the surface of the N-type semiconductor layer 40 away from the gallium nitride layer 30 , replacing the quantum barrier in the conventional structure. At the same time, the first potential well layer 512 is disposed on the quantum barrier layer 511 . Further, the plurality of second quantum well structures 520 are disposed on the first potential well layer 512 . Through the quantum barrier layer 511, the first potential well layer 512 and the plurality of second quantum well structures 520, a plurality of deep and narrow multi-quantum well structures can be formed, which are deeper than the traditional quantum well structure, so that the quantum wells The ability to confine electrons and holes is better, the half-width of the luminescent wavelength is reduced, and the specified wavelength band with purer wave color and stronger luminous intensity is generated.

In one embodiment, the quantum barrier layer 511 is Al _m In _n Ga _1-mn N, where 0<m<0.6 and 0<n<0.2. The first potential well layer 512 is In _x Ga _1-x N, where 0.2<x<0.22.

The traditional quantum barrier structure is replaced by the quantum barrier layer 511 of _{AlmInnGa1 -mnN ,} and the first potential well layer 512 of InxGa1 _{-xN is} arranged on the quantum barrier layer 511, forming the first potential well layer 512 of InxGa1-xN. A quantum well structure 510 . Among them, the Al _m In _n Ga _1-mn N structure prepared at high temperature provides a high energy level, which is a quantum barrier for high lattice matching and high lattice quality.

Due to the small effective mass and high mobility of electrons, in the traditional light-emitting diode structure, electrons can easily cross the GaN barrier and reach the P-type layer for non-radiative recombination with holes, which makes the concentration of holes and the injection of holes occur. Efficiency is reduced. The movement of electrons can be effectively slowed down by the high-energy quantum barrier layer 511 composed of Al _m In _n Ga _1-mn N in this embodiment. At the same time, a plurality of second quantum well structures 520 are arranged on the surface of the quantum barrier layer 511 of the Al _m In _n Ga _1-mn N, so that a deep and narrow multiple quantum well structure can be formed, which can further improve the quantum well's resistance to electrons and holes. Limit capacity and improve luminous efficiency.

Referring to FIG. 2 , in one embodiment, each of the second quantum well structures 520 includes a first barrier layer 521 and a second potential well layer 522 . The first potential barrier layer 521 is disposed on the surface of the first potential well layer 512 away from the quantum barrier layer 511 . The second potential well layer 522 is disposed on the surface of the first potential barrier layer 521 away from the first potential well layer 512 .

The second quantum well structure 520 is formed by the first barrier layer 521 and the second potential well layer 522 . Wherein, the thickness of each of the second quantum well structures 520 is smaller than the thickness of the first quantum well structures 510 . Since the thickness has a great influence on the polarization, at this time, by reducing the thicknesses of the first potential barrier layer 521 and the second potential well layer 522, the influence of the polarization can be reduced. Therefore, polarization is reduced by reducing the thickness of the well barrier of the monolayer. In addition, the first potential barrier layer 521 and the second potential well layer 522 are both composed of InGaN, and the lattice matching between the same materials is better, thereby improving the luminous efficiency of the light emitting diode 100 .

Due to the lattice mismatch between the GaN barrier layer and the InGaN well layer of the multi-quantum well layer in traditional light-emitting diodes, the polarization effect is large, which reduces the overlap of wave functions and the probability of radiative recombination, which reduces the luminous efficiency. The sub-layer quantum well structure formed by alternately stacking multiple first potential barrier layers 521 and multiple second potential well layers 522 in this embodiment makes the lattice matching between the sub-layer quantum well and the sub-layer quantum barrier better, Reduce polarization effect and improve luminous efficiency.

At the same time, the first potential barrier layer 521 is disposed on the surface of the first potential well layer 512, and the first potential well layer 512 is also composed of InGaN, so that the first potential well layer 512 is connected to the first potential well layer 512. The lattice matching between the barrier layers 521 is better. At this time, through the quantum barrier layer 511 of _{AlmInnGa1 -mnN ,} the first potential well layer 512 of InxGa1 _{- xN} , the first barrier layer 521 of InyGa1 _{-yN ,} and the In The second potential well layer 522 of xGa _{1-xN forms} the multiple quantum well layer 50 . The multiple quantum well layer 50 has the advantages of good lattice matching and little influence of polarization, which improves the luminous efficiency of the light emitting diode 100 .

In addition, by including a plurality of the second quantum well structures 520 in the sub-layer structure 501, a structure of deep and narrow multiple quantum wells can be formed. The multiple quantum well layer 50 includes a plurality of the sublayer structures 501, that is, the quantum barrier layer 511 including the _{AlmInnGa1 -mnN quantum} barrier layer 511 and the first potential of InxGa1 _{-xN arranged} in multiple cycles. The well layer 512, the first barrier layer 521 of InyGa1 _{- yN} , and the second potential well layer 522 of InxGa1 _{-xN make} the quantum well better in confinement ability of electrons and holes, reducing the The half-width of the luminous wavelength, resulting in a specified band with purer wavelengths and stronger luminous intensity.

In one embodiment, the first barrier layer 521 is In _y Ga _1-y N, where 0<y<0.1. The second potential well layer 522 is In _x Ga _1-x N, where 0.2<x<0.22.

The first potential barrier layer 521 and the second potential well layer 522 are both composed of InGaN, and the lattice matching between the same materials is better, thereby improving the luminous efficiency of the light emitting diode 100 . The first potential well layer 512 is also composed of InGaN, so that the lattice matching between the first potential well layer 512 and the first potential barrier layer 521 is better.

In one embodiment, the thickness of the quantum barrier layer 511 is 100 nm˜140 nm. The thickness of the first potential well layer 512 is 2 nm˜6 nm. The thickness of the first barrier layer 521 is 4 nm˜8 nm. The thickness of the second potential well layer 522 is 2 nm˜6 nm.

The thickness of the first potential well layer 512 , the first potential well layer 521 and the second potential well layer 522 is smaller than that of the quantum barrier layer 511 , and the thicknesses are also reduced compared to the conventional structure. At this time, by reducing the thickness of the first potential well layer 512 , the first potential barrier layer 521 and the second potential well layer 522 , the influence of polarization can be reduced, and the light emission of the light emitting diode 100 can be improved. efficiency.

Referring to FIG. 5, in one embodiment, a method for fabricating a light emitting diode includes:

S10, a substrate 10 is provided, and a buffer layer 20, a gallium nitride layer 30 and an N-type semiconductor layer 40 are sequentially prepared on the surface of the substrate 10;

S20 , setting the growth temperature to be 850° C.˜950° C., and preparing a quantum barrier layer 511 on the surface of the N-type semiconductor layer 40 away from the gallium nitride layer 30 ;

S30, set the growth temperature to 700°C to 800°C, and prepare a first potential well layer 512 on the surface of the quantum barrier layer 511 away from the N-type semiconductor layer 40 , the quantum barrier layer 511 and the first potential well layer 512 forms a first quantum well structure 510;

S40, set the growth temperature to be 750°C to 850°C, prepare a first barrier layer 521 on the surface of the first potential well layer 512 away from the quantum barrier layer 511, and prepare a first barrier layer 521 on the surface of the first potential well layer 512 away from the quantum barrier layer 511. A second potential well layer 522 is prepared on the surface of the first potential well layer 512, and the first potential barrier layer 521 and the second potential well layer 522 form a second quantum well structure 520;

S50 , according to the step S40 , on the surface of the second potential well layer 522 away from the first potential barrier layer 521 , the second quantum well structure 520 is prepared by cycling 3 to 6 times in sequence;

The first quantum well structure 510 and a plurality of the second quantum well structures 520 form a sub-layer structure 501 .

In the step S10, the substrate 10 is a sapphire substrate, and may also be a Si substrate or a SiC substrate. A GaN buffer layer 20 with a thickness of 25 nm to 35 nm is grown on the surface of the substrate 10 in an environment where the growth temperature is about 550°C. Control the growth temperature from 500°C to 1100°C, and grow a layer of undoped GaN layer on the surface of the buffer layer 20 with a thickness of about 0.5um to 1um to form a U-GaN gallium nitride layer 30 (undoped nitrogen gallium). High-temperature N-GaN (N-type semiconductor layer 40 ) is grown at a growth temperature of 1070°C to 1110°C. Among them, the Si doping concentration is 1.00E19-4.00E19, and the thickness is 0.5 μm-1.0 μm.

In the step S20 , a quantum barrier of Al _m In _n Ga _1-mn N is prepared on the surface of the N-type semiconductor layer 40 away from the gallium nitride layer 30 under the environment where the growth temperature is 850° C.˜950° C. Layer 511. The thickness of the quantum barrier layer 511 of Al _m In _n Ga _1-mn N is 100 nm to 140 nm, 0<m<0.6, and 0<n<0.2.

In the step S30, a first potential well layer of In _x Ga _1-x N is prepared on the surface of the quantum barrier layer 511 away from the N-type semiconductor layer 40 under an environment where the growth temperature is 700° C.˜800° C. 512. Wherein, the thickness of the first potential well layer 512 is 2 nm˜6 nm, and 0.2<x0.22.

In the step S40, a first potential barrier of In _y Ga _1-y N is prepared on the surface of the first potential well layer 512 away from the quantum barrier layer 511 under an environment where the growth temperature is 750° C.˜850° C. Layer 521. Wherein, the thickness of the first barrier layer 521 is 4 nm˜8 nm, 0<y<0.1,

In the step S50 , In _x Ga _1-x N is used as the well of the sub-layer quantum well in the multiple quantum well layer 50 , and In _y Ga _1-y N is used as the sub-layer quantum well in the multiple quantum well layer 50 The barrier is alternately grown for 3-6 cycles to form sub-layer quantum wells (a plurality of second quantum well structures 520).

Through steps S20 to S50, the multiple quantum well layer 50 includes a plurality of deep and narrow multiple quantum wells. The deep and narrow multiple quantum wells are formed by the cycles of InxGa1 _{- xN} /InyGa1 _{-yN for} multiple times, that is, a plurality of the second quantum well structures 520 are formed. The light-emitting diode prepared by the light-emitting diode preparation method has better confinement ability for electrons and holes through the deep and narrow multiple quantum wells, reduces the half-width of the light-emitting wavelength, and produces a light-emitting diode with a purer wave color and a stronger light-emitting intensity. Specifies the band. In addition, the lattice matching between the sublayer quantum well and the sublayer quantum barrier is better through the structure of InxGa1 _{- xN} /InyGa1 _{-yN ( second} quantum well structure), and the polarization effect is reduced, Improve luminous efficiency. Meanwhile, the quantum barrier layer 511 of _{AlmInnGa1 -mnN prepared} at high temperature provides a quantum barrier with high energy level, high lattice matching and high lattice quality.

In one embodiment, the light-emitting diode manufacturing method further includes:

S60 , according to the steps S20 to S50 , the sub-layer structure 501 is prepared by successive cycles 8 to 15 times on the surface of the N-type semiconductor layer 40 away from the gallium nitride layer 30 . That is to say, 8-15 layers of the sub-layer structure 501 are prepared on the surface of the N-type semiconductor layer 40 away from the gallium nitride layer 30 .

Wherein, a plurality of the sub-layer structures 501 form the multiple quantum well layer 50 .

The multiple quantum well layer 50 is formed by preparing a plurality of the sub-layer structures 501 through 8 to 15 cycles in the step S60 . Each of the sublayer structures 501 includes InxGa1 _{- xN} , InyGa1 _{-yN ,} and _{AlmInnGa1 -mnN .} Among them, the _{AlmInnGa1 -m- nN layer} can be doped with Si. Deep and narrow multiple quantum wells are formed by a plurality of the sub-layer structures 501 .

At this time, the multiple quantum well layer 50 obtained through the steps S10 to S60 is prepared. Through the deep and narrow multiple quantum wells, the confinement ability of electrons and holes is better, the half width of the emission wavelength is reduced, and the specified wavelength band with purer wave color and stronger emission intensity is generated.

In one embodiment, the light-emitting diode manufacturing method further includes:

S70 , in an environment where the growth temperature is 900° C.˜1000° C., a magnesium-doped high temperature P-type semiconductor layer 60 is prepared on the surface of the multiple quantum well layer 50 away from the N-type semiconductor layer 40 .

In the step S70, the P-type semiconductor layer 60 is grown and prepared at a growth temperature of 900°C to 1000°C. The P-type semiconductor layer 60 is a Mg-doped high-temperature P-type GaN layer. The thickness of the P-type semiconductor layer 60 is 100 nm˜120 nm.

The light emitting diode 100 obtained by the light emitting diode manufacturing method can emit a specified wavelength band with purer wave color and stronger luminous intensity, and has high luminous efficiency.

In one embodiment, the method for preparing the light emitting diode may use the metal-organic chemical vapor deposition method (Metal-organic Chemical Vapor Deposition, MOCVD) or MOVPE (Metal-organic Vapor-Phase Epitaxy) or the like.

The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above-described embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be regarded as the scope described in this specification.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent of the present application. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the appended claims.

Claims (10)

1. A light-emitting diode, characterized in that, comprising: substrate (10); A buffer layer (20), a gallium nitride layer (30), an N-type semiconductor layer (40) and a P-type semiconductor layer (60) are sequentially stacked on the surface of the substrate (10); a multiple quantum well layer (50), which is stacked and disposed between the N-type semiconductor layer (40) and the P-type semiconductor layer (60); The multiple quantum well layer (50) includes at least one sublayer structure (501), and the sublayer structure (501) is disposed on the surface of the N-type semiconductor layer (40) away from the gallium nitride layer (30) ; Each of the sub-layer structures (501) includes a first quantum well structure (510) and a plurality of second quantum well structures (520), and the first quantum well structures (510) are disposed on the N-type semiconductor layer ( 40) Away from the surface of the gallium nitride layer (30), the plurality of second quantum well structures (520) are sequentially arranged on the first quantum well structure (510) away from the N-type semiconductor layer (40) and the thickness of each of the second quantum well structures (520) is smaller than the thickness of the first quantum well structures (510). 2. The light emitting diode of claim 1, wherein the first quantum well structure (510) comprises: a quantum barrier layer (511), disposed on the surface of the N-type semiconductor layer (40) away from the gallium nitride layer (30); The first potential well layer (512) is disposed on the surface of the quantum barrier layer (511) away from the N-type semiconductor layer (40). 3. The light-emitting diode according to claim 2, wherein the quantum barrier layer (511) is Al _m In _n Ga _1-mn N, wherein 0<m<0.6, 0<n<0.2; The first potential well layer (512) is InxGa1 _{- xN} , where 0.2<x<0.22. 4. The light emitting diode according to claim 3, wherein the quantum barrier layer (511) has a thickness of 100 nm to 140 nm; The thickness of the first potential well layer (512) is 2 nm˜6 nm. 5. The light emitting diode of claim 2, wherein each of the second quantum well structures (520) comprises: a first potential barrier layer (521), disposed on a surface of the first potential well layer (512) away from the quantum barrier layer (511); The second potential well layer (522) is disposed on the surface of the first potential barrier layer (521) away from the first potential well layer (512). 6. The light emitting diode according to claim 5, wherein the first barrier layer (521) is In _y Ga _1-y N, wherein 0<y<0.1; The second potential well layer (522) is InxGa1 _{- xN} , where 0.2<x<0.22. 7. The light emitting diode according to claim 6, wherein the thickness of the first barrier layer (521) is 4 nm˜8 nm; The thickness of the second potential well layer (522) is 2 nm˜6 nm. 8. A method for preparing a light-emitting diode, comprising: S10, a substrate (10) is provided, and a buffer layer (20), a gallium nitride layer (30) and an N-type semiconductor layer (40) are sequentially prepared on the surface of the substrate (10); S20, setting the growth temperature to be 850°C to 950°C, and preparing a quantum barrier layer (511) on the surface of the N-type semiconductor layer (40) away from the gallium nitride layer (30); S30, setting the growth temperature to be 700°C to 800°C, and preparing a first potential well layer (512) on the surface of the quantum barrier layer (511) away from the N-type semiconductor layer (40); S40, setting the growth temperature to be 750° C.˜850° C., preparing a first potential barrier layer (521) on the surface of the first potential well layer (512) away from the quantum barrier layer (511), and on the surface of the first potential well layer (512) away from the quantum barrier layer (511). A second potential well layer (522) is prepared from the surface of the barrier layer (521) away from the first potential well layer (512), the first potential barrier layer (521) and the second potential well layer (522) forming a second quantum well structure (520); and S50 , according to the step S40 , the second quantum well structure ( 520 ) is prepared on the surface of the second potential well layer ( 522 ) away from the first potential barrier layer ( 521 ) by successive cycles 3 to 6 times. 9. The light-emitting diode manufacturing method according to claim 8, wherein the quantum barrier layer (511) and the first potential well layer (512) form a first quantum well structure (510), and the first quantum well structure (510) is formed by the quantum barrier layer (511) and the first potential well layer (512). A quantum well structure (510) and a plurality of the second quantum well structures (520) form a sublayer structure (501); The light-emitting diode manufacturing method further includes: S60, according to the steps S20-S50, prepare 8-15 layers of the sub-layer structure (501) on the surface of the N-type semiconductor layer (40) far away from the gallium nitride layer (30); Wherein, a plurality of the sub-layer structures (501) form a multiple quantum well layer (50). 10. The light-emitting diode manufacturing method of claim 9, further comprising: S70 , setting the growth temperature to be 900° C.˜1000° C., and preparing a magnesium-doped high temperature P-type semiconductor layer (60) on the surface of the multiple quantum well layer (50) away from the N-type semiconductor layer (40).

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