TWI858582B - Identification circuit of inkjet head chip - Google Patents

Abstract

An identification circuit of inkjet head chip is disclosed and includes an identification circuit matching with a printer so that the printer provides the inkjet head chip with required information according to the matching result. The identification circuit includes plural memory units. The memory units forms an array structure and each of the memory units includes a fuse and a first transistor. By burning the fuse and the first transistor or not burning the fuse and the first transistor, a data signal of each memory unit is set and can be read. The first transistor is a MOSFET Anti-Fuse. The fuse and the first transistor are formed on the same inkjet head chip.

Description

Inkjet head chip identification circuit

The present invention relates to an inkjet head chip identification circuit, and more specifically, to an inkjet head chip identification circuit which improves the structure of a memory unit in the inkjet head to increase the data recording flexibility and data security of the ink cartridge.

Inkjet printing technology, commonly known as "Inkjet Printing", is a widely used printing technology. Its history can be traced back to the 1950s when the British HP (Hewlett-Packard) invented inkjet printing technology. Since then, inkjet printing technology has developed rapidly, making inkjet printers the mainstream technology for home and commercial printing. Inkjet printers have many advantages, including: low cost, especially economical for home and small business use; high print quality, which can provide high resolution and high quality images, especially in photos or pictures; convenient to use, inkjet printers are easy to install, and most inkjet printers can print through computers or mobile devices. Combined with the emergence of office machines with all-in-one functions (including fax, photocopying, scanning) in recent years, it can quickly expand the flexibility of document work in the office.

The inkjet head identification circuit in an inkjet printer is an important component in inkjet printing technology. Since each type of inkjet printer needs to be matched with a corresponding inkjet head, and each inkjet head has its own special specifications, including: structure, ink used, number of nozzles, and control circuit characteristics, it is necessary to match a compatible printing system to work with the inkjet printer through the inkjet head identification circuit. Specifically, the inkjet head identification circuit includes a fuse, a transistor reverse fuse, and related circuit components, which are used to store information including but not limited to the ink cartridge serial number, ink type, ink capacity, ink color, and matching information between the inkjet head and the inkjet printer to ensure printing quality and efficiency.

Please refer to FIG. 1A and FIG. 1B, which describe the method in which the memory unit 100 contained in the memory of the ink cartridge identification circuit in the prior art stores the above-mentioned ink cartridge serial number, ink type, inkjet head-inkjet printer matching information and other information. The memory unit 100 includes an identification signal terminal 110, a data terminal 120, a fuse 130, and a transistor device 140. In more detail, when the data terminal 120 provides a high potential, the transistor device 140 will be in a conducting state, and if the identification signal terminal 110 provides a low potential, the memory unit 100 will not perform a burning operation. On the other hand, when the data terminal 120 provides a high potential, the transistor device 140 will be in a conducting state, and the identification signal terminal 110 will provide a low potential. If the burning potential is provided, the memory cell 100 will be burned, as shown in FIG. 1B. When reading the memory cell 100, when the data terminal 120 provides a high potential, the transistor device 140 will be in a conducting state. At this time, if the identification signal terminal 110 reads an unburned fuse, it will read a low potential, otherwise, it will read a high potential. In this way, the memory cell 100 can transmit a high potential or low potential transmission signal by controlling whether the fuse 130 is burned or not, so as to represent the information in each bit of the memory cell 100, thereby achieving the purpose of recording information.

However, the above ink cartridge identification circuit still has the following disadvantages. Although the information recorded by the memory unit 100 by the fuse burning or not can output a signal with high and low potentials, the functions of inkjet printers are becoming increasingly rich, and the amount of information contained is increasing. It is not enough to rely solely on the fuse 130 to record information. From the perspective of industrial utilization, the inkjet head can be easily obtained by reverse engineering to imitate the state and sequence of the fuse 130 melting or not in the ink cartridge identification circuit. In addition to the infringement of intellectual property labor in enterprises, matching information between inkjet printers may also cause users to purchase inferior ink cartridges, thereby affecting the quality and rights of printing, causing economic or intellectual property losses to enterprises or users using inkjet printers. Therefore, in the current market, there is still an urgent need for an inkjet head chip identification circuit that can effectively improve information recording and security while maintaining economic costs in the same chip.

Based on the above reasons, the present invention proposes an inkjet head chip identification circuit, which improves the memory unit in the inkjet head to increase the diversity of the circuit component composition in the memory unit. Without increasing the manufacturing cost, in addition to making the stored information such as the ink cartridge serial number, identification code, ink type, ink capacity, ink color, inkjet head temperature, etc. more detailed and complete, it can also increase the difficulty of reverse engineering and counterfeiting the inkjet head chip identification circuit, thereby improving the effectiveness of intellectual property protection. The inkjet head chip identification circuit includes the following components: an identification circuit, which matches the inkjet printer, so that the inkjet printer supplies the information required for the inkjet head chip to print according to the matching result; wherein the identification circuit includes a plurality of memory cells, the plurality of memory cells form an array structure, and further includes a fuse and a first transistor, and the data signal of the memory cell is read by burning or not burning the fuse and the first transistor. In the embodiment of the present invention, the first transistor is a transistor anti-fuse (MOSFET Anti-Fuse), and the fuse and the first transistor are generated on the same inkjet head chip.

According to the content of the present invention, the first transistor can be a metal oxide semiconductor field effect transistor (MOSFET), and can be selected from N-type metal oxide semiconductor field effect transistor (NMOS) or P-type metal oxide semiconductor field effect transistor (PMOS) according to the needs of the application. In addition, the fuse can also be selected from polysilicon fuse (polyfuse) or metal fuse (metal fuse) according to the needs of the application.

According to the content of the present invention, each memory unit further includes an identification signal terminal, a data terminal, and a second transistor. The identification signal terminal is connected to a fuse or a first transistor, the data terminal is connected to a gate of the second transistor, and the fuse or the first transistor is connected to the second transistor.

The present invention will be described in detail with preferred embodiments and viewpoints. The following description provides specific implementation details of the present invention so that the reader can fully understand the implementation methods of these embodiments. However, those skilled in the art should understand that the present invention can also be implemented without these details. In addition, the present invention can also be used and implemented through other specific embodiments. The various details described in this specification can also be applied based on different needs, and various modifications or changes can be made without departing from the spirit of the present invention. Therefore, the present invention will be described with preferred embodiments and viewpoints. Such descriptions are to explain the structure of the present invention and are only used for illustration and not to limit the scope of the patent application of the present invention. The terms used in the following description will be interpreted in the broadest reasonable manner so that they can be used together with the detailed description of a specific embodiment of the present invention. Those skilled in the art can adjust the structure of the present invention according to manufacturing or application requirements to meet the needs of the actual industry. In this specification, the fuse mentioned can be abbreviated as Fuse, and the first transistor can be abbreviated as MOS. If the first transistor is a transistor anti-fuse (MOSFET Anti-Fuse), it can also be abbreviated as MOS or MOS-Anti-Fuse in this specification, and this is explained in advance.

Referring to FIG. 2A, FIG. 2B, FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D, and FIG. 3E, in one embodiment of the present invention, an inkjet head chip identification circuit 200 is provided, which includes the following components: an identification circuit 210, which matches the inkjet printer, so that the inkjet printer can supply the inkjet head chip with the information required for printing according to the matching result; wherein the identification circuit 210 includes a plurality of memory units 211, and the plurality of memory units 211 form an array The memory unit 211 has an array structure, and each memory unit 211 further includes a fuse 211F and a first transistor 211C. By burning or not burning the above-mentioned fuse 211F and the first transistor 211C, the memory unit 211 is controlled to output a data signal, so that the identification circuit 210 can provide but not limited to the ink cartridge serial number, identification code (Identification Code), ink type, ink capacity, ink color and other information corresponding to the inkjet printer according to the array structure formed by the memory unit 211, thereby enabling the inkjet printer to identify the model and type of the inkjet head in the ink cartridge. The first transistor 211C is a MOSFET Anti-Fuse, and the fuse 211F and the first transistor 211C are formed on the same inkjet head chip.

In another embodiment of the present invention, an inkjet head chip identification circuit 200 is provided, which includes the following components: an identification circuit 210, which matches the inkjet printer, so that the inkjet printer can provide the inkjet head chip with the information required for printing according to its matching result; wherein the identification circuit 210 includes a plurality of memory units 211, and the plurality of memory units 211 form an array structure, and each memory unit The memory unit 211 further includes a first transistor 211C. By burning or not burning the first transistor 211C, the memory unit 211 is controlled to output a data signal, so that the identification circuit 210 can provide, according to the array structure formed by the memory unit 211, information such as an ink cartridge serial number, an identification code, an ink type, an ink capacity, and an ink color that matches the inkjet printer, but is not limited thereto, so that the inkjet printer can identify information such as the model and type of the inkjet head in the ink cartridge.

In accordance with the above, please continue to refer to FIG. 3A, FIG. 3B, FIG. 3C, and FIG. 3D. In the embodiment of the present invention, the first transistor 211C in FIG. 3A and FIG. 3B is of P type, and the first transistor 211C in FIG. 3C and FIG. 3D is of N type. In addition, FIG. 3E illustrates the state when the fuse 211F is used in the circuit structure of the memory unit 211 in an embodiment of the present invention. In addition, in the embodiment of the present invention, in order to provide the function of burning the fuse 211F and the first transistor 211C, each memory unit 211 further includes an identification signal terminal 211A, a data terminal 211B, and a second transistor 211E. The identification signal terminal 211A transmits an identification potential and is connected to the fuse 211F or the first transistor 211C in the memory unit 211 to control the burn/non-burn fuse 211F or the first transistor 211C. In addition, the data terminal 211B transmits a data potential and is connected to the gate G of the second transistor 211E, and the fuse 211F is connected to the second transistor 211E. The memory unit 211 controls the output of the data signal by adjusting the data potential and the identification potential. In some embodiments of the present invention, the first transistor 211C can be selected from a metal oxide semi-conductor field effect transistor (MOSFET), and can be selected from an N-type or a P-type. In addition, the fuse 211F can be selected from a polysilicon fuse (polyfuse) or a metal fuse (metalfuse). The first transistor 211C and the fuse 211F can be selected from the above types according to the needs of the actual application and can be arbitrarily combined to improve the flexibility of information recording.

Please refer to FIG. 4A, FIG. 4B, FIG. 5A, and FIG. 5B, which illustrate the states of the first transistor 211C when it is burned green and when it is not burned green in the memory cell 211. According to the different states, the memory cell 211 can output a binary digit data signal. Among them, FIG. 4A and FIG. 4B illustrate the situation in which the first transistor 211C uses an N-type metal oxide semi-conductor field effect transistor in an embodiment of the present invention. In FIG. 4A , the lower end of the gate G of the first transistor 211C has a gate oxide layer GOX. When the identification potential provided by the identification signal terminal 211A is less than a breakdown potential, the structure of the gate oxide layer GOX is intact. If the data terminal 211B provides a high potential at this time, the second transistor 211E will be in a conducting state, and the identification signal terminal 211A will be read out in a high resistance state in the memory cell 211, and the output data signal shows that the memory cell 211 is in an unrecorded state. On the other hand, in FIG. 4B , when the potential provided by the identification signal terminal 211A is greater than the breakdown potential, the structure of the gate oxide layer GOX breaks down, causing the gate G to be connected to the substrate of the first transistor 211C and causing irreversible damage. This will cause the identification signal terminal 211A to be read out in a low resistance state in the memory cell 211, and the output data signal shows that the memory cell 211 is in a recorded state, thereby achieving the purpose of outputting a binary data signal. It should be noted that in the present invention, the above binary data signal is not limited to 0 and 1 necessarily corresponding to low resistance or high resistance, and it can also be 1 and 0 corresponding to high resistance or low resistance respectively, which can be set, changed or modified according to the actual application. In addition, in Figure 5A and Figure 5B, it is described that the first transistor 211C can also use a P-type metal oxide semi-conductor field effect transistor, and the gate oxide layer GOX can also be controlled by controlling the potential provided by the identification signal terminal 211A to control whether the gate oxide layer GOX collapses, thereby recording/not recording the memory unit 211, so as to achieve the purpose of controlling the output of the binary data signal. Based on the fact that its recording/not recording mechanism is the same as that of the N-type metal oxide semi-conductor field effect transistor, it will not be repeated below.

In one embodiment, please refer to FIG. 6 and FIG. 7, which illustrate an array structure of MOS-Fuse composed of a plurality of memory cells 211 in an identification circuit 210, wherein the MOS-Fuse refers to the type of each memory cell 211 as shown in FIG. 3A or FIG. 3B, which uses a fuse 211F or a first transistor 211C. In the array structure, the type of memory cell 211 can use the fuse 211F or the first transistor 211C. In one aspect of the present invention, when the fuse 211F is selected from a polysilicon fuse or a metal fuse, and the first transistor 211C is selected from a PMOS or an NMOS, each memory cell 211 has at least the following four states: PMOS polyfuse NMOS MetalFuse

The combination of the above-mentioned various aspects in the identification circuit 210 can increase the diversity of each memory unit 211 in the identification circuit 210. In other words, when the array structure of the identification circuit 210 has N memory units 211, it means that the array structure can have multiple ways of recording data. The advantages of such an architecture are firstly economical, which can make MOS, F The manufacturing cost of the identification circuit 210 that uses the coexistence does not change (or changes little) compared to the prior art that only uses the fuse 130. In addition, from the perspective of data signal recording, since the identification circuit 210 has more choices for burning types, the identification circuit 210 can also record more and more complete information, such as the ink cartridge serial number, identification code, ink type, ink capacity, ink color, ink jet head temperature, etc. Finally, from the perspective of information security and intellectual property, since the inkjet head chip identification circuit 200 needs to be matched with relevant identification software, identification program or identification algorithm during the matching process with the inkjet printer, the increase in the burning type and diversity of the identification circuit 210 can also enhance the strictness of the information security encryption of the inkjet head chip identification circuit 200, thereby protecting the intellectual property of the enterprise and the relevant rights and interests of users. It should be noted that the MOS-Fuse array structure composed of a plurality of memory cells 211 in FIG. 6 is for illustration only. In the actual application of the present invention, the placement positions of MOS and Fuse in the array structure (i.e., the selection mode of each memory cell 211) and the number of bits are not limited. For example, FIG. 7 is another implementation mode in the above description. Therefore, those skilled in the art can select or modify it according to the actual application after reading this specification.

In summary, the present invention improves the memory unit structure in the inkjet head chip identification circuit, thereby increasing the data recording flexibility and information security of the traditional ink cartridge. It can be modified in various ways by a person skilled in the art, but all of them are within the scope of protection intended by the attached patent application.

100: memory unit 110: identification signal terminal 120: data terminal 130: fuse 140: transistor device 200: inkjet head chip identification circuit 210: identification circuit 211: memory unit 211A: identification signal terminal 211B: data terminal 211C: first transistor 211E: second transistor 211F: fuse G: gate N: N-type P: P-type GOX: gate oxide layer MOS-Anti-Fuse: metal oxide semi-field effect transistor anti-fuse Fuse: fuse

The detailed description of the present invention and the schematic diagrams of the embodiments described below should enable a more complete understanding of the present invention; however, it should be understood that this is only limited to a reference for understanding the application of the present invention, rather than limiting the present invention to a specific embodiment.

FIG. 1A illustrates the circuit structure of the memory cell before burning in the prior art. FIG. 1B illustrates the circuit structure of the memory cell after burning in the prior art. FIG. 2A illustrates the inkjet head chip identification circuit, which matches the inkjet printer through the identification circuit and supplies the information required for printing according to the matching result. FIG. 2B illustrates the array structure formed by the memory cell contained in the identification unit to record the information in the inkjet head. FIG. 3A illustrates the circuit structure of the memory cell in the present invention. FIG. 3B illustrates the circuit structure of the memory cell in the present invention. FIG. 3C illustrates the circuit structure of the memory cell in the present invention. FIG. 3D illustrates the circuit structure of the memory cell in the present invention. FIG. 3E illustrates a state when a fuse is used in the circuit structure of a memory cell in an embodiment of the present invention. FIG. 4A illustrates a cross-sectional structure of an N-type metal oxide semi-conductor field effect transistor before burning in the present invention. FIG. 4B illustrates a cross-sectional structure of an N-type metal oxide semi-conductor field effect transistor after burning in the present invention. FIG. 5A illustrates a cross-sectional structure of a P-type metal oxide semi-conductor field effect transistor before burning in the present invention. FIG. 5B illustrates a cross-sectional structure of a P-type metal oxide semi-conductor field effect transistor after burning in the present invention. FIG. 6 illustrates an array structure composed of a fuse and a first transistor in an embodiment of a memory cell of the present invention. FIG. 7 illustrates an array structure composed of a fuse and a first transistor in another embodiment of the memory unit of the present invention.

210: Identification circuit 211: Memory unit MOS-Anti-Fuse: MOS field effect transistor anti-fuse Fuse: Fuse

Claims (9)

An inkjet head chip identification circuit includes: an identification circuit, matched with an inkjet printer, so that the inkjet printer supplies inkjet head chip information according to the matching result; wherein the identification circuit further includes a plurality of memory units, and the plurality of memory units form an array structure; wherein the plurality of memory units include a fuse and a first transistor, and the first transistor is a transistor reverse fuse, and a data signal is read by burning the fuse or the first transistor; wherein the plurality of memory units further include: an identification signal A terminal connected to the fuse or the first transistor to provide an identification potential; a data terminal to provide a data potential; and a second transistor connected to the first transistor or the fuse, and a gate of the second transistor connected to the data terminal; wherein the plurality of memory units read the data signal by regulating the data potential and the identification potential; wherein the inkjet head chip identification circuit needs to be matched with an identification software, an identification program or an identification algorithm in the process of matching with the inkjet printer. The inkjet head chip identification circuit as described in claim 1, wherein the first transistor is selected from an N-type metal oxide semiconductor field effect transistor (NMOS) or a P-type metal oxide semiconductor field effect transistor (PMOS). The inkjet head chip identification circuit as described in claim 1, wherein the fuse is selected from a polysilicon fuse (polyfuse) or a metal fuse (metal fuse). As described in claim 1, the inkjet head chip identification circuit, wherein when the identification potential is less than a breakdown potential and the data terminal provides a high potential, the identification signal terminal will be in a high resistance state in the corresponding plurality of memory cells, and the output data signal shows that the corresponding plurality of memory cells are in an unrecorded state. The inkjet head chip identification circuit as described in claim 4, wherein the structure of the gate oxide layer (GOX) of the first transistor is in a good state. As described in claim 1, in the inkjet head chip identification circuit, when the identification potential is greater than a breakdown potential, the identification signal terminal will be in a low resistance state in the corresponding plurality of memory cells, and the output data signal shows that the corresponding plurality of memory cells are in a recorded state. In the inkjet head chip identification circuit as described in claim 6, the structure of the gate oxide layer (GOX) of the first transistor is in a collapsed state. An inkjet head chip identification circuit as described in claim 1, wherein the information recorded by the identification circuit includes ink cartridge serial number, identification code, ink type, ink capacity, ink color, inkjet head temperature, or any combination thereof. An inkjet head chip identification circuit includes: an identification circuit, matched with an inkjet printer, so that the inkjet printer supplies inkjet head chip information according to the matching result; wherein the identification circuit further includes a plurality of memory units, and the plurality of memory units form an array structure; wherein the plurality of memory units include a first transistor, and the first transistor is a transistor reverse fuse, and the reading of a data signal is controlled by burning the first transistor or not; wherein the plurality of memory units further include: an identification signal terminal, connected to the fuse A fuse or the first transistor is connected to provide an identification potential; a data terminal provides a data potential; and a second transistor, the second transistor is connected to the first transistor or the fuse, and the gate of the second transistor is connected to the data terminal; wherein the plurality of memory units read the data signal by adjusting the data potential and the identification potential; wherein the inkjet head chip identification circuit needs to be matched with an identification software, an identification program or an identification algorithm in the process of matching with the inkjet printer.

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