TW202502569A - Identification chip - Google Patents

Abstract

An identification chip is disclosed. The identification chip is disposed on a flexible circuit board and electrically connected to a printer. The identification chip includes a plurality of memory units arranged in an array structure, and the type of each memory unit is chosen from one of a first transistor, a third transistor or a fuse. By such arrangement of the array structure, the ink cartridge installed with the identification chip can be matched with the printer.

Description

Identification chip

The present invention relates to an identification chip, and more specifically, to an identification chip which can be reused, will not be disturbed by heat, and can improve environmental protection performance by providing an identification chip and electrically connecting it to a printer.

Inkjet printing technology, commonly known as "Inkjet Printing", is a widely used printing technology. Its history can be traced back to the 1950s when the British HP (Hewlett-Packard) invented inkjet printing technology. Since then, inkjet printing technology has developed rapidly, making inkjet printers the mainstream technology for home and commercial printing. Inkjet printers have many advantages, including: low cost, especially economical for home and small business use; high print quality, which can provide high resolution and high quality images, especially in photos or pictures; convenient to use, inkjet printers are easy to install, and most inkjet printers can print through computers or mobile devices. When combined with the emerging office machines with all-in-one functions (including fax, photocopying, scanning) in recent years, they can quickly expand the flexibility of document operations in offices.

The inkjet head identification circuit in an inkjet printer is an important component in inkjet printing technology. Since each type of inkjet printer needs to be matched with a corresponding inkjet head, and each inkjet head has its own special specifications, including: structure, ink used, number of nozzles, and control circuit characteristics, it is necessary to match a compatible printing system to work with the inkjet printer through the inkjet head identification circuit. Specifically, the inkjet head identification circuit includes a fuse, a transistor reverse fuse, and related circuit components, which are used to store information including but not limited to the ink cartridge serial number, ink type, ink capacity, ink color, and matching information between the inkjet head and the inkjet printer to ensure printing quality and efficiency.

Please refer to Figures 1A and 1B, which describe the matching and control method between the ink cartridge 10 and the printer 30 in the prior art: the ink cartridge 10 includes an inkjet head chip 100A, and the inkjet head chip 100A stores the above-mentioned ink cartridge serial number, ink type, inkjet head-printer matching information and other information. The general inkjet head chip 100A further includes a spray control circuit 110 and an inkjet head identification circuit 120, which are respectively coupled to the inkjet control terminal 320 and the identification signal terminal 310 on the printer 30. Among them, after receiving the ejection signal sent by the inkjet control terminal 320 of the printer 30, the above-mentioned ejection point control circuit 110 will activate the corresponding ejection point on the ink cartridge 10 to eject ink droplets, and the inkjet head identification circuit 120 mainly provides the inkjet head identification signal to the identification signal terminal 310 of the printer 30, such as the above-mentioned ink cartridge serial number, ink type, inkjet head-printer matching information, ink content and other information.

However, the prior art is deficient in that when the inkjet head chip 100A controls printing, it needs to heat the ink, which makes its structure inherently have a relatively high chip temperature and a more drastic temperature change. As shown in FIG. 1C , the conventional method of integrating the inkjet head identification circuit 120 into the inkjet head chip 100A easily increases the chances of the components in the inkjet head identification circuit 120 malfunctioning due to the above-mentioned temperature factors, thereby affecting the stability of the identification signal recognition during printing, resulting in lower reliability of the conventional technology, or further reinforcement design can only be performed in terms of materials or structure, so that only one can be chosen between device reliability and manufacturing cost. Furthermore, since the ink cartridge 10 in the prior art is used up, the printer 30 will immediately burn the inkjet head chip 100A according to the ink content recorded in the inkjet head identification circuit 120 to permanently disable the operation of the ink cartridge 10, this means that the information that can be recorded by the inkjet head chip 100A in the prior art is one-time, so that the ink cartridge 10 currently on the market can only be used once. When the ink is used up, the ink cartridge 10 will be permanently unusable. However, considering the mechanical structure of the ink cartridge 10, The structural part is still intact, and with the current environmental protection regulations becoming increasingly stringent, the environmental protection concept of market consumers and the general public gradually rising, and the cost of using corporate economic resources, the known technology will cause waste in the use of the ink cartridge 10. Therefore, at the current point in time in the market, there is still a need to improve the existing ink cartridge 10, or the matching control method between the ink cartridge 10 and the printer 30, so that the ink cartridge 10 can be reused after being filled with ink to meet the purpose of environmental protection and economy.

Based on the above reasons, the present invention proposes an identification chip, which is electrically connected to the inkjet head chip located on the outer layer of the ink cartridge, that is, electrically connected to the inkjet head chip of the flexible circuit board on the ink cartridge or the outer shell of the ink cartridge, and optimizes the inkjet head identification signal provided by the original inkjet head chip through the identification signal provided by the identification chip, so that the ink cartridge connected to the identification chip can continue to provide the printer with printing needs after filling new ink, instead of being a disposable consumable in the traditional way. In addition, since the identification chip is an independent component, it is more flexible in the location of the setting and is less likely to be affected by the heat energy of the inkjet head chip during operation, so that the identification chip can improve reliability while taking into account economic costs. In order to increase the diversity of the circuit components in the memory unit of the identification chip, and to make the memory unit modifiable, and to make the ink cartridge serial number and identification code stored in the memory unit structure of the identification chip Code), ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, ink cartridge capacity change (ink capacity), number of times the ink cartridge is used on the machine, and other information records are more detailed and complete, which can increase the difficulty of reverse engineering to copy the identification chip, increase the reuse of the ink cartridge, and reduce the cost spent by the enterprise to manufacture the ink cartridge, but can maintain the effectiveness of the intellectual property protection in the ink cartridge. Therefore, in order to achieve the above purpose, the present invention explores the circuit architecture in the above identification chip, and its detailed technical solution will be described in detail as follows.

The present invention provides an identification chip, comprising the following elements: the identification chip provides an identification signal to match a printer; wherein the identification chip has a plurality of memory cells, the plurality of memory cells form an array structure, and further comprises a first transistor, a third transistor, and a fuse, that is, the main type of each single memory cell can be selected from the first transistor, the third transistor, or the fuse. In the present invention, by configuring the types and quantities of the plurality of memory cells in the array structure in the identification chip, that is, the states of the first transistor, the third transistor, and the fuse, when reading the identification signal of the memory cell, the information recorded in the identification chip can be judged. In an embodiment of the present invention, the first transistor is a MOSFET Anti-Fuse, the third transistor is an EPROM, and the first transistor, the third transistor and the fuse are generated on the same identification chip.

According to the content of the present invention, the first transistor can be a metal oxide semiconductor field effect transistor (MOSFET), and can be selected from N-type metal oxide semiconductor field effect transistor (NMOS) or P-type metal oxide semiconductor field effect transistor (PMOS) according to the needs of the application. In addition, the third transistor is an erasable and programmable only memory (Erasable Programmable Read Only Memory, EPROM). Finally, the fuse can be selected from a polysilicon fuse (polyfuse) or a metal fuse (metal fuse) according to the needs of the application.

According to the content of the present invention, each memory unit further includes an identification signal terminal, a data terminal, and a second transistor. The identification signal terminal is connected to the first transistor, the third transistor or the fuse, the data terminal is connected to the gate of the second transistor, and the first transistor, the third transistor and the fuse are connected to the second transistor.

The present invention will be described in detail with preferred embodiments and viewpoints. The following description provides specific implementation details of the present invention so that the reader can fully understand the implementation methods of these embodiments. However, those skilled in the art should understand that the present invention can also be implemented without these details. In addition, the present invention can also be used and implemented through other specific embodiments. The various details described in this specification can also be applied based on different needs, and various modifications or changes can be made without departing from the spirit of the present invention. Therefore, the present invention will be described with preferred embodiments and viewpoints. Such descriptions are to explain the structure of the present invention and are only used for illustration and not to limit the scope of the patent application of the present invention. The terms used in the following description will be interpreted in the broadest reasonable manner so that they can be used together with the detailed description of a specific embodiment of the present invention. Those skilled in the art can adjust the structure of the present invention according to manufacturing or application requirements to meet the needs of the actual industry. Among them, in this manual, the fuse mentioned can be abbreviated as Fuse, and the first transistor can be abbreviated as MOS. If the first transistor is a metal oxide semi-conductor field effect transistor anti-fuse (MOSFET Anti-Fuse), it can also be abbreviated as MOS or MOS-Anti-Fuse in this manual. Similarly, if the third transistor is an erasable and programmable unique memory, it can be abbreviated as EPROM. In addition, in order to transmit the signal for identification (ID), this manual provides identification signal terminals 310 and 211A in the printer 30 and the memory unit 211 respectively. A person skilled in the art can understand the configuration of the current identification signal terminals 310 and 211A through the context of the manual and the accompanying diagrams, so it is described in advance.

Referring to FIG. 2A, FIG. 2E, FIG. 3A and FIG. 3B, in the first embodiment of the present invention, an identification chip 210 is provided, which is disposed on a flexible circuit board 200, and the flexible circuit board 200 is attached to and electrically connected to the inkjet head chip 100A in the flexible circuit board 100 located on the outer layer of the ink cartridge 10, wherein the identification chip 210 includes the following components: a plurality of memory cells 211, the plurality of memory cells 212, The cells 211 are arranged in the identification chip 210 to form an array structure. The multiple memory cells 211 include a first transistor 211C, a third transistor 211G and a fuse 211F. The states of the first transistor 211C, the third transistor 211G and the fuse 211F are configured in sequence and quantity in the identification chip 210 to record information, and the ink cartridge 10 is matched with the printer 30 by transmitting an identification signal. Among them, in the embodiment of the present invention, the first transistor 211C is a MOSFET Anti-Fuse, the third transistor 211G is an erasable and programmable unique memory (EPROM), and the fuse 211F is selected from a polysilicon fuse (polyfuse) or a metal fuse (metal fuse), and the first transistor 211C, the third transistor 211G and the fuse 211F are generated on the same identification chip 210. Among them, the array structure formed by the memory unit 211 provides but is not limited to the information such as the ink cartridge serial number, identification code, ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, ink cartridge capacity change (ink capacity), number of times the ink cartridge has been used on the machine, etc. that matches the printer 30, thereby enabling the printer 30 to identify the model and type of the ink jet head in the ink cartridge 10.

Please refer to FIG. 2A and FIG. 2E as well. According to the above embodiment of the present invention, the flexible circuit board 200 is configured and attached to the flexible circuit board 100 and has an identification chip 210. When the ink cartridge 10 is installed in the printer 30, the identification chip 210 is coupled to the identification signal terminal 310 and the inkjet control terminal 320 in the printer 30 in terms of the circuit structure. The inkjet point control circuit 110 and the inkjet head identification circuit 120 in the inkjet head chip 100A are coupled to the inkjet control terminal 320 in the printer 30 to transmit the ejection signal. When the identification chip 210 is connected to the printer 30, the ejection signal of the inkjet head chip 100A will be maintained or optimized. At the same time, the identification signal provided by the identification chip 210 will replace or optimize the original inkjet head identification signal. In this way, the inkjet head chip 100A, which was originally only used once and was discarded due to the exhaustion of ink in the previous use and burning by the printer 30, will not be used again. The discarded ink cartridge 10, after the ink cartridge 10 is filled with ink, can still transmit an identification signal to the identification signal terminal 310. The printer 30 transmits an ink jetting signal from the ink jetting control terminal 320 to the ejection point control circuit 110 according to the identification signal to activate the corresponding ejection point on the ink cartridge 10 to eject ink droplets again, so that the ink cartridge 10 has the performance of being reused, thereby achieving the purpose of the present invention.

Please refer to FIG. 2B, FIG. 2C, FIG. 2D and FIG. 2F. According to two other embodiments of the present invention, the identification chip 210 can also be independently attached to the flexible circuit board 100 of the ink cartridge 10 itself, or to the outer shell of the ink cartridge 10. When the ink cartridge 10 is installed in the printer 30, the identification chip 210 will be coupled to the identification signal terminal 310 and the ink jet control terminal 320 in the printer 30 in the circuit structure. The ink jet control circuit 110 in the ink jet head chip 100A is coupled to the ink jet control terminal 320 in the printer 30 to transmit the ejection signal. The advantage of such a setting is that the positions of the identification chip 210 and the inkjet head chip 100A are set independently of each other, so the heat energy generated by the inkjet head chip 100A during operation, or the temperature changes during the inkjet control process can be far away from the position of the identification chip 210, which can ensure to the greatest extent that the identification chip 210 will not be affected by temperature changes during the transmission of identification signals, thereby achieving the purpose of the present invention to improve the reliability of the device.

According to one viewpoint of the present invention, the identification chip 210 proposed by the present invention can be modified and recorded for multiple times through repeated burning, wherein the MOSFET Anti-Fuse and the fuse 211F selected by the first transistor 211C mainly record the information in the identification chip 210 that will not change, such as specification parameters, ink cartridge serial number, identification code, ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, or any combination of the above; on the other hand, the EPROM selected by the third transistor 211G has a different resistance value each time it is burned, and can mainly be used as a recording carrier of variable information, such as changes in the ink cartridge capacity (ink capacity) during printing, the number of times the ink cartridge is used on the machine, or any combination of the above. In the embodiment of the present invention, no matter whether the MOSFET Anti-Fuse and EPROM have been burned or not, the appearance of the identification chip 210 is not different. Moreover, whether reading, burning or using the identification chip 210, a specific software algorithm must be used. From the perspective of intellectual property rights and industrial utilization, even if the information security attacker copies the fuse 211F of the present invention in its entirety and the order of melting, but does not have the MOSFET Anti-Fuse or EPROM, the information security attacker will not be able to steal the information. Whether the Anti-Fuse and EPROM have been burned, the identification chip 210 using the present invention cannot be counterfeited through reverse engineering, thereby enhancing information security, protecting the rights and interests of both consumers and manufacturers in the industry, and achieving the purpose of making the encryption function and the information that can be recorded more complete. At the same time, the fuse 211F can be retained for fixed information recording, with the advantages of simple structure, easy cost control and the ability to reuse the ink cartridge 10.

In accordance with the above, please continue to refer to FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E and FIG. 4F, wherein, in the embodiment of the present invention, the first transistor 211C in FIG. 4A and FIG. 4B is of P type, and the first transistor 211C in FIG. 4C and FIG. 4D is of N type. In addition, FIG. 4E illustrates the state when the third transistor 211G in the circuit structure of the memory unit 211 adopts EPROM in one embodiment of the present invention. In addition, in the embodiment of the present invention, in order to provide the function of burning the first transistor 211C, the third transistor 211G, and the fuse 211F, each memory unit 211 further includes an identification signal terminal 211A, a data terminal 211B, and a second transistor 211E. The identification signal terminal 211A transmits an identification potential and is connected to the first transistor 211C, the third transistor 211G or the fuse 211F in the memory unit 211 to control whether to burn or not burn the first transistor 211C, the third transistor 211G or the fuse 211F. In addition, the data terminal 211B transmits a data potential and is connected to the gate G of the second transistor 211E, and the first transistor 211C, the third transistor 211G or the fuse 211F is connected to the second transistor 211E. The memory unit 211 controls the output of the identification signal by adjusting the data potential and the identification potential. In some embodiments of the present invention, the first transistor 211C can be selected from metal oxide semi-conductor field effect transistors (MOSFET), and can be selected from N-type or P-type. In addition, the third transistor 211G is an EPROM. The above-mentioned memory unit 211 can be selected from the types of the first transistor 211C, the third transistor 211G, and the fuse 211F according to the needs of actual applications, and any combination of the above types can be performed in the array structure formed by multiple memory units 211 to improve the flexibility of information recording.

Please refer to FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D, which illustrate the states of the first transistor 211C when it is burned green and not burned in the memory cell 211. According to the different states, the memory cell 211 can output a binary digit identification signal. Among them, FIG. 5A and FIG. 5B illustrate the situation in which the first transistor 211C uses an N-type metal oxide semi-conductor field effect transistor in an embodiment of the present invention. In FIG. 5A , the lower end of the gate G of the first transistor 211C has a gate oxide layer GOX. When the identification potential provided by the identification signal terminal 211A is less than a breakdown potential, the structure of the gate oxide layer GOX is intact. If the data terminal 211B provides a high potential at this time, the second transistor 211E will be in a conducting state, and the identification signal terminal 211A will be read out as a high resistance state in the memory cell 211, and the output identification signal shows that the memory cell 211 is in an unrecorded state. On the other hand, in FIG. 5B , when the potential provided by the identification signal terminal 211A is greater than the breakdown potential, the structure of the gate oxide layer GOX breaks down, causing the gate G to be connected to the substrate of the first transistor 211C and causing irreversible damage. This will cause the identification signal terminal 211A to be read out in a low resistance state in the memory cell 211, and the output identification signal shows that the memory cell 211 is in a recorded state, thereby achieving the purpose of outputting a binary identification signal. It should be noted that in the present invention, the above binary identification signal is not limited to 0 and 1 necessarily corresponding to low resistance or high resistance, and it can also be 1 and 0 corresponding to low resistance or high resistance respectively, which can be set, changed or modified according to the actual application. In addition, in Figure 5C and Figure 5D, it is described that the first transistor 211C can also use a P-type metal oxide semi-conductor field effect transistor, and the gate oxide layer GOX can also be controlled by controlling the potential provided by the identification signal terminal 211A to control whether the gate oxide layer GOX collapses, thereby burning/not burning the memory unit 211 to achieve the purpose of controlling the output of the binary identification signal. Based on the fact that its burning/not burning mechanism is the same as that of the N-type metal oxide semi-conductor field effect transistor, it will not be repeated below.

Please refer to FIG. 5E, which illustrates the cross-sectional structure of the third transistor 211G of the present invention. In the embodiment of the present invention, if the third transistor 211G is an EPROM, the main components contained therein include a source S (Source), a drain D (Drain), a polysilicon gate PG (Poly gate), a floating gate _M1 (Floating gate), a first dielectric layer ILD, a control gate _M2 (Control gate), and a second dielectric layer IMD. The source S and drain D can be made of N-type or P-type semiconductors, and the first dielectric layer ILD is set between the polysilicon gate PG and the floating gate _M1 , and the second dielectric layer IMD is set between the floating gate _M1 and the control gate _M2 . The polysilicon gate PG is used to connect the source S and the drain D, and the floating gate _M1 and the control gate _M2 are metal materials. In an embodiment of the present invention, if the source S and drain D are N-type semiconductors, when the burning starts, a high voltage will be provided at the drain D. At this time, the electrons will move from the source S to the drain D through the polysilicon gate PG. Under the action of the high voltage, the moving pulling force of the electrons is strengthened, and the energy causes the temperature of the electrons to rise, and they become hot electrons. Then, a high voltage is provided to the control gate _M2 , and the hot electrons will overcome the potential energy of the first dielectric layer ILD and jump to the floating gate _M1 . If the high voltage of the control gate _M2 and the drain D is turned off at this time, the hot electrons will be confined (stored) in the floating gate _M1 , and this will complete one burning. When the third transistor 211G completes the burning, the value read will be high resistance (high), compared to the value read when there are no hot electrons in the floating gate _M1 before burning, which is low resistance (low). In this way, the memory unit 211 can output a binary digit identification signal. Similarly, the above binary identification signal is not limited to 0 and 1 corresponding to low resistance or high resistance. It can also be 1 and 0 corresponding to low resistance or high resistance respectively. It can be set, changed or modified according to the actual application. In addition, when the EPROM of the third transistor 211G is burned multiple times, its resistance value will change when reading, and can be used as a variable record of information during repeated burning, such as the aforementioned change in ink cartridge capacity (ink capacity), the number of times the ink cartridge is used on the machine, etc.

In the embodiment of the present invention, please refer to FIG. 6A and FIG. 6B, which illustrate an array structure composed of a plurality of memory cells 211 in an identification chip 210, wherein the array structure includes a fuse 211F, a first transistor 211C (ie, MOS Anti-Fuse), and a third transistor 211G (ie, EPROM). Among them, FIG. 6A and FIG. 6B illustrate that in the combination of the identification chip 210, the diversity of the types of each memory unit 211 in the identification chip 210 can be increased. That is to say, when the array structure of the identification chip 210 has N memory units 211, it means that the array structure can have a variety of ways to record data. The advantages of such a structure are firstly economical, which can well control the manufacturing cost of the identification chip 210 with Fuse, MOS Anti-Fuse, and EPROM coexisting. And from the perspective of identification signal recording, since the selection of the burning type of the identification chip 210 is more, the identification chip 210 can also record more and more complete information, such as the ink cartridge serial number, identification code (Identification Code), ink type, ink volume, ink color, inkjet head temperature, etc. Finally, in terms of information security and intellectual property, since the inkjet head chip 100A needs to be matched with relevant identification software, identification program or identification algorithm during the matching process with the printer 30, the increase in the burning type and diversity of the identification chip 210, combined with the above-mentioned algorithm, can also enhance the strictness of the identification chip 210 in information security encryption, thereby protecting the intellectual property of the enterprise and the relevant rights and interests of users. It should be noted here that the array structure composed of a plurality of memory cells 211 in FIG. 6 is for illustration only. In the actual application of the present invention, the placement positions of fuses, MOS anti-fuses and EPROMs in the array structure (i.e., the selection type and mode of each memory cell 211) and the number of bits are not limited. For example, FIG. 6A is one mode of the present invention, and FIG. 6B is another mode of implementation in the above description. Therefore, those skilled in the art can select or modify the placement positions and the number of bits of fuses, MOS anti-fuses and EPROMs in the array structure according to the actual application.

In summary, the present invention proposes a structure for arranging the memory unit in the identification chip identification circuit, so that the ink cartridge can be reused, improving the environmental performance of the product while maintaining the protection of intellectual property rights. It can be modified in various ways by people familiar with this technology, but all of them do not deviate from the rights to be protected as specified in the attached patent application scope.

10: ink cartridge 100: flexible circuit board 100A: inkjet head chip 110: jet point control circuit 120: inkjet head identification circuit 200: flexible circuit board 210: identification chip 211: memory unit 211A: identification signal terminal 211B: data terminal 211C: first transistor 211E: second transistor 211F: fuse 211G: third transistor 30: printer 310: identification signal terminal 320: inkjet control terminal G: gate N: N type P: P type GOX: gate oxide layer S: source D: drain PG: polysilicon gate _M1 : floating gate _M2 :Control gate ILD:First dielectric layer IMD:Second dielectric layer

The detailed description of the present invention and the schematic diagrams of the embodiments described below should enable a more complete understanding of the present invention; however, it should be understood that this is only limited to a reference for understanding the application of the present invention, rather than limiting the present invention to a specific embodiment.

Figure 1A illustrates the structure of the ink cartridge and the setting method of the inkjet head chip. Figure 1B illustrates the circuit structure of the connection between the printer and the inkjet head chip. Figure 1C illustrates the circuit structure of the connection between the printer and the inkjet head chip. Figure 2A illustrates the first setting method of connecting the identification chip to the ink cartridge. Figure 2B illustrates the second setting method of connecting the identification chip to the ink cartridge. Figure 2C illustrates the third setting method of connecting the identification chip to the ink cartridge. Figure 2D illustrates the configuration method of the identification chip. Figure 2E illustrates the first circuit structure of the circuit of the printer and the inkjet head chip after connecting the identification chip. FIG. 2F illustrates the circuit of the printer and inkjet head chip, and the second and third circuit structures after connecting the identification chip. FIG. 3A illustrates the structure of the identification chip being set on the flexible circuit board. FIG. 3B illustrates the array structure formed by the memory unit contained in the identification circuit of the identification chip to record the information in the inkjet head. FIG. 4A illustrates the circuit structure of one embodiment of the memory unit in the present invention. FIG. 4B illustrates the circuit structure of one embodiment of the memory unit in the present invention. FIG. 4C illustrates the circuit structure of one embodiment of the memory unit in the present invention. FIG. 4D illustrates the circuit structure of one embodiment of the memory unit in the present invention. FIG. 4E illustrates a state when a third transistor, i.e., EPROM, is used in the circuit structure of a memory cell in an embodiment of the present invention. FIG. 4F illustrates a state when a fuse is used in the circuit structure of a memory cell in an embodiment of the present invention. FIG. 5A illustrates a cross-sectional structure of an N-type metal oxide semi-conductor field effect transistor before burning in the present invention. FIG. 5B illustrates a cross-sectional structure of an N-type metal oxide semi-conductor field effect transistor after burning in the present invention. FIG. 5C illustrates a cross-sectional structure of a P-type metal oxide semi-conductor field effect transistor before burning in the present invention. FIG. 5D illustrates a cross-sectional structure of a P-type metal oxide semi-conductor field effect transistor after burning in the present invention. FIG. 5E illustrates a cross-sectional structure of an EPROM in the present invention. FIG. 6A illustrates an array structure composed of the first and third transistors and the fuse in one embodiment of the memory unit of the present invention. FIG. 6B illustrates an array structure composed of the first and third transistors and the fuse in another embodiment of the memory unit of the present invention.

100A: Inkjet head chip

110: Spray point control circuit

120: Inkjet head identification circuit

210: Identification chip

30: Printer

310: Identification signal terminal

320: Inkjet control terminal

Claims (13)

An identification chip includes: A plurality of memory cells arranged to form an array structure, wherein the array structure further includes: A first transistor; A third transistor; and, A fuse; wherein the identification chip connects and matches a printer and transmits an identification signal to the printer by configuring the quantity, combination, and position of the first transistor, the third transistor, and the fuse in the array structure. An identification chip as described in claim 1, wherein the first transistor is selected from an N-type metal oxide semiconductor field effect transistor (NMOS) or a P-type metal oxide semiconductor field effect transistor (PMOS). An identification chip as described in claim 1, wherein the third transistor comprises: a source, a drain, a polysilicon gate, a floating gate, a first dielectric layer, a control gate, and a second dielectric layer; wherein the first dielectric layer is disposed between the polysilicon gate and the floating gate, the second dielectric layer is disposed between the floating gate and the control gate, and the polysilicon gate is connected to the source and the drain. An identification chip as described in claim 3, wherein the material of the floating gate and the control gate is metal. An identification chip as described in claim 1, wherein the fuse is selected from a polysilicon fuse (polyfuse or metal fuse). The identification chip as described in claim 1, wherein the plurality of memory cells further comprises: an identification signal terminal connected to the fuse, the first transistor or the third transistor to provide an identification potential; a data terminal providing a data potential; and, a second transistor, the second transistor connected to the fuse, the first transistor or the third transistor, and a gate of the second transistor connected to the data terminal; wherein the plurality of memory cells read the identification signal by regulating the data potential and the identification potential. An identification chip as described in claim 6, wherein when the identification signal terminal is connected to the first transistor and the identification potential is less than a breakdown potential, and the data terminal provides a high potential, the identification signal terminal will be in a high resistance state in the corresponding plurality of memory cells, and the output identification signal indicates that the corresponding plurality of memory cells are in an unrecorded state. An identification chip as described in claim 7, wherein the structure of the gate oxide layer (GOX) of the first transistor is in a good state. An identification chip as described in claim 6, wherein when the identification signal terminal is connected to the first transistor and the identification potential is greater than a breakdown potential, the identification signal terminal will be in a low resistance state in the corresponding plurality of memory cells, and the output identification signal indicates that the corresponding plurality of memory cells appear to be in a recorded state. An identification chip as described in claim 9, wherein the structure of the gate oxide layer (GOX) of the first transistor is in a collapsed state. An identification chip as described in claim 1, wherein the information recorded by the identification chip includes information such as ink cartridge serial number, identification code, ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, ink cartridge capacity change (ink capacity), number of times the ink cartridge has been used on the machine, or any combination of the above. An identification chip as described in claim 11, wherein the first transistor and the fuse record information in the inkjet head chip that will not change, including ink cartridge serial number, identification code, ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, or any combination of the above. An identification chip as described in claim 11, wherein the third transistor records information that will change in the inkjet head chip, including information such as changes in ink cartridge capacity (ink capacity), the number of times the ink cartridge is used on the machine, or any combination of the above.

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