CN119567722A

CN119567722A - Identification chip

Info

Publication number: CN119567722A
Application number: CN202410188605.1A
Authority: CN
Inventors: 莫皓然; 张正明; 廖文雄
Original assignee: Microjet Technology Co Ltd
Current assignee: Microjet Technology Co Ltd
Priority date: 2023-09-07
Filing date: 2024-02-20
Publication date: 2025-03-07

Abstract

An identification chip is provided on a flexible printed circuit board and electrically connected to a printer. The components include: a plurality of memory units arranged to form an array structure, and the type of each memory unit in the array structure can be selected from a first transistor or a fuse. By configuring the pattern and state of the array structure, the ink cartridge after the identification chip is installed can be matched with the printer.

Description

Identification wafer

Technical Field

The present invention relates to a recognition chip, and more particularly, to a recognition chip capable of recycling the recognition chip, not being interfered by heat energy, and increasing environmental protection performance by providing a recognition chip and electrically connecting the recognition chip to a printer.

Background

The ink jet Printing technology, commonly referred to as "Inkjet Printing", is a widely used Printing technology, the history of which can be traced back to the 1950 s, when the uk HP company (Hewlett-Packard) invented the ink jet Printing technology. Since then, the development of inkjet printing technology has been rapid, making inkjet printers the dominant technology for home and business printing, inkjet printers have many advantages including low cost, economic advantages especially in home and small business applications, higher print quality, capability of providing high resolution and high quality images, especially in photographs or pictures, ease of use, ease of installation of inkjet printers, and most inkjet printers capable of printing by computer or mobile equipment, combined with the recent rise of all-in-one function (including fax, photocopying, scanning) business flexibility in document work in offices, can be rapidly expanded.

The inkjet head identification circuit in an inkjet printer is an important element in inkjet printing technology. Because each type of inkjet printer needs to be matched with a corresponding inkjet head, and various inkjet heads have special specifications including characteristics of structure, ink used, number of nozzles, control circuit, etc., a compatible printing system is needed to cooperate with the inkjet printer through an inkjet head identification circuit, specifically, the inkjet head identification circuit includes fuses, metal oxide semiconductor field effect transistor (mosfet) counter fuses and related circuit elements, and is used for storing information including, but not limited to, ink cartridge serial numbers, ink types, ink capacities, ink colors, matching information between inkjet head and inkjet printer, etc., so as to ensure printing quality and efficiency.

Referring to fig. 1A and 1B, a conventional matching and controlling method between an ink cartridge 10 and a printer 30 is described, wherein the ink cartridge 10 includes an ink jet head chip 100A, the ink jet head chip 100A stores the information of the serial number, the ink type, the matching information between the ink jet head and the printer, and the conventional ink jet head chip 100A further includes a dot control circuit 110 and an ink jet head identification circuit 120 respectively coupled to the ink jet control terminal 320 and the identification signal terminal 310 of the printer 30. After receiving the ejection signal from the ink jet control end 320 of the printer 30, the above-mentioned control circuit 110 starts the corresponding ejection point on the ink cartridge 10 to eject ink drops, and the ink jet head identification circuit 120 mainly provides the ink jet head identification signal to the identification signal end 310 of the printer 30, such as the information of the serial number of the ink cartridge, the type of ink, the matching information between the ink jet head and the printer, the ink content, etc.

However, the prior art is disadvantageous in that the inkjet head chip 100A has a relatively high chip temperature and a relatively strong temperature change due to the need of heating the ink during printing, as shown in fig. 1C, the conventional method of integrating the inkjet head identification circuit 120 into the inkjet head chip 100A is easy to increase the probability of malfunction of the components in the inkjet head identification circuit 120 due to the above temperature factors, thereby affecting the stability of identification signal identification during printing, resulting in lower reliability of the conventional technology, or only performing further reinforcement design on materials or structures, so that only one of the reliability and manufacturing cost of the device can be selected. Furthermore, since the printer 30 of the prior art burns the printhead chip 100A according to the ink content recorded in the printhead identification circuit 120 after the ink consumption is completed, the operation of the ink cartridge 10 is permanently disabled, which represents that the information recorded by the printhead chip 100A of the prior art is disposable, so that the ink cartridge 10 in the current market can be used only once, and after the ink consumption, the ink cartridge 10 is permanently disabled, but the mechanical structure of the ink cartridge 10 is still considered to be still intact, and as the current environmental regulations are becoming stricter, the environmental concepts of market consumers and the mass population are gradually raised, and the economic resources of enterprises are considered to be used, the conventional art can cause the waste of the ink cartridge 10 in use, so that in the current market, there is still a need for improving the existing ink cartridge 10 or the matching control mode between the ink cartridge 10 and the printer 30, so that the ink cartridge 10 can be reused and the environmental protection and economic purposes are met.

Disclosure of Invention

Based on the above reasons, the present invention provides an identification chip, which is electrically connected to an inkjet head chip or a housing of an ink cartridge, which is located on an outer layer of the ink cartridge, that is, is electrically connected to a flexible circuit board of the ink cartridge, by using an identification signal provided by the identification chip, the inkjet head identification signal provided by the original inkjet head chip is optimized, so that the ink cartridge connected to the identification chip can continue to provide printing for a printer after filling new ink, instead of being a disposable consumable product in the prior art. In addition, the identification wafer is an independent element, so the identification wafer is more flexible in the arranged position and is less susceptible to the influence of the heat energy generated during the operation of the ink jet head wafer, so that the identification wafer can also consider the economic cost while improving the reliability. In the memory unit of the identification chip, in order to increase the diversity of the circuit element composition in the memory unit and in order to make the information records such as the serial number, identification code (Identification Code), ink type, ink capacity, ink color, spray hole number, manufacturing date, delivery date, ink cartridge capacity change (ink capacity), number of times of use of the ink cartridge on-machine and the like stored in the memory unit structure of the identification chip more detailed and complete, the difficulty of copying the identification chip by reverse engineering can be increased, the cost of manufacturing the ink cartridge by enterprises can be reduced while the ink cartridge is reused, but the intelligent property protection effect in the ink cartridge can be maintained, so the invention discusses the circuit structure in the identification chip for achieving the purposes, and the detailed technical scheme is as follows.

The invention provides an identification chip, which comprises the following elements that the identification chip provides an identification signal and is matched with a printer, wherein the identification chip is provided with a plurality of memory units which form an array structure and further comprises a first transistor and a fuse, namely, the main type of each single memory unit can be selected from the first transistor or the fuse. In the invention, by configuring a plurality of memory cells in the identification chip to form the type and the number of the array structure, namely the states of the first transistor and the fuse, the information recorded in the identification chip can be interpreted when the identification signal of the memory cells is read. In one embodiment of the present invention, the first transistor is a metal oxide semiconductor field effect transistor (MOSFET Anti-Fuse), and the first transistor and the Fuse are formed on the same identification chip.

According to the present invention, the first transistor may be a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and may be selected from an N-type metal oxide semiconductor field effect transistor (NMOS) or a P-type metal oxide semiconductor field effect transistor (PMOS) according to the application. In addition, the fuse may be selected from a polysilicon fuse (polyfuse) or a metal fuse (metal fuse) as required by the application.

According to the present invention, each memory cell further includes an identification signal terminal, a data terminal, and a second transistor. Wherein the identification signal terminal is connected to the first transistor or the fuse, the data terminal is connected to the gate of the second transistor, and the first transistor and the fuse are connected to the second transistor.

Drawings

The detailed description and examples of the invention described below should be construed as providing a full appreciation of the invention, however, it should be understood that this is done solely by way of reference to the accompanying drawings, which are to be regarded as illustrative of the application of the invention, and not as a limitation of the invention to a particular embodiment.

FIG. 1A illustrates the structure of a conventional ink cartridge and the arrangement of the ink jet head chip.

FIG. 1B illustrates a circuit architecture of a conventional printer and inkjet head die connection.

FIG. 1C illustrates a circuit architecture for a conventional printer and inkjet head die attach.

FIG. 2A illustrates a first arrangement for attaching an identification wafer to an ink cartridge.

FIG. 2B illustrates a second arrangement for attaching an identification wafer to an ink cartridge.

FIG. 2C illustrates a third arrangement for attaching an identification wafer to an ink cartridge.

Fig. 2D illustrates an arrangement for identifying a wafer.

Fig. 2E illustrates the circuitry of the printer, inkjet head die, and the first circuit architecture after the identification die is attached.

Fig. 2F illustrates the circuitry of the printer, inkjet head die, and the second and third circuit architectures after the identification die is attached.

Fig. 3A illustrates a structure in which an identification chip is disposed on a flexible circuit board.

FIG. 3B illustrates an array structure of memory cells included in the identification chip to record information in the ink jet head.

FIG. 4A illustrates a circuit structure of one embodiment of a memory cell according to the present invention.

FIG. 4B illustrates a circuit structure of one embodiment of a memory cell according to the present invention.

FIG. 4C illustrates a circuit structure of one embodiment of a memory cell according to the present invention.

FIG. 4D illustrates a circuit structure of one embodiment of a memory cell according to the present invention.

FIG. 4E illustrates a fuse in the circuit structure of the memory cell according to an embodiment of the present invention.

FIG. 5A illustrates a cross-sectional structure of the N-type MOSFET before programming in the present invention.

FIG. 5B illustrates a cross-sectional structure of the N-type MOSFET after programming in accordance with the present invention.

FIG. 5C illustrates a cross-sectional structure of the PMOS transistor before programming in the present invention.

FIG. 5D illustrates a cross-sectional structure of a PMOS transistor after programming in accordance with the present invention

FIG. 6A illustrates an array structure of first transistors and fuses in one embodiment of the memory cell of the present invention.

FIG. 6B illustrates an array structure of first transistors and fuses according to another embodiment of the memory cell of the present invention.

[ Symbolic description ]

10 Ink cartridge

100 Flexible circuit board

100A inkjet head wafer

110 Spray point control circuit

120 Inkjet head identification circuit

200 Flexible circuit board

210 Identification wafer

211 Memory cell

310. 211A identification signal terminal

211B data terminal

211C first transistor

211E second transistor

211F fuse

30 Printer

320 Inkjet control end

G: gate electrode

N-type

P-type

GOX gate oxide layer

Detailed Description

The invention will be described in detail with reference to preferred embodiments and aspects. The following description provides specific details of the invention to provide a thorough understanding of the implementations of the embodiments. It will be understood by those skilled in the art that the present invention may be practiced without these specific details. Furthermore, the invention may be practiced and carried out in other embodiments, which specific details are set forth in the present description may be utilized to advantage, and various modifications or alterations may be made without departing from the spirit of the present invention, thus, the present invention will be described in terms of preferred embodiments and aspects, which are provided to illustrate the structure of the present invention and are only for the purpose of illustrating the invention and not for the purpose of limiting the claimed invention. The terminology used in the following description is to be interpreted in its broadest reasonable manner so as to be able to be utilized in conjunction with a detailed description of certain specific embodiments of the invention, as will be apparent to those skilled in the art from a detailed description of certain specific embodiments of the invention that follows, as may be desired in the fabrication or application of the invention. In this specification, the Fuse may be referred to simply as Fuse, and the first transistor may be referred to simply as MOS or MOS-Anti-Fuse in this specification, and in order to transmit a signal for Identification (ID), the identification signal terminals 310 and 211A are provided in the printer 30 and the memory unit 211, respectively, and those skilled in the art will understand the configuration of the identification signal terminals 310 and 211A as will be described by the context of the specification and the drawings.

Referring to fig. 2A, 2E, 3A and 3B, in a first embodiment of the present invention, an identification chip 210 is provided on a flexible circuit board 200, the flexible circuit board 200 is attached to and electrically connected to an inkjet head chip 100A in a flexible circuit board 100 disposed on an outer layer of an ink cartridge 10, wherein the identification chip 210 includes a plurality of memory units 211, the plurality of memory units 211 are arranged in the identification chip 210 to form an array structure, the plurality of memory units 211 include a first transistor 211C and a fuse 211F, and by configuring the order and the number of states of the first transistor 211C and the fuse 211F in the identification chip 210, information is recorded, and the ink cartridge 10 is matched with the printer 30 by transmitting identification signals. In the embodiment of the invention, the first transistor 211C is a metal oxide semiconductor field effect transistor (MOSFET Anti-Fuse), the Fuse 211F is selected from a polysilicon Fuse (polyfuse) or a metal Fuse (metal Fuse), and the first transistor 211C and the Fuse 211F are formed on the same identification chip 210. The array structure formed by the memory unit 211 provides, but is not limited to, information such as the serial number, identification code (Identification Code), ink type, ink capacity, ink color, number of nozzles, manufacturing date, delivery date, ink cartridge capacity change (ink capacity), number of times of use of the ink cartridge, etc. corresponding to the matching of the printer 30, so that the printer 30 can identify the type and kind of the ink jet head in the ink cartridge 10.

Referring to fig. 2A and 2E, according to the above embodiment of the invention, the flexible circuit board 200 is configured and attached on the flexible circuit board 100, and has an identification chip 210, and when the ink cartridge 10 is installed in the printer 30, the identification chip 210 is electrically coupled to the identification signal terminal 310 and the ink jet control terminal 320 in the printer 30. The dot control circuit 110 in the inkjet head chip 100A is coupled to the inkjet head identification circuit 120 and the inkjet control terminal 320 in the printer 30 for transmitting the jetting signal. When the identification chip 210 is connected to the printer 30, the ejection signal of the inkjet head chip 100A is maintained or optimized, and the identification signal provided by the identification chip 210 replaces or optimizes the original inkjet head identification signal, so that the inkjet head chip 100A can be burned by the printer 30 due to the exhaustion of ink in the previous use, and the ink cartridge 10 which can be discarded after only one time can still be used for recycling the ink cartridge 10 by transmitting the identification signal to the identification signal terminal 310 after the ink cartridge 10 is filled, and the printer 30 transmits the inkjet signal to the inkjet control terminal 320 to start the inkjet control circuit 110 to eject the corresponding inkjet droplet on the ink cartridge 10 again according to the identification signal, so that the ink cartridge 10 has the recycling effect, thereby achieving the purpose of the present invention.

Referring to fig. 2B, 2C, 2D and 2F, according to another two embodiments of the present invention, the identification chip 210 may also be independently attached to the flexible circuit board 100 of the ink cartridge 10 itself or the housing of the ink cartridge 10, and when the ink cartridge 10 is installed into the printer 30, the identification chip 210 is electrically coupled to the identification signal terminal 310 and the inkjet control terminal 320 in the printer 30. The dot control circuit 110 in the printhead die 100A is coupled to the ink jet control terminal 320 in the printer 30 for transmitting the jetting signals. The advantage of this arrangement is that the positions of the identification wafer 210 and the inkjet head wafer 100A are independent of each other, so that the thermal energy generated by the inkjet head wafer 100A during operation or the temperature rise and fall variation during the inkjet process can be controlled to be far away from the position of the identification wafer 210, so as to ensure that the identification wafer 210 is not affected by the temperature variation during the process of transmitting the identification signal to the greatest extent, thereby achieving the purpose of improving the reliability of the device of the invention.

According to an aspect of the present invention, the MOSFET Anti-Fuse and the Fuse 211F selected by the first transistor 211C can record the specification parameters of the identification chip 210, such as the serial number of the ink cartridge, the identification code, the ink type, the ink capacity, the ink color, the number of nozzles, the date of manufacture, the date of delivery, or any combination thereof. In the embodiment of the invention, since the MOSFET Anti-Fuse cannot see the difference between the front and back in the appearance of the identification chip 210 no matter whether it goes through the burning stage, and no matter whether the identification chip 210 is read, burned or used, a specific software algorithm is required to be matched with the identification chip 210, even if the Fuse 211F of the invention is completely copied by the security attacker from the perspective of intellectual property and industrial utilization, the identification chip 210 adopting the invention cannot be forged by reverse engineering without the information of whether the MOSFET Anti-Fuse goes through the burning stage, thereby achieving the purposes of enhancing the security, guaranteeing the rights of both consumers and manufacturers in the industry, achieving the purposes of ensuring more complete encryption function and recordable information, and simultaneously having the advantages of simple structure, easy control of cost and repeated use of the ink cartridge 10.

As described above, please continue to refer to fig. 4A, 4B, 4C, and 4D, wherein in the embodiment of the present invention, the first transistor 211C in fig. 4A and 4B is P-type, and the first transistor 211C in fig. 4C and 4D is N-type. In addition, in the embodiment of the present invention, in order to provide the function of burning the first transistor 211C and the fuse 211F, each memory cell 211 further includes an identification signal terminal 211A, a data terminal 211B, and a second transistor 211E. The identification signal terminal 211A transmits an identification potential and is connected to the first transistor 211C or the fuse 211F in the memory unit 211 for controlling the first transistor 211C or the fuse 211F to be burned/not burned, and the data terminal 211B transmits a data potential and is connected to the gate G of the second transistor 211E, and the first transistor 211C or the fuse 211F is connected to the second transistor 211E. The memory unit 211 controls the output of the identification signal by controlling the data potential and the identification potential. In some embodiments of the present invention, the first transistor 211C may be selected from Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and may be selected from N-type or P-type, so that the memory cells 211 may be selected from the types of the first transistor 211C and the fuse 211F according to practical requirements, and any combination of the types may be performed on the array structure formed by the plurality of memory cells 211, thereby improving the flexibility in information recording.

Referring to fig. 5A, 5B, 5C, and 5D, states of the first transistor 211C when the memory cell 211 is burned and not burned are illustrated, and according to the states, the memory cell 211 can output a binary (binary bit) identification signal. In fig. 5A and 5B, the case where the first transistor 211C is an N-type mosfet is illustrated in an embodiment of the present invention. In fig. 5A, the gate electrode G of the first transistor 211C has a gate oxide layer GOX at the lower end, and when the identification potential provided by the identification signal terminal 211A is smaller than a breakdown potential, the structure of the gate oxide layer GOX is intact, and when the data terminal 211B provides a high potential at this time, the second transistor 211E will be in a conducting state, and the identification signal terminal 211A will be read out of a high resistance state in the memory cell 211, and the identification signal outputted by the identification signal terminal will indicate that the memory cell 211 is in an unfired state. On the other hand, in fig. 5B, when the potential provided by the identification signal terminal 211A is greater than the breakdown potential, the structure of the gate oxide layer GOX is broken down, so that the gate G is connected to the substrate (substrate) of the first transistor 211C to generate irreversible damage, which causes the identification signal terminal 211A to be read out of a low resistance state in the memory cell 211, and the output identification signal indicates that the memory cell 211 is in a burned state, thereby achieving the purpose of outputting a binary identification signal. It should be noted that, in the present invention, the binary identification signals are not limited to 0 and 1, which necessarily correspond to low resistance or high resistance, but 1 and 0 may also correspond to low resistance or high resistance, respectively, which may be set, changed or modified according to practical applications. In addition, in fig. 5C and 5D, it is described that the first transistor 211C may be a P-type mosfet, and the voltage level provided by the identification signal terminal 211A may be controlled to control whether the gate oxide layer GOX is broken down, so as to burn/un-burn the memory unit 211, thereby achieving the purpose of controlling and outputting the binary identification signal.

In the embodiment of the present invention, referring to fig. 6A and 6B, an array structure of a plurality of memory cells 211 in an identification chip 210 is illustrated, wherein the array structure includes a Fuse 211F and a combination of first transistors 211C (i.e., MOS Anti-Fuse). In the combination of the identification chips 210, fig. 6A and 6B illustrate that the variety of each memory cell 211 in the identification chip 210 can be increased, that is, when the array structure of the identification chip 210 has N memory cells 211, the array structure is configured to have multiple recording data, so that the manufacturing cost of the identification chip 210 with coexisting Fuse, MOS Anti-Fuse can be well controlled in view of the economical aspect, and if the recording of the identification signal is considered, the recording of the identification chip 210 can be more and more complete information, such as the cartridge number, the identification code (Identification Code), the ink type, the ink capacity, the ink color, the inkjet head temperature, etc., due to the more recording type selection of the identification chip 210. Finally, in terms of information security and intellectual property, since the inkjet head chip 100A needs to be matched with related recognition software, recognition program or recognition algorithm in the process of matching with the printer 30, the burning type and the pluripotency of the recognition chip 210 are increased, and the tightness of the recognition chip 210 in terms of security encryption can be improved by matching with the algorithm, thereby guaranteeing the related rights and interests of the intellectual property and the user of the enterprise. It should be noted that the array structure of the memory cells 211 shown in fig. 6 is only illustrative, and the placement positions (i.e., the selection type and the pattern of each memory cell 211) and the number of bits in the array structure of the Fuse and the MOS Anti-Fuse are not limited in practical application of the present invention, for example, fig. 6A is one of the aspects of the present invention, and fig. 6B is another implementation of the foregoing description, so those skilled in the art can select or modify the placement positions and the number of bits of the Fuse and the MOS Anti-Fuse in the array structure according to practical application.

In view of the above, the present invention proposes a structure for setting memory cells in a recognition chip recognition circuit, so that the ink cartridge can be reused, the environmental protection performance of the product can be improved, and the protection of intellectual property rights can be maintained.

Claims

1. An identification chip, comprising:

A plurality of memory cells are arranged to form an array structure, and the array structure also includes:

a first transistor; and

A fuse;

The identification chip is connected and matched with the printer by configuring the quantity, combination and position of the first transistor and the fuse in the array structure, and transmits an identification signal to the printer.

2. The identification chip as claimed in claim 1, wherein the first transistor is selected from an N-type metal oxide semiconductor field effect transistor (NMOS) or a P-type metal oxide semiconductor field effect transistor (PMOS).

3 . The identification chip as claimed in claim 1 , wherein the fuse is selected from a polysilicon fuse or a metal fuse.

4. The identification chip as claimed in claim 1, wherein the plurality of memory units further comprises:

an identification signal terminal connected to the fuse or the first transistor to provide an identification potential;

a data terminal, providing a data potential; and,

a second transistor, the second transistor is connected to the fuse or the first transistor, and a gate of the second transistor is connected to the data terminal;

The plurality of memory units read the identification signal by adjusting the data potential and the identification potential.

5. An identification chip as described in claim 4, wherein when the identification signal end is connected to the first transistor, and the identification potential is less than a breakdown potential, and the data end provides a high potential, the identification signal end will be in a high resistance state in the corresponding multiple memory cells, and the output identification signal shows that the corresponding multiple memory cells are in an unburned state.

6 . The identification chip as claimed in claim 5 , wherein the structure of the gate oxide layer (GOX) of the first transistor is in a good state.

7. An identification chip as described in claim 4, wherein when the identification signal end is connected to the first transistor and the identification potential is greater than a breakdown potential, the identification signal end will be in a low resistance state in the corresponding multiple memory units, and the output identification signal shows that the corresponding multiple memory units are in a burned state.

8 . The identification chip as claimed in claim 7 , wherein a structure of a gate oxide layer (GOX) of the first transistor is in a collapsed state.

9. The identification chip as described in claim 1, wherein the information recorded in the identification chip includes ink cartridge serial number, identification code, ink type, ink capacity, ink color, number of nozzles, manufacturing date, factory date, or any combination thereof.