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TWI838798B - 晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構 - Google Patents

晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構 Download PDF

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TWI838798B
TWI838798B TW111127750A TW111127750A TWI838798B TW I838798 B TWI838798 B TW I838798B TW 111127750 A TW111127750 A TW 111127750A TW 111127750 A TW111127750 A TW 111127750A TW I838798 B TWI838798 B TW I838798B
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chip
circuit board
flexible circuit
connection pad
electrically connected
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TW111127750A
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TW202406414A (zh
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于鴻祺
林俊榮
古瑞庭
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華東科技股份有限公司
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Priority to TW111127750A priority Critical patent/TWI838798B/zh
Priority to KR2020230001403U priority patent/KR20240000183U/ko
Priority to US18/220,272 priority patent/US20240030124A1/en
Priority to JP2023002576U priority patent/JP3243746U/ja
Publication of TW202406414A publication Critical patent/TW202406414A/zh
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Publication of TWI838798B publication Critical patent/TWI838798B/zh

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Abstract

一種晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構，其中該晶片封裝單元中的一軟質電路板之至少一第一連接墊、至少一第二連接墊與至少一第三連接墊彼此之間能藉由該軟質電路板之電路而互相電性連結，其中一晶片之一正面上所設的至少一晶墊是先與該軟質電路板之各該第一連接墊電性連結，再藉由該軟質電路板之各該第二連接墊或各該第三連接墊以進一步與外部電性連結，實現了該晶片封裝單元中的該晶片得藉由該表面或該背面來對外電性連結的功效，達成製程簡化及節省能源，以利於製造端降低成本，且能減少該封裝結構的體積。

Description

晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構
本發明是一種封裝結構，尤指一種晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構。
在習知的晶片封裝結構中，具有一種藉由矽穿孔(TSV，Through Silicon Via)之技藝使晶片封裝結構的表面能電性連結至晶片封裝結構的背面(即相對於表面)的雙層晶片封裝結構，藉以實現晶片封裝結構中的晶片得藉由晶片封裝結構的表面或背面來對外電性連結。
但是，上述習知的晶片封裝結構必須在晶片封裝結構的表面往背面貫穿出一矽穿孔，以在該矽穿孔內設有與晶片封裝結構中晶片電性連結的連結線路，藉此實現晶片得藉由晶片封裝結構的表面或背面來對外電性連結的功效，然而，該矽穿孔的構成造成了製造端的製程增加，且晶片封裝結構一般具有金屬的結構層而硬度較硬，這使得該矽穿孔的構成需耗費較多能源，不利於製造端降低成本。此外，構成該矽穿孔亦可能損傷晶片封裝結構內部線路的風險，使得內部線路的設計需要重新規劃，而增加了製造端的成本。
因此，一種有效地解決習知晶片封裝結構之矽穿孔的構成造成了製造端的製程增加及能源耗費的問題，且不需要重新規劃晶片封裝結構內部線路的晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構，為目前相關產業之迫切期待者。
本發明之主要目的在於提供一種晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構，其中該晶片封裝單元中的一軟質電路板之至少一第一連接墊、至少一第二連接墊與至少一第三連接墊彼此之間能藉由該軟質電路板之電路而互相電性連結，其中一晶片之一正面上所設的至少一晶墊是先與該軟質電路板之各該第一連接墊電性連結，再藉由該軟質電路板之各該第二連接墊或各該第三連接墊以進一步與外部電性連結，實現了該晶片封裝單元中的該晶片得藉由該表面或該背面來對外電性連結的功效，有效地解決習知晶片封裝結構之矽穿孔的構成造成了製造端的製程增加及能源耗費的問題，且不需要重新規劃晶片封裝結構內部線路。
為達成上述目的，本發明提供一種晶片封裝單元，該晶片封裝單元包含有一晶片及一軟質電路板；該晶片具有一正面、一背面及一側邊，該正面上設有至少一晶墊(Die Pad)，該背面是相對於該正面，該側邊是介於該正面與該背面之間；該軟質電路板內部設有預先設計之電路，該軟質電路板是以截面彎摺成C型形狀地夾設在該晶片外部，且該軟質電路板具有一第一表面及一相對於該第一表面的第二表面，該第一表面是貼覆在該晶片之該正面、該側邊、及該背面上，且該第一表面上設有至少一第一連接墊供分別對應於該晶片的各該晶墊，使得該軟質電路板之電路能藉由各該第一連接墊以與各該晶墊電性連結，其中該第二表面具有至少一第二連接墊及至少一第三連接墊，各該第二連接墊是相對於該晶片之該背面，各該第三連接墊是相對於該晶片之該正面，其中該軟質電路板之各該第一連接墊、各該第二連接墊與各該第三連接墊彼此之間能藉由該軟質電路板之電路而互相電性連結；其中該晶片之該正面上所設的 各該晶墊是先與該軟質電路板之各該第一連接墊電性連結，再藉由該軟質電路板之各該第二連接墊或各該第三連接墊以進一步與外部電性連結，達成製程簡化及節省能源，以利於製造端降低成本。
在本發明一較佳實施例中，各該晶墊與各該連接墊之間進一步包含有一保護層。
本發明更提供一種晶片封裝單元之製造方法，該製造方法包含下列步驟：步驟S1：提供一晶片，該晶片具有一正面、一背面及一側邊，該正面上設有至少一晶墊(Die Pad)，該背面是相對於該正面，該側邊是介於該正面與該背面之間；步驟S2：提供一軟質電路板，該軟質電路板內部設有預先設計之電路，且該軟質電路板具有一第一表面及一相對於該第一表面的第二表面，該第一表面上設有至少一第一連接墊供分別對應於該晶片的各該晶墊，該第二表面具有至少一第二連接墊及至少一第三連接墊，其中該軟質電路板之各該第一連接墊、各該第二連接墊與各該第三連接墊彼此之間能藉由該軟質電路板之電路而互相電性連結；及步驟S3：使該軟質電路板截面彎摺成C型形狀地夾設在該晶片外部，其中該第一表面是貼覆在該晶片之該正面、該側邊、及該背面上，且該軟質電路板之電路能藉由各該第一連接墊以與各該晶墊電性連結，其中各該第二連接墊是相對於該晶片之該背面，其中各該第三連接墊是相對於該晶片之該正面，其中該晶片之該正面上所設的各該晶墊是先與該軟質電路板之各該第一連接墊電性連結，再藉由該軟質電路板之各該第二連接墊或各該第三連接墊以進一步與外部電性連結，藉此完成一晶片封裝單元。
本發明更提供一種由晶片封裝單元所堆疊形成的封裝結構，該封裝結構包含至少二晶片封裝單元、至少一連接線路及至少一絕緣層；其中各該 各該晶片封裝單元是形成一上一下的對應關係而堆疊在一起；其中各該連接線路是設於上一各該晶片封裝單元及下一各該晶片封裝單元之間，並與上一各該晶片封裝單元之各該第二連接墊及下一各該晶片封裝單元之各該第三連接墊電性連結，以供上一各該晶片封裝單元與下一各該晶片封裝單元能藉由各該連接線路而互相電性連結；其中各該絕緣層是包覆各該晶片封裝單元及各該連接線路並填滿該封裝結構之空隙，且各該絕緣層具有至少一上開口及至少一下開口，各該上開口是供各該晶片封裝單元中最上方的各該晶片封裝單元之各該第三連接墊對外露出，各該下開口是供各該晶片封裝單元中最下方的各該晶片封裝單元之各該第二連接墊對外露出，其中各該晶片封裝單元能藉由各該絕緣層的各該上開口或各該下開口以對外電性連結，以利於晶片封裝產品體積能縮小化且降低製造端成本。
在本發明一較佳實施例中，其中各該絕緣層的各該下開口上進一步設有一錫球，各該晶片封裝單元能藉由各該錫球以對外電性連結。
在本發明一較佳實施例中，其中該封裝結構進一步藉由各該下開口中的各該第二連接墊以與一電路板(PCB)電性連結。
1:封裝結構
1a:晶片封裝單元
10:晶片
10a:正面
10b:背面
10c:側面
11:晶墊
12:保護層
20:軟質電路板
20a:第一表面
20b:第二表面
21:第一連接墊
22:第二連接墊
22:第三連接墊
30:連接線路
40:絕緣層
41:上開口
42:下開口
50:錫球
2:電路板
圖1為本發明之晶片封裝單元的側面剖視的平面示意圖。
圖2為本發明之晶片的側面剖視的平面示意圖。
圖3為本發明之軟質電路板的側面剖視的平面示意圖。
圖4為圖1的分解示意圖。
圖5為本發明之封裝結構的側面剖視的平面示意圖。
圖6為本發明之封裝結構具有三個晶片封裝單元的側面剖視的平面示意圖。
配合圖示，將本發明的結構及其技術特徵詳述如後，其中各圖示只用以說明本發明的結構關係及相關功能，因此各圖示中各元件的尺寸並非依實際比例畫製且非用以限制本發明。
參考圖1及4，本發明提供一種晶片封裝單元1a，該晶片封裝單元1a包含一晶片10及一軟質電路板(FPC，Flexible Printed Circuit)20。
該晶片10具有一正面10a、一背面10b及一側邊10c，該正面10a上設有至少一晶墊11(Die Pad)，該背面10b是相對於該正面10a，該側邊10是介於該正面10a與該背面10b之間如圖2所示；其中在圖1所示之實施例中，本發明的各該晶墊11的數量為二個但不限制。
該軟質電路板20內部設有預先設計之電路，該軟質電路板20是以截面彎摺成C型形狀地夾設在該晶片10外部如圖1所示，且該軟質電路板20具有一第一表面20a及一相對於該第一表面20a的第二表面20b如圖3所示，該第一表面20a是貼覆在該晶片10之該正面10a、該側邊10c、及該背面10b上如圖1所示，且該第一表面20a上設有至少一第一連接墊21供分別對應於該晶片10的各該晶墊11，使得該軟質電路板20之電路能藉由各該第一連接墊21以與各該晶墊11電性連結如圖1所示；其中該第二表面20b具有至少一第二連接墊22及至少一第三連接墊23，各該第二連接墊22是相對於該晶片10之該背面10b，各該第三連接墊23是相對於該晶片10之該正面10a如圖1所示；其中該軟質電路板20之各該第一連接墊21、各該第二連接墊22與各該第三連接墊23彼此之間能藉由該軟質電路板20之電 路而互相電性連結；其中在圖1所示的實施例中，本發明的該第一連接墊21、各該第二連接墊22及各該第三連接墊23的數量皆為二個但不限制。
該晶片10之該正面10a上所設的各該晶墊11是先與該軟質電路板20之各該第一連接墊21電性連結，再藉由該軟質電路板20之各該第二連接墊22或各該第三連接墊23以進一步與外部電性連結如圖1所示。
其中，各該晶墊11與各該連接墊21之間進一步包含有一保護層12但不限制如圖1所示，以利於增加產品的良率提升。
參考圖1至4，本發明更提供一種晶片封裝單元的製造方法，其包含下列步驟：
步驟S1：提供一晶片10，該晶片10具有一正面10a、一背面10b及一側邊10c，該正面10a上設有至少一晶墊11(Die Pad)，該背面10b是相對於該正面10a，該側邊10是介於該正面10a與該背面10b之間如圖2所示。
步驟S2：提供一軟質電路板20，該軟質電路板20內部設有預先設計之電路，且該軟質電路板20具有一第一表面20a及一相對於該第一表面20a的第二表面20b如圖3所示，該第一表面20a上設有至少一第一連接墊21供分別對應於該晶片10的各該晶墊11如圖1所示，該第二表面20b具有至少一第二連接墊22及至少一第三連接墊23如圖3所示，其中該軟質電路板20之各該第一連接墊21、各該第二連接墊22與各該第三連接墊23彼此之間能藉由該軟質電路板20之電路而互相電性連結。
步驟S3：使該軟質電路板20截面彎摺成C型形狀地夾設在該晶片10外部如圖4所示，其中該第一表面20a是貼覆在該晶片10之該正面10a、該側邊10c、及該背面10b上，且該軟質電路板20之電路能藉由各該第一連接墊21以與各該晶墊11電性連結如圖1所示，其中各該第二連接墊22是相對於該晶片10之該背面10b如圖1所示，其中各該第三連接墊23是相對於該晶片10之該正面10a如圖1所 示，其中該晶片10之該正面10a上所設的各該晶墊11是先與該軟質電路板20之各該第一連接墊21電性連結，再藉由該軟質電路板20之各該第二連接墊22或各該第三連接墊23以進一步與外部電性連結，藉此完成一晶片封裝單元1a如圖1所示。
參考圖5及6，本發明更提供一種由晶片封裝單元所堆疊形成的封裝結構1，該封裝結構1包含至少二晶片封裝單元1a、至少一連接線路30及至少一絕緣層40。
各該晶片封裝單元1a是形成一上一下的對應關係而堆疊在一起如圖5及6所示；其中在圖6所示之實施例中，本發明的各該晶片封裝單元1a的數量為三個但不限制。
各該連接線路30是設於上一各該晶片封裝單元1a及下一各該晶片封裝單元1a之間，並與上一各該晶片封裝單元1a之各該第二連接墊22及下一各該晶片封裝單元1a之各該第三連接墊23電性連結如圖5及6所示，以供上一各該晶片封裝單元1a與下一各該晶片封裝單元1a能藉由各該連接線路30而互相電性連結；其中在圖6所示之實施例中，本發明的各該連接線路30的數量為三個但不限制。
各該絕緣層40是包覆各該晶片封裝單元1a及各該連接線路30並填滿該封裝結構1之空隙，且各該絕緣層40具有至少一上開口41及至少一下開口42如圖5及6所示，各該上開口41是供各該晶片封裝單元1a中最上方的各該晶片封裝單元1a之各該第三連接墊23對外露出，各該下開口42是供各該晶片封裝單元1a中最下方的各該晶片封裝單元1a之各該第二連接墊22對外露出如圖5及6所示；其中在圖6所示之實施例中，本發明的各該上開口41及各該下開口42的數量皆為二個但不限制。
其中，各該晶片封裝單元1a能藉由各該絕緣層40的各該上開口41或各該下開口42以對外電性連結如圖5及6所示。
此外，各該絕緣層40的各該下開口42上進一步設有一錫球50但不限制如圖5及6所示，各該晶片封裝單元1a能藉由各該錫球50以對外電性連結。
參考圖6，該封裝結構1進一步藉由各該下開口42中的各該第二連接墊22以與一電路板(PCB)2電性連結但不限制，以利於增加產品的市場競爭力。
本發明的該晶片封裝單元1a及其製造方法及由其所堆疊形成的該封裝結構2具有以下優點：
(1)本發明的該晶片封裝單元1a中的該軟質電路板20之各該第一連接墊21、各該第二連接墊22與各該第三連接墊23彼此之間能藉由該軟質電路板20之電路而互相電性連結，其中該晶片10之該正面10a上所設的各該晶墊11是先與該軟質電路板20之各該第一連接墊21電性連結，再藉由該軟質電路板20之各該第二連接墊22或各該第三連接墊23以進一步與外部電性連結如圖1所示，實現了該晶片封裝單元1a中的該晶片10得藉由該表面10a或該背面10b來對外電性連結的功效，有效地解決習知晶片封裝結構之矽穿孔(TSV，Through Silicon Via)的構成造成了製造端的製程增加及能源耗費的問題，且不需要重新規劃晶片封裝結構內部線路，達成製程簡化及節省能源，以利於製造端降低成本。此外，目前人類所使用的能源大都仍取自大自然，大自然用以產生能源的材料並非都是取之不盡而用之不竭的，且部分產生能源的方式伴隨著污染，可知能源的使用與地球環境的保護息息相關，本發明因具備上述節省能源的功效，亦有利於地球環境的保護。
(2)本發明的的封裝結構1的各該晶片封裝單元1a是形成一上一下的對應關係而堆疊在一起如圖5及6所示，上一各該晶片封裝單元1a與下一各該晶片封裝單元1a能藉由各該連接線路30而互相電性連結，藉此堆疊模式以形成該封裝結構1，以使各該晶片10之間能藉其中一各該晶片10對其他各該晶片10進行 指令操作，或藉各該晶片10之間的運算功能疊加而能加乘增加總體運算的效能，以利於晶片封裝產品體積能縮小化且降低製造端成本。
以上該僅為本發明的優選實施例，對本發明而言僅是說明性的，而非限制性的；本領域普通技術人員理解，在本發明權利要求所限定的精神和範圍內可對其進行許多改變，修改，甚至等效變更，但都將落入本發明的保護範圍內。
1a‧‧‧晶片封裝單元 10‧‧‧晶片 10a‧‧‧正面 10b‧‧‧背面 10c‧‧‧側面 11‧‧‧晶墊 12‧‧‧保護層 20‧‧‧軟質電路板 20a‧‧‧第一表面 20b‧‧‧第二表面 21‧‧‧第一連接墊 22‧‧‧第二連接墊 22‧‧‧第三連接墊

Claims (5)

  1. 一種晶片封裝單元，其包含：一晶片，其具有一正面、一背面及一側邊，該正面上設有至少一晶墊(Die Pad)，該背面是相對於該正面，該側邊是介於該正面與該背面之間；及一軟質電路板，其內部設有預先設計之電路，該軟質電路板是以截面彎摺成C型形狀地夾設在該晶片外部，且該軟質電路板具有一第一表面及一相對於該第一表面的第二表面，該第一表面是貼覆在該晶片之該正面、該側邊、及該背面上，且該第一表面上設有至少一第一連接墊供分別對應於該晶片的各該晶墊，使得該軟質電路板之電路能藉由各該第一連接墊以與各該晶墊電性連結；其中該第二表面具有至少一第二連接墊及至少一第三連接墊，各該第二連接墊是相對於該晶片之該背面，各該第三連接墊是相對於該晶片之該正面；其中該軟質電路板之各該第一連接墊、各該第二連接墊與各該第三連接墊彼此之間能藉由該軟質電路板之電路而互相電性連結；其中該晶片之該正面上所設的各該晶墊是先與該軟質電路板之各該第一連接墊電性連結，再藉由該軟質電路板之各該第二連接墊或各該第三連接墊以進一步與外部電性連結；其中該晶片封裝單元的製造方法是包含下列步驟：步驟S1：提供一晶片，該晶片具有一正面、一背面及一側邊，該正面上設有至少一晶墊(Die Pad)，該背面是相對於該正面，該側邊是介於該正面與該背面之間；步驟S2：提供一軟質電路板，該軟質電路板內部設有預先設計之電路，且該軟質電路板具有一第一表面及一相對於該第一表面的第二表面，該第一表面上設有至少一第一連接墊供分別對應於該晶片的各該晶墊，該第二表面具有至少一 第二連接墊及至少一第三連接墊，其中該軟質電路板之各該第一連接墊、各該第二連接墊與各該第三連接墊彼此之間能藉由該軟質電路板之電路而互相電性連結；及步驟S3：使該軟質電路板截面彎摺成C型形狀地夾設在該晶片外部，其中該第一表面是貼覆在該晶片之該正面、該側邊、及該背面上，且該軟質電路板之電路能藉由各該第一連接墊以與各該晶墊電性連結，其中各該第二連接墊是相對於該晶片之該背面，其中各該第三連接墊是相對於該晶片之該正面，其中該晶片之該正面上所設的各該晶墊是先與該軟質電路板之各該第一連接墊電性連結，再藉由該軟質電路板之各該第二連接墊或各該第三連接墊以進一步與外部電性連結，藉此完成一晶片封裝單元。
  2. 如請求項1所述之晶片封裝單元，其中各該晶墊與各該連接墊之間進一步包含有一保護層。
  3. 一種由晶片封裝單元所堆疊形成的封裝結構，其包含：至少二晶片封裝單元，各該晶片封裝單元是如申請專利範圍請求項1至請求項2中任一項所述的該晶片封裝單元，且各該晶片封裝單元是形成一上一下的對應關係而堆疊在一起；至少一連接線路，各該連接線路是設於上一各該晶片封裝單元及下一各該晶片封裝單元之間，並與上一各該晶片封裝單元之各該第二連接墊及下一各該晶片封裝單元之各該第三連接墊電性連結，以供上一各該晶片封裝單元與下一各該晶片封裝單元能藉由各該連接線路而互相電性連結；及至少一絕緣層，各該絕緣層是包覆各該晶片封裝單元及各該連接線路並填滿該封裝結構之空隙，且各該絕緣層具有至少一上開口及至少一下開口，各該上開口是供各該晶片封裝單元中最上方的各該晶片封裝單元之各該第三連接墊對外 露出，各該下開口是供各該晶片封裝單元中最下方的各該晶片封裝單元之各該第二連接墊對外露出；其中各該晶片封裝單元能藉由各該絕緣層的各該上開口或各該下開口以對外電性連結。
  4. 如請求項3所述之封裝結構，其中各該絕緣層的各該下開口上進一步設有一錫球，各該晶片封裝單元能藉由各該錫球以對外電性連結。
  5. 如請求項3所述之封裝結構，其中該封裝結構進一步藉由各該下開口中的各該第二連接墊以與一電路板(PCB)電性連結。
TW111127750A 2022-07-25 2022-07-25 晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構 TWI838798B (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1862811A (zh) * 2005-05-11 2006-11-15 英飞凌科技股份公司 叠置半导体存储器件
US20190081420A1 (en) * 2017-09-08 2019-03-14 Advanced Flexible Circuits Co., Ltd. Stacked insertion structure for flexible circuit board

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1862811A (zh) * 2005-05-11 2006-11-15 英飞凌科技股份公司 叠置半导体存储器件
US20190081420A1 (en) * 2017-09-08 2019-03-14 Advanced Flexible Circuits Co., Ltd. Stacked insertion structure for flexible circuit board

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