:350 6 5 3 5 twf. doc/00 6 A7 五、發明說明（I) (請先閱讀背面之注意事項再填寫本頁) 本發明是有關於一種具有增加間隙高的銲墊之封裝結 構，且特別是有關於一種應用於半導體覆晶型態封裝且可 增加晶片與銲墊之間隙高度的銲墊結構。 一般而言，積體電路(Integrated Circuit, 1C)的生產，主 要分爲三個階段：矽晶片的製造、積體電路的製作及積體 電路的封裝(Package)。積體電路封裝，可說是完成積體電 路成品的最後步驟。積體電路之封裝，其目的在於提供晶 片(Die)與印刷電路板(Printed Circuit Board，PCB)或其他適 當元件之間電性連接的媒介、以及保護晶片，爲製作積體 電路成品的最後步驟。 現今電子產品之開發莫不朝向輕、薄、短、小的目標 發展，對於半導體來說即是提高其積集度(Integration)，至 於封裝技術方面，則有晶片尺寸封裝(Chip Scale Package， CSP)、覆晶構裝(Flip Chip，FC)等高密度之封裝技術的提 出。其中覆晶構裝是經常應用於晶片尺寸構裝的構裝技 術，由於其可以採用面積陣列方式(Area Array)配置焊墊， 且透過凸塊（Bump)連接承載器，故可以縮小構裝面積，並 縮短訊號傳輸路徑。 經濟部智慧財產局員工消費合作社印製 請參照第1A圖與第1C圖，其所繪示爲習知的覆晶構 裝結構的剖面示意圖。 如第1A圖所示，習知的覆晶結構構裝常採用具有較 闻積集度的基板102(Substrate)作爲承載器。在基板102表 面塗佈有一層靜罩110(Solder mask)，僅暴露出鍵墊 104(Bonding Pad)。其中銲墊的底材112可爲銅，並於其表 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 ζ95 Ο 6535twf.doc/006 A7 _ B7 五、發明說明（之） 面分別鍍上一鎮層114與一金層116,以增進與靜料（Solder) 之良好銲性。 如第1B圖所示，另一種銲墊104常見的作法，是將 銅112表面塗佈一層有機表面護層118(0rganic Surface Protection，〇SP)，可避免銲墊104表面氧化，亦可不會影 響銲墊104與銲料之銲性。但由於有機表面護層118不耐 高溫，會於銲接後分解消失。 如第1C圖所示，覆晶構裝結構係在晶片主動表 面101上，分別形成數個凸塊108，且晶片以主動表 面101面向基板102配置，並以凸塊108與銲墊1〇4電性 連接。晶片106與基板102之間會塡充一塡充物質 (Underfill，未繪示），以保護凸塊108，避免因晶片106與 基板102間熱膨脹係數不同，而承受熱應力造成疲勞破壞 (Fatigue Collapse)。在進行迴銲(Reflow)後’凸塊108會將 整個銲墊104包住，使得晶片106與基板之間的距離 變小，尤其在銲罩110與基板102之間的第一間隙120會 非常小，造成塡充物質(Underfill)塡入困難。 因此’本發明之一目的即在提供一種可增加晶片與基 板之間隙高度的銲墊結構。 本發明之另一目的在提供一種應用在覆晶產品構 裝，且可增加晶片與基板之間隙高度的銲蟄結構。 本發明之再一目的在提供一種應用在覆晶產品構 裝’僅改變銲墊之材，即可增加晶片與基板之間隙高度的 焊墊結構。 4 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） i — ------I--^i ----訂 _ — 1--— If 1^. {請先閱讀背面之注f項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 46 295 Ο 6535twf.doc/006 A7 ___B7 五、發明說明（$ ) 根據本發明之上述之目的，提出一種具有增加間隙 高的銲墊之封裝結構，至少包括：一基板、數個銲墊、一 銲罩、一晶片、以及數個凸塊。其中基板，至少具有一第 一表面。銲墊包括底材、鎳層、以及銅層自基板之第一表 面上依序疊合後，覆蓋一有機表面護層。銲罩覆蓋於基板 之第一表面，且完全暴露出銲墊。晶片具有一主動表面， 並於主動表面配置數個凸塊。其中晶片以主動表面面對基 板之第一表面配置，使得每一凸塊分別對應數個銲墊之 一，並使凸塊包覆鎳層、以及銅層，但暴露出底材。 依照本發明之較佳實施例，本發明具有增加間隙高 的銲墊之封裝結構僅將銲墊改變爲以鋁爲底材，並於底材 分別鍍上一層鎳與一層銅，因鋁、鎳、以及銅之材質彼此 間並無黏合不良的問題，具良好之作業性。銲墊外觀與傳 傳統相似，並不影響組裝製程，具良好之組裝性。而利用 鋁與銲錫銲性不良之特性，不但改善覆晶構裝產品之晶片 與基板之間隙，且具良好之產品品質與信賴性。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下 圖式之簡ifig明： 第1A隱1C圖係繪示爲習知的覆晶構裝結構的剖 面示意_ °〈:氣 第2A圖與圖係繪示根據本發明具有增加間隙高 的銲墊之封裝結構較佳實施例的剖面示意圖。 5 -------- · -------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用令國圉家標準（CNS)A4規格（210 X 297公芨） 45295 Ο 6535twf.doc/006 A7 _B7 五、發明說明（Y) 圖式之標記說明： 102 202 ： 基底 101 201 ： 主動表面 203 第一 表面 104 204 ： 銲墊 108 208 : 凸塊 106 206 ： 晶片 110 ' 210 ： 銲罩 112， 212 ： 底材 114、 214 ： 鎳層 116 金層 216 銅層 118、 218 ： 有機表面護層 120 第一間隙 220 Mhr —* 弟一 間隙 (請先閱讀背面之注意事項再填窝本頁) 經濟部智慧財產局員工消費合作社印製 實施例 請參照第2A圖與第2B圖，其所繪示根據本發明具 有增加間隙高的銲墊之封裝結構較佳實施例的剖面示意 圖。 如第2A圖所示，基板202至少具有一第一表面203。 銲墊204包括底材212，比如是銘（Aluminum)、鎳層214、 以及銅層216自基板102之第一表面203上依序疊合後， 覆蓋一有機表面護層 218(Organic Surface Protection’ OSP)。 其中鎳層214、以及銅層216具有與銲料（Solder)黏合 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公笼） 經濟部智慧財產局員工消費合作社印製 45295 Ο 6 53 5twf . doc/006 A7 _ ____B7____ 五、發明說明（Γ) (Wetting)良好之特性。有機表面護層218 (0SP)則是爲了防 止底材212、鎳層214、以及銅層216之表面產生氧化，塗 佈於銲墊204表面以防止其與外界接觸。而且有機表面護 層218更具有於銲接後分解消失之特性，不會影響銲墊204 原有之銲性。銲罩210(Solder Mask)覆蓋於基板202之第一 表面203 ’且完全暴露出銲墊204。形成銲罩層210之材質 爲絕緣材料，包括紫外線型綠漆及熱硬化型綠漆等。 如第2B圖所示，晶片206具有一主動表面201，並 於主動表面201配置數個凸塊208。其中凸塊208的材質 比如是共晶之錫鉛合金、金、或導電聚合物。晶片206以 主動表面201對基板204之第一表面203配置，使得每一 凸塊208分別對應數個銲墊204之一。若銲墊204以鋁爲 底材212,並於底材212分別鍍上一鎳層214與一銅層216， 比如以15 m的鋁爲底材212，則分別鍍上5m的鎳層214 與10 m的銅層216，因鋁、鎳、以及銅之材質彼此間並 無黏合(Wettmg)不良的問題，具良好之作業性。 而利用底材212之材質鋁與銲料（Solder)銲性不良之 特性，因此形成凸塊208之銲料不會與材質爲鋁的底材212 黏合，故在進行迴銲(Reflow)後，凸塊208僅包覆鎳層214、 以及銅層216，但暴露出該底材212 ’使整個凸塊208之位 置往上提昇。藉此便可無形中增加銲接完後之間隙高度 (Stand-off Height)，即增加覆晶構裝產品之晶片206與基板 202之銲罩210間之第二間隙220，可順利塡充一塡充物質 (Underfill，未繪示），以保護凸塊208 ’避免因晶片206與 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） II---— — — — — — ---— — — —— ^-1111111 {請先Μ讀背面之注項再填寫本頁) 經濟部智慧財1局員工消費合作社印製 45295 Ο 6535twf.doc/006 A7 五、發明說明（6 ) 基板202間熱膨脹係數不同，而承受熱應力造成疲勞破壞 (Fatigue Collapse)，具良好之產品品質與信賴性。此外， 僅將銲墊204材質改變，因此銲墊204外觀與傳統相似， 並不影響組裝製程，具良好之組裝性。 綜上所述，本發明至少具有下列優點： 1. 本發明具有增加間隙高的銲墊之封裝結構，僅將銲 墊改變爲以鋁爲底材，並於底材分別鍍上一層鎳與一層 銅，因鋁、鎳、以及銅之材質彼此間並無黏合不良的問題， 具良好之作業性。 2. 本發明具有摻雜材質的凸塊結構，僅將銲墊改變爲 以鋁爲底材，利用鋁與銲錫銲性不良之特性，不但改善覆 晶構裝產品之晶片與基板之間隙，且具良好之產品品質與 信賴性。 3. 本發明具有增加間隙高的銲墊之封裝結構，僅將銲 墊材質改變，因此銲墊外觀與傳傳統相似，並不影響組裝 製程，具良好之組裝性。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內’當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 8 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公爱） ! 裝----II 訂--------I -線 — (靖先閱讀背面之注意事項再填寫本頁}: 350 6 5 3 5 twf. Doc / 00 6 A7 V. Description of the Invention (I) (Please read the precautions on the back before filling out this page) The present invention relates to a packaging structure with solder pads with increased clearance. In particular, it relates to a pad structure applied to a semiconductor flip-chip type package and capable of increasing the height of the gap between the wafer and the pad. Generally speaking, the production of integrated circuits (1C) is mainly divided into three stages: the manufacture of silicon wafers, the manufacture of integrated circuits and the packaging of integrated circuits. Integrated circuit packaging can be said to be the last step to complete the finished integrated circuit. The package of integrated circuits is designed to provide a medium for the electrical connection between a die and a printed circuit board (PCB) or other appropriate components, and to protect the chip. It is the final step in the manufacture of a finished integrated circuit. . At present, the development of electronic products must be developed toward light, thin, short, and small goals. For semiconductors, it is to increase their integration. As for packaging technology, there is Chip Scale Package (CSP). , Flip Chip (FC), and other high-density packaging technologies. Among them, flip-chip mounting is a mounting technique often applied to wafer-size mounting. Because it can use area arrays to configure pads and connect to the carrier through bumps, it can reduce the mounting area. , And shorten the signal transmission path. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to Figures 1A and 1C for a schematic cross-sectional view of a conventional flip chip structure. As shown in FIG. 1A, the conventional flip-chip structure construction often uses a substrate 102 having a relatively high degree of accumulation as a carrier. A layer of a solder mask 110 is coated on the surface of the substrate 102, and only the bonding pad 104 is exposed. The substrate 112 of the solder pad can be copper, and the paper size in Table 3 is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm). It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ζ95 Ο 6535twf.doc / 006 A7 _ B7 V. Description of the invention The surface is plated with a ballast layer 114 and a gold layer 116, respectively, to improve the good solderability with the solder. As shown in FIG. 1B, another common method for the pad 104 is to coat the surface of the copper 112 with an organic surface protection layer 118 (0rganic Surface Protection, 0SP), which can prevent the surface of the pad 104 from oxidizing, and it will not affect The solderability between the pad 104 and the solder. However, since the organic surface protective layer 118 is not resistant to high temperatures, it will decompose and disappear after welding. As shown in FIG. 1C, the flip-chip mounting structure is formed on the active surface 101 of the wafer, forming a plurality of bumps 108, and the wafer is arranged with the active surface 101 facing the substrate 102, and the bumps 108 and the pads 104 are arranged. Electrical connection. An underfill (not shown) is filled between the wafer 106 and the substrate 102 to protect the bumps 108 and avoid fatigue damage caused by thermal stress due to different thermal expansion coefficients between the wafer 106 and the substrate 102 (Fatigue Collapse) ). After the reflow (reflow), the bump 108 will cover the entire pad 104, so that the distance between the wafer 106 and the substrate becomes smaller, especially the first gap 120 between the solder mask 110 and the substrate 102 will be very Small, making it difficult for Underfill to penetrate. Therefore, an object of the present invention is to provide a pad structure capable of increasing the height of the gap between a wafer and a substrate. Another object of the present invention is to provide a solder bump structure which can be applied to a flip-chip product structure and can increase the height of the gap between the wafer and the substrate. Yet another object of the present invention is to provide a pad structure which can be used in the structure of a flip-chip product to increase the height of the gap between the wafer and the substrate by only changing the material of the pad. 4 This paper size applies to China National Standard (CNS) A4 (210x297 mm) i — ------ I-^ i ---- Order_ — 1 --— If 1 ^. {Please read first Note f on the back, please fill in this page again) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 46 295 Ο 6535twf.doc / 006 A7 ___B7 V. Description of the invention ($) According to the above purpose of the present invention, a method with increased clearance The packaging structure of high bonding pads includes at least: a substrate, several bonding pads, a solder mask, a wafer, and several bumps. The substrate has at least a first surface. The pad includes a substrate, a nickel layer, and a copper layer that are sequentially stacked from the first surface of the substrate, and then covered with an organic surface protective layer. The solder mask covers the first surface of the substrate and completely exposes the solder pads. The chip has an active surface, and a plurality of bumps are arranged on the active surface. The wafer is arranged with the active surface facing the first surface of the substrate, so that each bump corresponds to one of several pads, and the bump is covered with a nickel layer and a copper layer, but the substrate is exposed. According to a preferred embodiment of the present invention, the packaging structure of the present invention having a pad with increased clearance only changes the pad to an aluminum substrate, and the substrate is plated with a layer of nickel and a layer of copper, respectively. There is no problem of poor adhesion between copper and copper materials, and it has good workability. The appearance of the solder pad is similar to the traditional one. It does not affect the assembly process and has good assembly properties. By using the characteristics of poor solderability between aluminum and solder, not only the gap between the wafer and the substrate of the flip-chip packaged product is improved, but it also has good product quality and reliability. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the following diagrams: The drawing is a schematic cross-sectional view of a conventional flip-chip mounting structure. Figure 2A and FIG. 2 are schematic cross-sectional views showing a preferred embodiment of a packaging structure with a pad having a high gap according to the present invention. 5 -------- · ------- Order --------- line (Please read the precautions on the back before filling out this page) This paper applies the national standard (CNS) A4 specification (210 X 297 cm) 45295 Ο 6535twf.doc / 006 A7 _B7 V. Description of the invention (Y) Mark description of the drawing: 102 202: substrate 101 201: active surface 203 first surface 104 204: Pad 108 208: Bump 106 206: Wafer 110 ′ 210: Welding cover 112, 212: Substrate 114, 214: Nickel layer 116 Gold layer 216 Copper layer 118, 218: Organic surface protective layer 120 First gap 220 Mhr — * Diyi Gap (please read the notes on the back before filling in this page) Example printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Please refer to Figures 2A and 2B, which illustrate the increased gap according to the present invention. A schematic cross-sectional view of a preferred embodiment of a packaging structure with high bonding pads. As shown in FIG. 2A, the substrate 202 has at least a first surface 203. The bonding pad 204 includes a substrate 212, such as aluminum, a nickel layer 214, and a copper layer 216, which are sequentially stacked on the first surface 203 of the substrate 102 and covered with an organic surface protection layer 218 (Organic Surface Protection '). OSP). Among them, the nickel layer 214 and the copper layer 216 are adhered to the solder (Solder) 6 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 male cage) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 45295 Ο 6 53 5twf. Doc / 006 A7 _ ____B7____ 5. Description of the Invention (Γ) (Wetting) Good characteristics. The organic surface protection layer 218 (0SP) is used to prevent the surface of the substrate 212, the nickel layer 214, and the copper layer 216 from being oxidized, and is applied on the surface of the pad 204 to prevent it from contacting the outside world. In addition, the organic surface protective layer 218 has the characteristic of disintegrating and disappearing after welding, and does not affect the original solderability of the pad 204. A solder mask 210 (Solder Mask) covers the first surface 203 'of the substrate 202 and completely exposes the solder pad 204. The material for forming the solder mask layer 210 is an insulating material, including ultraviolet-type green paint and heat-hardening type green paint. As shown in FIG. 2B, the wafer 206 has an active surface 201, and a plurality of bumps 208 are arranged on the active surface 201. The material of the bump 208 is eutectic tin-lead alloy, gold, or conductive polymer. The wafer 206 is configured with the active surface 201 opposite the first surface 203 of the substrate 204, so that each bump 208 corresponds to one of the plurality of bonding pads 204, respectively. If the pad 204 uses aluminum as the substrate 212, and a nickel layer 214 and a copper layer 216 are plated on the substrate 212, for example, 15 m of aluminum is used as the substrate 212, then a 5 m nickel layer 214 and The copper layer 216 of 10 m has good workability because the materials of aluminum, nickel, and copper have no bad adhesion (Wettmg). However, due to the poor solderability between the aluminum material and the solder (Solder) of the substrate 212, the solder forming the bump 208 does not adhere to the substrate 212 made of aluminum, so after the reflow, the bump 208 only covers the nickel layer 214 and the copper layer 216, but the substrate 212 'is exposed to raise the position of the entire bump 208 upward. This can virtually increase the stand-off height after soldering, that is, increase the second gap 220 between the wafer 206 and the solder mask 210 of the substrate 202, which can be filled smoothly. Underfill (not shown) to protect the bumps 208 'to avoid wafers 206 and 7 This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) II --------- — --- — — — — ^ -1111111 {Please read the notes on the back before filling out this page) Printed by the Employee Consumer Cooperative of the 1st Bureau of Smart Finance of the Ministry of Economic Affairs 45295 Ο 6535twf.doc / 006 A7 V. Description of the invention ( 6) The thermal expansion coefficients between the substrates 202 are different, and fatigue fatigue caused by thermal stress (Fatigue Collapse), which has good product quality and reliability. In addition, only the material of the solder pad 204 is changed, so the appearance of the solder pad 204 is similar to the traditional one, which does not affect the assembly process and has good assembly properties. To sum up, the present invention has at least the following advantages: 1. The present invention has a packaging structure that increases the bonding pads with high gaps. Only the bonding pads are changed to aluminum substrate, and the substrate is plated with nickel and a layer respectively. Copper has good workability because there is no problem of poor adhesion between aluminum, nickel, and copper materials. 2. The present invention has a bump structure of doped material. Only the solder pad is changed to aluminum as a substrate, and the poor solderability between aluminum and solder is used to improve the gap between the wafer and the substrate of the flip-chip structured product. With good product quality and reliability. 3. The present invention has a packaging structure that increases the bonding pads with a high gap, and only changes the material of the bonding pads. Therefore, the appearance of the bonding pads is similar to traditional tradition, and does not affect the assembly process, and has good assembly properties. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. 8 This paper size is applicable to China National Standard (CNS) A4 specification (21〇x 297 public love)! Packing ---- II Order -------- I-Line- (Jing first read the precautions on the back before Fill out this page}