TWI797401B - Control circuit and control method thereof - Google Patents

Abstract

A control circuit coupled between an image acquisition device and a display device is provided. The image acquisition device outputs a plurality of pieces of image data according to a working frequency. The control circuit includes a first transmission interface, a storage circuit, a processing circuit and a second transmission interface. The first transmission interface is configured to couple to the image acquisition device to receive the plurality of pieces of image data. The storage circuit is coupled to the first transmission interface to receive and store the plurality of pieces of image data. The processing circuit reads the plurality of pieces of image data stored in the storage circuit to generate a plurality of pieces of display data and generates the working frequency according to the number of the image data stored in the storage circuit. The second transmission interface is coupled to the processing circuit to output the plurality of pieces of display data to the display device.

Description

Control circuit and its control method

The present invention relates to a control circuit, in particular to a control circuit coupled between an image capture device and a display device.

In the current image processing process, a microprocessor unit (MPU) is usually utilized. However, nowadays microcontroller units (MCUs) are becoming more and more powerful and can gradually perform image processing. However, the internal storage space of the microcontroller unit is limited and cannot store a large amount of image data.

The invention provides a control circuit coupled between an image capture device and a display device. The image capture device outputs multiple image data according to a working frequency. The control circuit includes a first transmission interface, a storage circuit, a processing circuit and a second transmission interface. The first transmission interface is coupled to the image capture device for receiving image data. The storage circuit is coupled to the first transmission interface for receiving and storing image data. The processing circuit retrieves the image data stored in the storage circuit to generate multiple display data, and generates a working frequency according to the quantity of data stored in the storage circuit. The second transmission interface is coupled to the processing circuit for outputting display data to the display device.

The present invention also provides a control method, which is suitable for a control circuit, and includes receiving multiple image data, wherein the image data is provided by an image capture device; storing the image data in a storage circuit; capturing the image data The image data stored in the storage circuit is used to generate multiple display data; output the display data to a display device; and adjust a working frequency of the image capture device according to the amount of data stored in the storage circuit.

The control method of the present invention can be implemented through the control circuit of the present invention, which is hardware or firmware capable of executing specific functions, and can also be recorded in a recording medium in the form of program code, and combined with specific hardware to implement . When the program code is loaded and executed by the electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes a control circuit or an operating system for implementing the present invention.

In order to make the purpose, features and advantages of the present invention more comprehensible, the following specifically cites the embodiments, together with the accompanying drawings, for a detailed description. The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. Wherein, the arrangement of each element in the embodiment is for illustration, not for limiting the present invention. In addition, the partial repetition of the symbols in the figures in the embodiments is for the purpose of simplifying the description, and does not imply the relationship between different embodiments.

Fig. 1 is a schematic diagram of the operating system of the present invention. As shown in the figure, the operating system 100 includes an image capture device 110 , a control circuit 120 and a display device 130 . The image capture device 110 senses external light according to a working frequency MCLK, and generates image data DT _I according to the sensing result. In a possible embodiment, the image capture device 110 converts the operating frequency MCLK to generate a pixel frequency PCLK, and outputs the image data DT _I according to the pixel frequency PCLK. In this embodiment, the image capture device 110 outputs the image data DT _I in a serial communication (serial communication), but this is not intended to limit the present invention. In other embodiments, the image capture device 110 outputs the image data DT _I in a parallel communication manner. In addition, the present invention does not limit the circuit structure of the image capture device 110 . In a possible embodiment, the image capture device 110 includes a charge coupled device (CCD) or a complementary metal-oxide semiconductor (CMOS) sensor.

The control circuit 120 is coupled between the image capture device 110 and the display device 130 to receive and store the image data DT _I . In this embodiment, when the amount of image data DT _I stored by the control circuit 120 reaches a target value, the control circuit 120 generates display data DT _D to the display device 130 according to the image data DT _I stored by itself. In a possible embodiment, the control circuit 120 directly outputs the image data DT _I to the display device 130 as the display data DT _D. In this example, whenever the control circuit 120 outputs a display data DT _D , the control circuit 120 deletes the corresponding image data DT _I . For convenience of description, the following content assumes that the control circuit 120 directly uses the image data DT _I as the display data DT _D , but this is not intended to limit the present invention. In other embodiments, the control circuit 120 processes (eg converts) the image data DT _I to generate the display data DT _D .

While the control circuit 120 is outputting the display data DT _D , the control circuit 120 continues to receive and store the image data DT _I . When the amount of the image data DT _I stored by the control circuit 120 is greater than a first critical value, the control circuit 120 reduces the operating frequency MCLK to slow down the output speed of the image data DT _I by the image capture device 110 . However, when the amount of the image data DT _I stored by the control circuit 120 is less than a second critical value, the control circuit 120 increases the operating frequency MCLK to increase the output speed of the image data DT _I by the image capture device 110 . In this embodiment, the control circuit 120 outputs the display data DT _D in a serial manner, but this is not intended to limit the present invention. In other embodiments, the control circuit 120 outputs the display data DT _D in a parallel manner. The present invention does not limit the architecture of the control circuit 120 . In a possible embodiment, the control circuit 120 is a micro control unit (MCU).

In other embodiments, the control circuit 120 receives the image data DT _I according to the pixel frequency PCLK. The present invention does not limit the relationship between the working frequency MCLK and the pixel frequency PCLK. In a possible embodiment, when the control circuit 120 reduces the operating frequency MCLK, the pixel frequency PCLK also decreases accordingly. Therefore, the speed at which the control circuit 120 receives the image data _DT1 becomes slower. In this example, when the control circuit 120 increases the operating frequency MCLK, the pixel frequency PCLK also increases accordingly. Therefore, the speed at which the control circuit 120 receives the image data _DT1 becomes faster.

The present invention does not limit how the control circuit 120 determines whether the quantity of the image data _DT1 stored by itself reaches a target value. In a possible embodiment, whenever the image capture device 110 outputs an image data DT _I , the image capture device 110 enables a horizontal synchronization signal Hsync. Therefore, the control circuit 120 can know whether the quantity of the image data DT _I reaches a target value according to the number of times the horizontal synchronization signal Hsync is enabled. In another possible embodiment, the control circuit 120 knows whether the quantity of the image data DT _I reaches a target value according to the quantity of memory blocks filled with the image data DT _I.

The present invention does not limit the format of the image data _DTI . In a possible embodiment, each image data DT _I is a series of image data. In this example, when the control circuit 120 outputs a display data DT _D according to an image data DT _I , a row of pixels of the display device 130 presents an image according to the display data DT _D. The present invention does not limit the speed at which the control circuit 120 receives the image data DT _I and the speed at which the display data DT _D is output. The speed at which the control circuit 120 receives the image data DT _I may be the same as or different from the speed at which the display data DT _D is output.

In a possible embodiment, whenever the control circuit 120 receives an image data DT _I , the control circuit 120 increases a count value. Whenever the control circuit 120 outputs a display data DT _D , the control circuit 120 decreases the count value. In this example, the count value represents the number of image data DT _I stored by the control circuit 120 . In other embodiments, the control circuit 120 reads the count value at regular intervals, and adjusts the operating frequency MCLK according to the count value.

When the count value is greater than a high threshold value (or called the first threshold value), it indicates that the amount of image data DT _I stored in the control circuit 120 is too large. Therefore, the control circuit 120 lowers the operating frequency MCLK to slow down the speed at which the image capture device 110 outputs the image data DT _I. However, when the count value is less than a low threshold value (or called the second threshold value), it means that the amount of image data _DT1 stored in the control circuit 120 is too small. Therefore, the control circuit 120 increases the operating frequency MCLK to speed up the output speed of the image data DT _I by the image capture device 110 .

In other embodiments, the image capture device 110 enables a vertical synchronization signal Vsync whenever the quantity of the image data DT _I output by the image capture device 110 reaches a preset value. For example, after the image capture device 110 outputs 240 pieces of image data DT _I , the image capture device 110 enables the vertical synchronization signal Vsync. In this example, whenever the image capture device 110 outputs a piece of image data DT _I , the image capture device 110 enables the horizontal synchronization signal Hsync.

In some embodiments, the control circuit 120 communicates with the image capture device 110 through an IC bus (Inter-Integrated Circuit; I ² C) 125 . In this example, the control circuit 120 may set the image capture device 110 to output color or black image data through the integrated circuit bus 125 according to its pre-stored setting values, or set the image capture device 110 to output color or black image data per second. The number of frames, such as 60, 30 or 1 frame. In a possible embodiment, each frame is composed of a plurality of (eg 240) image data DT _I. In some embodiments, the control circuit 120 sets the resolution of the image data DT _I through the IC bus 125 . For example, the control circuit 120 may require the image capture device 110 to output image data with a resolution of 320×240 or 640×480 to match the resolution of the display device 130 .

The display device 130 presents images according to the display data DT _D. In a possible embodiment, the display device 130 has an i80 interface (not shown) or a serial peripheral interface for receiving the display data DT _D . The present invention does not limit the type of the display device 130 . In a possible embodiment, the display device 130 is a non-self-luminous display, such as a liquid crystal display (LCD display). In other embodiments, the display device 130 is a self-luminous display (self-luminous display), such as an organic light emitting diode display (Organic Light Emitting Diode Display; OLED display).

Figure 2 is a possible schematic diagram of the control circuit of the present invention. As shown in the figure, the control circuit 120 includes transmission interfaces 210 , 230 , a processing circuit 220 and a storage circuit 240 . The transmission interface 210 is coupled to the image capture device 110 for transmitting image data DT _I , operating frequency MCLK, vertical synchronization signal Vsync, horizontal synchronization signal Hsync and pixel frequency PCLK. In addition, the transmission interface 210 has an integrated circuit bus bar 125 .

The processing circuit 220 receives the image data DT _I through the transmission interface 210 and writes the image data DT _I into the storage circuit 240 . In this embodiment, when the amount of image data DT _I stored in the storage circuit 240 reaches a target value, the processing circuit 220 starts to read and output the image data stored in the storage circuit 240 in sequence.

The transmission interface 230 transmits the display data DT _D to the display device 130 . In this embodiment, the transmission interface 230 receives the display data DT _D in a serial manner, and outputs the display data DT _D to the display device 130 in a serial manner, but this is not intended to limit the present invention. In other embodiments, the transmission interface 230 may receive the display data DT _D generated by the processing circuit 220 in parallel.

The storage circuit 240 is coupled to the processing circuit 220 for storing the image data DT _I . In this embodiment, the storage circuit 240 indirectly receives the image data DT _I through the processing circuit 220 , but this is not intended to limit the present invention. In other embodiments, the storage circuit 240 is directly coupled to the transmission interface 210 for directly receiving the image data DT _I . The invention does not limit the type of the storage circuit 240 . In a possible embodiment, the storage circuit 240 is a static random access memory (SRAM).

FIG. 3 is a schematic diagram of the storage circuit 240 . As shown in the figure, the storage circuit 240 has blocks BK0˜BK11 for storing a plurality of image data DT _I . In other embodiments, the storage circuit 240 has other blocks for storing other information. In this embodiment, each of the blocks BK0-BK11 is used to store a piece of image data. In this example, the image data stored in each of the blocks BK0˜BK11 is data required by a row of pixels of the display device 130 . In other embodiments, the image data stored in each block can be used by multiple rows of pixels, or the image data stored in multiple blocks can be used by a single row of pixels.

In this embodiment, it is assumed that the storage circuit 240 stores nine pieces of image data DT _I , and each piece of image data DT _I can fill up one block. Therefore, the blocks BK0-BK8 are in a full state, while the blocks BK9-BK11 are in an unfilled state. Since the blocks BK0~BK8 are full, the index IND points to the block BK8. In this example, when the index IND points to the block BK5, it means that the quantity of the image data DT _I has reached the target value DATCAP/2. Therefore, the processing circuit 220 starts to read and output the image data DT _I stored in the storage circuit 240 .

For example, the processing circuit 220 may read the image data stored in the block BK0 first, and output the image data stored in the block BK0 to the display device 130 as the first display data DT _D. The first column of pixels in the display device 130 presents an image according to the first display data DT _D. At this time, the indicator value IND may move down. However, since the processing circuit 220 continues to write the image data _DT1 to the storage circuit 240, the index value IND may gradually move up to the block BK8.

When the index value IND points to the block BK8, it means that the quantity of the image data DT _I stored in the storage circuit 240 has reached the high threshold value DATHTH. Therefore, the processing circuit 220 lowers the operating frequency MCLK to instruct the image capture device 110 to slow down the speed of outputting the image data DT _I. However, when the index value IND points to the block BK1, it means that the quantity of the image data DT _I stored in the storage circuit 240 is lower than the low threshold value DATLTH. Therefore, the processing circuit 220 increases the operating frequency MCLK to instruct the image capture device 110 to increase the output speed of the image data DT _I. When the index IND is between the high threshold DATHTH and the low threshold DATLTH, the processing circuit 220 does not adjust the working frequency MCLK. In a possible embodiment, the target value DATCAP/2 is half of the memory space DATCAP of the storage circuit 240 for storing row image data.

Since the processing circuit 220 starts to read the image data stored in the storage circuit 240 after the amount of image data in the storage circuit 240 reaches a target value, in order to provide display data DT _D to the display device 130, the memory of the storage circuit 240 The space does not need to be too large. Moreover, since the processing circuit 220 dynamically adjusts the operating frequency MCLK, the number of rows of image data stored in the storage circuit 240 can be properly controlled without losing the image data DT _I .

In some embodiments, when the processing circuit 220 detects that an abnormal situation occurs, the processing circuit 220 executes a specific action. For example, when the index IND is greater than a boundary value DATFULLF (such as the third threshold value), it means that the image capture device 110 outputs the image data DT _I too fast, and the storage circuit 240 has no time to store the image data DT _I . Therefore, the processing circuit 220 may suspend providing the display data DT _D to the display device 130 after outputting the column image data stored in BK0-BK11 until the vertical synchronization signal Vsync is enabled. In this example, since the processing circuit 220 suspends refreshing the frame of the display device 130 , some columns of pixels of the display device 130 may present a previous frame. However, after the vertical synchronous signal Vsync is enabled, the processing circuit 220 starts to output the display data DT _D to the display device 130 , so the user is not easy to observe that the display device 130 presents an incorrect picture. In other embodiments, when the storage circuit 240 has no time to store the image data DT _I , the processing circuit 220 may output specific display data to the display device 130 to make certain rows of pixels of the display device 130 present black images.

Similarly, when the index IND is lower than another boundary value DATEPTF (such as the fourth critical value), it means _that the output speed of the image capture device 110 is too slow, and the storage circuit 240 has not stored the complete image data DT _I . Therefore, the processing circuit 220 cannot provide correct display data DT _D to the display device 130 . At this time, the processing circuit 220 may suspend capturing the blocks BK0 - BK11 and suspend refreshing the frame of the display device 130 . In this example, the display device 130 may present the previous frame. In other embodiments, the processing circuit 220 may provide a preset image to the display device 130 for temporarily displaying a black screen on the display device 130 . At this time, the processing circuit 220 may increase the operating frequency MCLK to increase the speed at which the image capture device 110 outputs the image data DT _I. Since the amount of the image data DT _I reaches the target value DATCAP/2 very quickly, the processing circuit 220 can immediately generate the display data DT _D for the display device 130 . Due to the effect of persistence of vision and the processing circuit 220 provides the display data DT _D in real time, it is difficult for the user to observe incorrect images presented by the display device 130 .

Please refer to FIG. 2 , the control circuit 120 includes a counting circuit 250 . The counting circuit 250 has a counting value VA. The count value VA corresponds to the index IND in FIG. 3 . In this example, the processing circuit 220 adjusts the count value VA according to the quantity of the image data DT _I stored in the storage circuit 240, and adjusts the operating frequency MCLK according to the count value VA. In another possible embodiment, the count value VA is related to the number of times the horizontal synchronization signal Hsync is enabled. In this example, the processing circuit 220 increases the count value VA every time the image capture device 110 enables the horizontal synchronization signal Hsync. Whenever the processing circuit 220 generates a display data DT _D , the processing circuit 220 decreases the count value VA.

The present invention does not limit when the processing circuit 220 adjusts the working frequency MCLK. In a possible embodiment, whenever the horizontal synchronization signal Hsync is enabled, the processing circuit 220 adjusts the operating frequency MCLK according to the count value VA. In other embodiments, when the number of times the horizontal synchronization signal Hsync is enabled reaches a preset value, the processing circuit 220 reads the count value VA.

FIG. 4 is a schematic flow chart of a possible flow of the control method of the present invention. The control method 400 of the present invention is applicable to a control circuit (such as the control circuit 200 in FIG. 2 ) for adjusting the speed at which an image capture device outputs image data. In this example, the control circuit does not need a large-capacity memory to store image data. Therefore, the usable space of the control circuit can be increased, and the cost of components can be reduced, because the larger the capacity, the more expensive the memory.

First, perform an initialization setting (step S411). In a possible embodiment, step S411 is to initialize a plurality of flags inside the control circuit. These flags are used to provide different default values, such as DATFULLF, DATHTH, DATCAP/2, DATLTH and DATEPTF in Figure 3. In addition, the control circuit may set an external image capture device according to the flags. In a possible embodiment, the number of these flags may be programmed in the control circuit in advance, so step S411 may be omitted.

Receive and store multiple image data (step S412). In a possible embodiment, the image data is provided by an image capture device (such as 110 shown in FIG. 1 ). The image capture device may include a CCD or a CMOS sensor. In some embodiments, each piece of image data is a row of image data for use by a row of pixels of the display device. In a possible embodiment, step S412 is to store the image data in a storage circuit. The storage circuit may be a volatile memory.

It is judged whether the quantity of the stored image data reaches a target value (step S413). In a possible embodiment, the target value is the value of a flag initialized in step S411, such as the target value DATCAP/2 in FIG. 3 . The present invention does not limit how the step S413 determines whether the quantity of the stored image data reaches a target value. In a possible embodiment, each time the image capture device enables a horizontal synchronization signal, a count value is gradually increased. Therefore, according to the count value, it can be known whether the quantity of the stored image data reaches a target value. In other embodiments, step S413 is to determine whether the number of stored image data reaches a target value according to the number of memory blocks filled with image data.

When the number of stored image data does not reach the target value, return to step S412 to continue receiving and storing image data. When the quantity of the stored image data reaches the target value, output a display data to a display device (step S414). In a possible embodiment, step S414 is to output the image data stored in the storage circuit to the display device as display data. In this example, each time a display data is output in step S414, the count value will be decreased. However, as long as one image data is stored at the same time, the above count value will be increased.

According to the quantity of the stored image data, the speed of outputting the image data by the image capture device is adjusted (step S415). In a possible embodiment, step S415 is only triggered when the image capture device enables a horizontal synchronization signal. For example, after step S414, if the horizontal synchronization signal is not triggered, then step S415 is not performed. In other embodiments, step S415 is performed only when the number of times the horizontal synchronization signal is enabled reaches a preset value.

In this embodiment, step S415 includes steps S416-S419. Firstly, it is determined whether the quantity of the stored image data is greater than a first threshold (step S416). If the amount of the stored image data is greater than the first threshold, slow down the output speed of the image capture device (step S417). In a possible embodiment, step S417 is to reduce the operating frequency of the image capture device. In this example, the image capture device reduces the frequency of one pixel according to the reduced operating frequency. However, return to step S414 to continue reading and converting the stored image data.

If the quantity of the stored image data is not greater than the first threshold, it is determined whether the quantity of the stored image data is less than a second threshold (step S418 ). In this embodiment, the second critical value is smaller than the first critical value. When the quantity of the stored image data is less than the second threshold value, the speed of outputting the image data by the image capture device is increased (step S419 ). In a possible embodiment, step S419 is to speed up the working frequency of the image capture device. In this example, the image capture device may increase the pixel frequency according to the accelerated operating frequency. However, return to step S414 to continue reading and converting the stored image data.

In this embodiment, after starting to receive image data (step S412 ), continue to receive image data. Therefore, the amount of image data stored by the storage circuit can be maintained within a preset range.

Fig. 5 is another schematic flowchart of the control method of the present invention. FIG. 5 is similar to FIG. 4, except that the control method 500 in FIG. 5 has more steps S520 and S521. Since the steps S511-S519 are similar to the steps S411-S419, they are not repeated here. In this example. Step S520 is to determine whether an abnormal situation occurs. When an abnormal situation occurs, perform a specific action (step S521), and then return to step S512 to continue receiving and storing image data. When no abnormal situation occurs, step S515 is executed.

In a possible embodiment, the abnormal condition is that the amount of data stored in the storage circuit is greater than a third critical value or less than a fourth critical value, wherein the third critical value is greater than the first critical value, and the fourth critical value less than the second critical value. For example, when the amount of image data stored in the storage circuit is greater than the third critical value, it means that the output speed of the image capture device is too fast for the storage circuit to store the image data. In other embodiments, when the amount of image data stored in the storage circuit is less than the fourth critical value, it means that the output speed of the image capture device is too slow, and the image data in the storage circuit is not enough to drive the display device.

When the above abnormal situation occurs, perform a specific action, such as outputting a preset data to the display device. In this example, the pixels of the display device may display a black frame (corresponding to default data). Due to the image persistence of vision, the user will not perceive the black screen. In other embodiments, the specific action may suspend refreshing the display device, that is, not outputting any signal to the display device. Therefore, the display device presents the previous picture. Since the control circuit of the present invention will properly adjust (speed up or slow down) the speed of outputting image data from the image capture device, it can refresh the display device in real time to avoid data overrun or underrun.

The control method of the present invention, or specific forms or parts thereof, may exist in the form of program codes. The code may be stored on a physical medium, such as a floppy disk, a CD, a hard disk, or any other machine-readable (such as a computer-readable) storage medium, or a computer program product without limitation in an external form, wherein, When the program code is loaded and executed by a machine, such as a computer, the machine becomes a control circuit for participating in the present invention. Code may also be sent via some transmission medium, such as wire or cable, optical fiber, or any type of transmission in which, when the code is received, loaded, and executed by a machine, such as a computer, the machine becomes the one used to participate in this Invented Control Road. When implemented on a general-purpose processing unit, the code combines with the processing unit to provide a unique device that operates similarly to application-specific logic circuits.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be understood by those of ordinary skill in the art to which this invention belongs. In addition, unless expressly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device or method of the embodiments of the present invention can be implemented in physical embodiments of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

100: operating system

110: image capture device

120: control circuit

130: display device

125: Integrated circuit bus

210, 230: transmission interface

220: processing circuit

240: storage circuit

250: counting circuit

400, 500: control method

MCLK: operating frequency

VA: count value

DT _I : Image data

PCLK: pixel frequency

DT _D : display data

Hsync: horizontal synchronization signal

Vsync: vertical synchronization signal

BK0~BK11: block

IND: index

DATCAP/2: target value

DATHTH, DATLTH: Threshold

DATCAP: memory space

DATFULLF, DATEPTF: Boundary value

S411~S419, S511~S521: steps

Fig. 1 is a schematic diagram of the operating system of the present invention. Figure 2 is a possible schematic diagram of the control circuit of the present invention. FIG. 3 is a schematic diagram of a storage circuit. FIG. 4 is a schematic flow chart of a possible flow of the control method of the present invention. FIG. 5 is a schematic diagram of another possible flow chart of the control method of the present invention.

400: control method

S411~S419: steps

Claims (8)

A control circuit, coupled between an image capture device and a display device, the image capture device outputs multiple image data according to an operating frequency, the control circuit includes: a first transmission interface, coupled to the image capture A device for receiving the image data; a storage circuit coupled to the first transmission interface for receiving and storing the image data; a processing circuit for retrieving and processing the image data stored in the storage circuit , used to generate a plurality of display data, and generate the operating frequency according to the amount of data stored in the storage circuit; and a second transmission interface, coupled to the processing circuit, for outputting the display data to the display device; Wherein when the amount of data stored in the storage circuit is greater than a first critical value, the processing circuit reduces the operating frequency to slow down the speed at which the image capture device outputs the image data, when the data stored in the storage circuit When the amount of data is less than a second critical value, the processing circuit increases the operating frequency to speed up the output speed of the image capture device for outputting the image data, and the first critical value is greater than the second critical value. The control circuit described in item 1 of the scope of the patent application, wherein the image capture device converts the operating frequency to generate a pixel frequency, and provides the pixel frequency to the processing circuit, and the processing circuit according to the pixel The frequency receives the image data, and writes the image data into the storage circuit. The control circuit described in item 2 of the scope of patent application, wherein when the processing circuit reduces the operating frequency, the image capture device reduces the pixel frequency, and when the processing circuit increases the operating frequency, the image capture device Increase the pixel frequency. The control circuit described in item 1 of the scope of the patent application, wherein when the amount of data stored in the storage circuit is greater than a third critical value or less than a fourth critical value, the processing circuit suspends the retrieval of the data stored in the storage circuit For the stored image data, the third critical value is greater than the first critical value, and the fourth critical value is smaller than the second critical value. The control circuit described in item 4 of the scope of the patent application, wherein when the amount of data stored in the storage circuit is greater than the third critical value or smaller than the fourth critical value, the processing circuit outputs through the second transmission interface A default data is given to the display device. The control circuit described in item 1 of the scope of the patent application further includes: a counting circuit with a count value, wherein the processing circuit adjusts the count value according to the amount of data stored in the storage circuit, and adjusts the count value according to the count value The operating frequency. A control method, which is applicable to a control circuit, and includes receiving multiple image data, wherein the image data is provided by an image capture device; storing the image data in a storage circuit; capturing and processing the storage circuit The stored image data is used to generate multiple display data; output the display data to a display device; and adjust an operating frequency of the image capture device according to the amount of data stored in the storage circuit; The amount of data stored in the storage circuit, the step of adjusting the operating frequency of the image capture device includes: judging whether the amount of data stored in the storage circuit is greater than a first critical value; when the data stored in the storage circuit When the quantity is greater than the first critical value, reduce the operating frequency; judging whether the quantity of data stored in the storage circuit is less than a second critical value; when the quantity of data stored in the storage circuit is less than the second critical value, increasing the operating frequency; wherein the first critical value is greater than the second critical value Two critical values. The control method described in item 7 of the scope of the patent application further includes: receiving a pixel frequency; and receiving the image data according to the pixel frequency; wherein when the working frequency is reduced, the pixel frequency is a first A value, when the working frequency is increased, the pixel frequency is a second value, the first value is smaller than the second value.

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