CN112929512B - Control circuit and control method thereof - Google Patents

Abstract

The invention provides a control circuit and a control method thereof, wherein the control circuit is coupled between an image acquisition device and a display device. The image acquisition device outputs a plurality of image data according to an operating frequency. The control circuit comprises a first transmission interface, a storage circuit, a processing circuit and a second transmission interface. The first transmission interface is coupled to the image acquisition device for receiving the image data. The storage circuit is coupled to the first transmission interface for receiving and storing the image data. The processing circuit acquires the image data stored in the storage circuit, is used for generating a plurality of display data, and generates the working frequency according to the quantity of the data stored in the storage circuit. The second transmission interface is coupled to the processing circuit and used for outputting display data to the display device.

Description

Control circuit and control method thereof

Technical Field

The invention relates to a control circuit, and more particularly to a control circuit coupled between an image acquisition device and a display device.

Background technique

In the current image processing process, microprocessor units (MPUs) are usually used. However, today, microcontroller units (MCUs) are becoming more and more powerful and can gradually perform image processing. However, the internal storage space of microcontroller units is limited and cannot store large amounts of image data.

Summary of the invention

The present invention provides a control circuit coupled between an image acquisition device and a display device. The image acquisition device outputs a plurality of image data according to an operating frequency. The control circuit includes a first transmission interface, a storage circuit, a processing circuit, and a second transmission interface. The first transmission interface is coupled to the image acquisition device to receive image data. The storage circuit is coupled to the first transmission interface to receive and store image data. The processing circuit acquires the image data stored in the storage circuit to generate a plurality of display data, and generates an operating frequency according to the amount of data stored in the storage circuit. The second transmission interface is coupled to the processing circuit to output the display data to the display device.

The present invention further provides a control method, which is applicable to a control circuit and includes receiving a plurality of image data, wherein the plurality of image data are provided by an image acquisition device; storing the plurality of image data in a storage circuit; acquiring the plurality of image data stored in the storage circuit to generate a plurality of display data; outputting the plurality of display data to a display device; and adjusting an operating frequency of the image acquisition device according to the amount of data stored in the storage circuit.

The control method of the present invention can be implemented through the control circuit of the present invention, which is hardware or firmware that can perform specific functions, or can be recorded in a recording medium in the form of program code and implemented in combination with specific hardware. When the program code is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes a control circuit or operating system for implementing the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an operating system of the present invention.

FIG. 2 is a possible schematic diagram of a control circuit of the present invention.

FIG. 3 is a schematic diagram of a storage circuit.

FIG. 4 is a schematic diagram of a possible flow chart of the control method of the present invention.

FIG. 5 is another possible flow chart of the control method of the present invention.

Reference numerals:

100: operating system; 110: image acquisition device;

120: control circuit; 130: display device;

125: integrated circuit bus; 210, 230: transmission interface;

220: processing circuit; 240: storage circuit;

250: counting circuit; 400, 500: control method;

MCLK: operating frequency; VA: count value;

DTI: image data; PCLK: pixel frequency;

DTD: display data; Hsync: horizontal synchronization signal;

Vsync: vertical synchronization signal; BK0~BK11: block;

IND: indicator; DATCAP/2: target value;

DATHTH, DATLTH: critical value;

DATCAP: Memory Space

DATFULLF, DATEPTF: boundary value;

S411~S419, S511~S521: steps.

Detailed ways

In order to make the purpose, features and advantages of the present invention more clearly understood, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each element in the embodiment is for illustrative purposes and is not intended to limit the present invention. In addition, some repetitions of the figure numbers in the embodiments are for the purpose of simplifying the description and do not mean the relevance between different embodiments.

FIG. 1 is a schematic diagram of an operating system of the present invention. As shown in the figure, the operating system 100 includes an image acquisition device 110, a control circuit 120, and a display device 130. The image acquisition device 110 senses external light according to an operating frequency MCLK, and generates image data DT _I according to the sensing result. In a possible embodiment, the image acquisition device 110 converts the operating frequency MCLK to generate a pixel frequency PCLK, and outputs the image data DT _I according to the pixel frequency PCLK. In this embodiment, the image acquisition device 110 outputs the image data DT _I in a serial communication manner, but it is not intended to limit the present invention. In other embodiments, the image acquisition device 110 outputs the image data DT _I in a parallel communication manner. In addition, the present invention does not limit the circuit architecture of the image acquisition device 110. In a possible embodiment, the image acquisition device 110 includes a charge coupled device (CCD) or a complementary metal-oxide semiconductor (CMOS) sensor element.

The control circuit 120 is coupled between the image acquisition device 110 and the display device 130, and receives and stores the image data DT _I. In this embodiment, when the amount of the image data DT _I stored in the control circuit 120 reaches a target value, the control circuit 120 generates display data DT _D for the display device 130 according to the image data DT _I stored in the control circuit 120. In a possible embodiment, the control circuit 120 directly outputs the image data DT _I as the display data DT _D to the display device 130. In this example, each time the control circuit 120 outputs a display data DT _D , the control circuit 120 deletes the corresponding image data DT _I. For the convenience of explanation, the following content assumes that the control circuit 120 directly uses the image data DT _I as the display data DT _D , but it is not intended to limit the present invention. In other embodiments, the control circuit 120 processes (e.g., converts) the image data DT _I to generate the display data DT _D.

While the control circuit 120 outputs the display data _DTD , the control circuit 120 continues to receive and store the image data _DTI . When the amount of the image data _DTI stored in the control circuit 120 is greater than a first critical value, the control circuit 120 reduces the operating frequency MCLK to slow down the speed at which the image acquisition device 110 outputs the image data _DTI . However, when the amount of the image data _DTI stored in the control circuit 120 is less than a second critical value, the control circuit 120 increases the operating frequency MCLK to speed up the speed at which the image acquisition device 110 outputs the image data _DTI . In this embodiment, the control circuit 120 outputs the display data _DTD in a serial manner, but this is not intended to limit the present invention. In other embodiments, the control circuit 120 outputs the display data _DTD in a parallel manner. The present invention does not limit the architecture of the control circuit 120. In one possible embodiment, the control circuit 120 is a micro control unit (MCU).

In other embodiments, the control circuit 120 receives the image data _DTI according to the pixel frequency PCLK. The present invention does not limit the relationship between the operating frequency MCLK and the pixel frequency PCLK. In one possible embodiment, when the control circuit 120 reduces the operating frequency MCLK, the pixel frequency PCLK also decreases. Therefore, the speed at which the control circuit 120 receives the image data _DTI becomes slower. In this example, when the control circuit 120 increases the operating frequency MCLK, the pixel frequency PCLK also increases. Therefore, the speed at which the control circuit 120 receives the image data _DTI becomes faster.

The present invention does not limit how the control circuit 120 determines whether the amount of the image data _DTI stored in the control circuit 120 reaches a target value. In one possible embodiment, each time the image acquisition device 110 outputs an image data _DTI , the image acquisition device 110 enables a horizontal synchronization signal Hsync. Therefore, the control circuit 120 can determine whether the amount of the image data _DTI reaches a target value based on the number of times the horizontal synchronization signal Hsync is enabled. In another possible embodiment, the control circuit 120 determines whether the amount of the image data _DTI reaches a target value based on the number of memory blocks filled with the image data _DTI .

The present invention does not limit the format of the image data _DTI . In one possible embodiment, each image data _DTI is a row of image data. In this example, when the control circuit 120 outputs a display data _DTD according to an image data _DTI , a row of pixels of the display device 130 presents a picture according to the display data _DTD . The present invention does not limit the speed at which the control circuit 120 receives the image data _DTI and the speed at which the display data _DTD is output. The speed at which the control circuit 120 receives the image data _DTI may be the same as or different from the speed at which the display data _DTD is output.

In one possible embodiment, each time the control circuit 120 receives a piece of image data _DTI , the control circuit 120 increases a count value. Each time the control circuit 120 outputs a piece of display data _DTD , the control circuit 120 decreases the count value. In this example, the count value indicates the number of image data _DTI stored by the control circuit 120. In other embodiments, the control circuit 120 reads the count value at a fixed time interval and adjusts the operating frequency MCLK according to the count value.

When the count value is greater than a high threshold value (or the first threshold value), it indicates that the amount of image data _DTI stored in the control circuit 120 is too large. Therefore, the control circuit 120 reduces the operating frequency MCLK to slow down the speed at which the image acquisition device 110 outputs the image data _DTI . However, when the count value is less than a low threshold value (or the second threshold value), it indicates that the amount of image data _DTI stored in the control circuit 120 is too small. Therefore, the control circuit 120 increases the operating frequency MCLK to speed up the speed at which the image acquisition device 110 outputs the image data _DTI .

In other embodiments, whenever the number of image data _DTI outputted by the image acquisition device 110 reaches a preset value, the image acquisition device 110 enables a vertical synchronization signal Vsync. For example, when the image acquisition device 110 outputs 240 sets of image data _DTI , the image acquisition device 110 enables the vertical synchronization signal Vsync. In this example, whenever the image acquisition device 110 outputs a set of image data _DTI , the image acquisition device 110 enables the horizontal synchronization signal Hsync.

In some embodiments, the control circuit 120 communicates with the image acquisition device 110 through an Inter-Integrated Circuit (I ² C) 125. In this example, the control circuit 120 may set the image acquisition device 110 to output color or black image data according to the setting value stored in advance, or set the number of frames output by the image acquisition device 110 per second, such as 60 frames, 30 frames, or 1 frame. In a possible embodiment, each frame is composed of a plurality of (such as 240) pieces of image data _DTI . In some embodiments, the control circuit 120 sets the resolution of the image data _DTI through the integrated circuit bus 125. For example, the control circuit 120 may require the image acquisition device 110 to output image data with a resolution of 320X240 or 640X480 to meet the resolution of the display device 130.

The display device 130 presents a picture according to the display data _DTD . In one possible embodiment, the display device 130 has an i80 interface (not shown) or a serial peripheral interface for receiving the display data _DTD . The present invention does not limit the type of the display device 130. In one possible embodiment, the display device 130 is a non-self-luminous display, such as a liquid crystal display (LCD display). In other embodiments, the display device 130 is a self-luminous display, such as an organic light emitting diode display (OLED display).

FIG2 is a possible schematic diagram of the control circuit of the present invention. As shown in the figure, the control circuit 120 includes transmission interfaces 210, 230, a processing circuit 220 and a storage circuit 240. The transmission interface 210 is coupled to the image acquisition device 110 to transmit image data _DT1 , operating frequency MCLK, vertical synchronization signal Vsync, horizontal synchronization signal Hsync and pixel frequency PCLK. In addition, the transmission interface 210 has an integrated circuit bus 125.

The processing circuit 220 receives the image data _DT1 through the transmission interface 210 and writes the image data _DT1 into the storage circuit 240. In this embodiment, when the amount of the image data _DT1 stored in the storage circuit 240 reaches a target value, the processing circuit 220 starts to read and output the image data stored in the storage circuit 240 in sequence.

The transmission interface 230 transmits the display data DT _D to the display device 130. In this embodiment, the transmission interface 230 receives the display data DT _D in serial and outputs the display data DT _D to the display device 130 in serial, but this is not intended to limit the present invention. In other embodiments, the transmission interface 230 may receive the display data DT _D generated by the processing circuit 220 in parallel.

The storage circuit 240 is coupled to the processing circuit 220 to store the image data _DT1 . In the present embodiment, the storage circuit 240 indirectly receives the image data _DT1 through the processing circuit 220, but this is not intended to limit the present invention. In other embodiments, the storage circuit 240 is directly coupled to the transmission interface 210 to directly receive the image data _DT1 . The present invention does not limit the type of the storage circuit 240. In one possible embodiment, the storage circuit 240 is a static random access memory (SRAM).

FIG. 3 is a schematic diagram of the storage circuit 240. As shown in the figure, the storage circuit 240 has blocks BK0-BK11 for storing a plurality of image data _DT1 . In other embodiments, the storage circuit 240 has other blocks for storing other information. In this embodiment, each of the blocks BK0-BK11 is used to store a piece of image data. In this example, the image data stored in each of the blocks BK0-BK11 is data required for a column of pixels of the display device 130. In other embodiments, the image data stored in each block can be used for a plurality of columns of pixels, or the image data stored in a plurality of blocks can be used for a single column of pixels.

In this embodiment, it is assumed that the storage circuit 240 stores nine pieces of image data DT _I , and each piece of image data DT _I can fill up a block. Therefore, blocks BK0-BK8 are filled, and blocks BK9-BK11 are not filled. Since blocks BK0-BK8 are filled, the pointer IND points to block BK8. In this example, when the pointer IND points to block BK5, it means that the amount of image data DT _I has reached the target value DATCAP/2. Therefore, the processing circuit 220 starts to read and output the image data DT _I stored in the storage circuit 240.

For example, the processing circuit 220 may first read the image data stored in the block BK0, and output the image data stored in the block BK0 as the first display data DT _D to the display device 130. The first row of pixels in the display device 130 presents a picture according to the first display data DT _D. At this time, the indicator value IND may move downward. However, since the processing circuit 220 continues to write the image data DT _I to the storage circuit 240, the indicator value IND may gradually move upward to the block BK8.

When the indicator value IND points to the block BK8, it means that the amount of image data _DTI stored in the storage circuit 240 has reached the high threshold value DATHTH. Therefore, the processing circuit 220 reduces the operating frequency MCLK to instruct the image acquisition device 110 to slow down the speed of outputting the image data _DTI . However, when the indicator value IND points to the block BK1, it means that the amount of image data _DTI stored in the storage circuit 240 has been lower than the low threshold value DATLTH. Therefore, the processing circuit 220 increases the operating frequency MCLK to instruct the image acquisition device 110 to increase the speed of outputting the image data _DTI . When the indicator IND is between the high threshold value DATHTH and the low threshold value DATLTH, the processing circuit 220 does not adjust the operating frequency MCLK. In one possible embodiment, the target value DATCAP/2 is half of the memory space DATCAP used by the storage circuit 240 to store the column image data.

Since the processing circuit 220 starts to read the image data stored in the storage circuit 240 after the amount of image data in the storage circuit 240 reaches a target value to provide the display data DT _D to the display device 130, the memory space of the storage circuit 240 does not need to be too large. Furthermore, since the processing circuit 220 dynamically adjusts the operating frequency MCLK, the amount of row image data stored in the storage circuit 240 can be appropriately controlled without losing the image data DT _I .

In some embodiments, when the processing circuit 220 detects an abnormal situation, the processing circuit 220 performs a specific action. For example, when the indicator IND is greater than a boundary value DATFULLF (such as a third critical value), it means that the image acquisition device 110 outputs the image data _DTI too fast, and the storage circuit 240 has no time to store the image data _DTI . Therefore, the processing circuit 220 may stop providing the display data _DTD to the display device 130 after outputting the row image data stored in BK0-BK11 until the vertical synchronization signal Vsync is enabled. In this example, since the processing circuit 220 stops refreshing the screen of the display device 130, some rows of pixels of the display device 130 may display the previous screen. However, after the vertical synchronization signal Vsync is enabled, the processing circuit 220 starts to output the display data _DTD to the display device 130, so it is not easy for the user to observe that the display device 130 displays an incorrect screen. In other embodiments, when the storage circuit 240 is unable to store the image data _DTI in time, the processing circuit 220 may output specific display data to the display device 130 so as to make certain columns of pixels of the display device 130 present a black image.

Similarly, when the indicator IND is lower than another boundary value DATEPTF (such as the fourth critical value), it means that the speed of the image acquisition device 110 outputting the image data DT _I is too slow, and the storage circuit 240 does not store the complete image data DT _I. Therefore, the processing circuit 220 cannot provide the correct display data DT _D to the display device 130. At this time, the processing circuit 220 may suspend the acquisition of the blocks BK0-BK11 and suspend the refreshing of the screen of the display device 130. In this example, the display device 130 may present the previous screen. In other embodiments, the processing circuit 220 may provide a preset image to the display device 130 so that the display device 130 temporarily presents a black screen. At this time, the processing circuit 220 may increase the operating frequency MCLK to speed up the speed of the image acquisition device 110 outputting the image data DT _I. Since the amount of the image data DT _I quickly reaches the target value DATCAP/2, the processing circuit 220 can immediately generate the display data DT _D to the display device 130. Due to the effect of persistence of vision and the fact that the processing circuit 220 provides the display data DT _D in real time, the user is unlikely to notice that the display device 130 presents an incorrect image.

Referring to FIG. 2 , the control circuit 120 includes a counting circuit 250. The counting circuit 250 has a counting value VA. The counting value VA is equivalent to the indicator IND in FIG. 3 . In this example, the processing circuit 220 adjusts the counting value VA according to the number of image data _DTI stored in the storage circuit 240, and adjusts the operating frequency MCLK according to the counting value VA. In another possible embodiment, the counting value VA is related to the number of times the horizontal synchronization signal Hsync is enabled. In this example, the processing circuit 220 increases the counting value VA every time the image acquisition device 110 enables the horizontal synchronization signal Hsync. Every time the processing circuit 220 generates a display data _DTD , the processing circuit 220 decreases the counting value VA.

The present invention does not limit when the processing circuit 220 adjusts the operating frequency MCLK. In one possible embodiment, whenever the horizontal synchronization signal Hsync is enabled, the processing circuit 220 adjusts the operating frequency MCLK according to the count value VA. In other embodiments, when the number of times the horizontal synchronization signal Hsync is enabled reaches a preset value, the processing circuit 220 reads the count value VA.

FIG. 4 is a possible flow chart of the control method of the present invention. The control method 400 of the present invention is applicable to a control circuit (such as the control circuit 200 of FIG. 2 ) to adjust the speed at which an image acquisition device outputs image data. In this example, the control circuit does not need to be provided with a large-capacity memory to store image data. Therefore, the usable space of the control circuit can be increased and the component cost can be reduced, because the larger the capacity, the more expensive the memory.

First, an initialization setting is performed (step S411). In one possible embodiment, step S411 is to initialize multiple flags inside the control circuit. The multiple flags are used to provide different preset values, such as DATFULLF, DATHTH, DATCAP/2, DATLTH and DATEPTF in FIG. 3. In addition, the control circuit may set an external image acquisition device based on the multiple flags. In one possible embodiment, the number of the multiple flags may be pre-burned in the control circuit, so step S411 can be omitted.

Receive and store a plurality of image data (step S412). In one possible embodiment, the plurality of image data are provided by an image acquisition device (such as 110 shown in FIG. 1). The image acquisition device may include a CCD or CMOS sensor element. In some embodiments, each piece of image data is a column of image data for use by a column of pixels of a display device. In one possible embodiment, step S412 is to store the plurality of image data in a storage circuit. The storage circuit may be a volatile memory.

Determine whether the amount of stored image data reaches a target value (step S413). In one possible embodiment, the target value is the value of a flag initialized by step S411, such as the target value DATCAP/2 in FIG. 3. The present invention does not limit how step S413 determines whether the amount of stored image data reaches a target value. In one possible embodiment, each time the image acquisition device enables a horizontal synchronization signal, a count value gradually increases. Therefore, by using the count value, it can be known whether the amount of stored image data reaches a target value. In other embodiments, step S413 determines whether the amount of stored image data reaches a target value based on the number of memory blocks filled with image data.

When the amount of stored image data does not reach the target value, the process returns to step S412 to continue receiving and storing image data. When the amount of stored image data reaches the target value, a display data is output to a display device (step S414). In one possible embodiment, step S414 is to output the image data stored in the storage circuit as display data to the display device. In this example, each time a display data is output in step S414, the count value is reduced. However, at the same time, as long as one image data is stored, the count value is increased.

According to the amount of stored image data, the speed at which the image acquisition device outputs the image data is adjusted (step S415). In one possible embodiment, step S415 is triggered only when the image acquisition device enables a horizontal synchronization signal. For example, after step S414, if the horizontal synchronization signal is not triggered, step S415 is not performed. In other embodiments, step S415 is performed only when the number of times the horizontal synchronization signal is enabled reaches a preset value.

In this embodiment, step S415 includes steps S416 to S419. First, it is determined whether the amount of stored image data is greater than a first critical value (step S416). If the amount of stored image data is greater than the first critical value, the speed at which the image acquisition device outputs image data is slowed down (step S417). In a possible embodiment, step S417 is to reduce the operating frequency of the image acquisition device. In this example, the image acquisition device reduces a pixel frequency according to the reduced operating frequency. However, it returns to step S414 to continue reading and converting the stored image data.

If the amount of stored image data is not greater than the first critical value, determine whether the amount of stored image data is less than a second critical value (step S418). In this embodiment, the second critical value is less than the first critical value. When the amount of stored image data is less than the second critical value, speed up the image acquisition device to output image data (step S419). In a possible embodiment, step S419 is to speed up the working frequency of the image acquisition device. In this case, the image acquisition device may increase the pixel frequency according to the accelerated working frequency. However, return to step S414 to continue reading and converting the stored image data.

In this embodiment, after starting to receive the image data (step S412), the image data is continuously received. Therefore, the amount of image data stored in the storage circuit can be maintained within a preset range.

FIG. 5 is another flow chart of the control method of the present invention. FIG. 5 is similar to FIG. 4, except that the control method 500 of FIG. 5 has additional steps S520 and 521. Since steps S511 to S519 are similar to steps S411 to S419, they are not described in detail. In this embodiment, step S520 is to determine whether an abnormal situation occurs. When an abnormal situation occurs, a specific action (step S521) is performed, and then the process returns to step S512 to continue receiving and storing image data. When an abnormal situation does not occur, step S515 is performed.

In one possible embodiment, the abnormal situation is that the amount of data stored in the storage circuit is greater than a third critical value or less than a fourth critical value, wherein the third critical value is greater than the first critical value and the fourth critical value is less than the second critical value. For example, when the amount of image data stored in the storage circuit is greater than the third critical value, it means that the image acquisition device outputs the image data too fast and the storage circuit does not have time to store the image data. In other embodiments, when the amount of image data stored in the storage circuit is less than the fourth critical value, it means that the image acquisition device outputs the image data too slowly and the image data in the storage circuit is insufficient to drive the display device.

When the above abnormal situation occurs, a specific action is performed, such as outputting a preset data to the display device. In this example, the pixels of the display device may present a black screen (corresponding to the preset data). Due to the image of visual persistence, the user will not notice the black screen. In other embodiments, the specific action may pause the refresh of the display device, that is, no signal is output to the display device. Therefore, the display device presents the previous screen. Since the control circuit of the present invention will appropriately adjust (speed up or slow down) the speed at which the image acquisition device outputs image data, the display device can be refreshed immediately to avoid data overload (overrun) or underrun (underrun).

The control method of the present invention, or a specific form or part thereof, may exist in the form of program code. The program code may be stored in a physical medium, such as a floppy disk, an optical disk, a hard disk, or any other machine-readable (such as computer-readable) storage medium, or a computer program product that is not limited to an external form, wherein when the program code is loaded and executed by a machine, such as a computer, the machine becomes used to participate in the control circuit of the present invention. The program code may also be transmitted through some transmission medium, such as wires or cables, optical fibers, or any transmission mode, wherein when the program code is received, loaded and executed by a machine, such as a computer, the machine becomes used to participate in the control circuit of the present invention. When implemented on a general-purpose processing unit, the program code combines with the processing unit to provide a unique device that operates similarly to an application-specific logic circuit.

Unless otherwise defined, all words (including technical and scientific words) herein are generally understood by those skilled in the art to which the present invention belongs. In addition, unless otherwise expressly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in the relevant technical field, and should not be interpreted as an ideal state or overly formal tone.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in the form of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

Claims (8)

1. A control circuit, characterized in that it is coupled between an image acquisition device and a display device, the image acquisition device outputs a plurality of image data according to a working frequency, and the control circuit comprises: a first transmission interface, coupled to the image acquisition device, for receiving the plurality of image data; a storage circuit, coupled to the first transmission interface, for receiving and storing the plurality of image data; a processing circuit, which acquires the plurality of image data stored in the storage circuit to generate a plurality of display data, and generates the operating frequency according to the amount of data stored in the storage circuit; and a second transmission interface, coupled to the processing circuit, for outputting the plurality of display data to the display device; When the amount of data stored in the storage circuit is greater than a first critical value, the processing circuit reduces the operating frequency to slow down the speed at which the image acquisition device outputs the image data. When the amount of data stored in the storage circuit is less than a second critical value, the processing circuit increases the operating frequency to speed up the speed at which the image acquisition device outputs the image data. The first critical value is greater than the second critical value. 2. The control circuit as described in claim 1 is characterized in that the image acquisition device converts the operating frequency to generate a pixel frequency and provides the pixel frequency to the processing circuit. The processing circuit receives the multiple image data according to the pixel frequency and writes the multiple image data into the storage circuit. 3. The control circuit as claimed in claim 2, characterized in that when the processing circuit reduces the operating frequency, the image acquisition device reduces the pixel frequency, and when the processing circuit increases the operating frequency, the image acquisition device increases the pixel frequency. 4. The control circuit as described in claim 1 is characterized in that when the amount of data stored in the storage circuit is greater than a third critical value or less than a fourth critical value, the processing circuit suspends obtaining the multiple image data stored in the storage circuit, the third critical value is greater than the first critical value, and the fourth critical value is less than the second critical value. 5. The control circuit of claim 4, wherein when the amount of data stored in the storage circuit is greater than the third critical value or less than the fourth critical value, the processing circuit outputs a preset data to the display device through the second transmission interface. 6. The control circuit according to claim 1, further comprising: A counting circuit has a counting value, wherein the processing circuit adjusts the counting value according to the amount of data stored in the storage circuit, and adjusts the operating frequency according to the counting value. 7. A control method, characterized in that it is applicable to a control circuit and comprises receiving a plurality of image data, wherein the plurality of image data is provided by an image acquisition device; Storing the plurality of image data in a storage circuit; Acquiring the plurality of image data stored in the storage circuit to generate a plurality of display data; Outputting the plurality of display data to a display device; and Adjusting an operating frequency of the image acquisition device according to the amount of data stored in the storage circuit; When the amount of data stored in the storage circuit is greater than a first critical value, the processing circuit reduces the operating frequency to slow down the speed at which the image acquisition device outputs the image data. When the amount of data stored in the storage circuit is less than a second critical value, the processing circuit increases the operating frequency to speed up the speed at which the image acquisition device outputs the image data. The first critical value is greater than the second critical value. 8. The control method according to claim 7, further comprising: receiving a pixel frequency; and receiving the plurality of image data according to the pixel frequency; When the operating frequency is reduced, the pixel frequency is a third value, and when the operating frequency is increased, the pixel frequency is a fourth value, and the third value is smaller than the fourth value.