TWI683230B - Chip and power planning method - Google Patents

Abstract

A chip includes a substrate; macros placed on the substrate, which has a placement region being divided into sub-regions according to locations of the macros; and one or more vertical power stripes (VPSs) disposed in each sub-region. At least one VPS is not aligned with the VPSs of an adjacent higher or lower sub-region.

Description

Chip and power planning method

The present invention relates to a power supply planning, and in particular to a power-out planning method and chip for macro-aware that can be based on routability-driven.

Power planning is an important step in the design of integrated circuits. Due to the shrinking of components, the unit area of the wafer can accommodate more electronic components, which greatly increases the power density of the wafer. The design efficiency of contemporary chips has gradually improved, causing the chips to consume a lot of dynamic power, making voltage drop a serious problem. When a lower supply voltage is used to reduce the dynamic power of the integrated circuit, the voltage drop problem becomes more serious due to the tolerable voltage drop value.

In order to provide stable and stronger power to components, power is generally transmitted to a macro or standard cell through a global power mesh. The power network includes a power ring, a horizontal power line, and a vertical power line, and is usually located in the top two metal layers. For example, the metal width of the upper metal layer is wider than other layers, and is generally used to set horizontal power lines. The vertical power line is placed on the next metal layer and must share the winding resources with signal nets. Therefore, the design of the power network must balance the voltage drop with the winding area (or congestion).

Due to continuous advances in manufacturing technology, contemporary system-on-a-chips can contain hundreds of intellectual property (IP) macros, such as embedded memory. All macros must be connected to a power/ground network, and power planning becomes more complicated. As the number of system-on-a-chip macros continues to increase, relying on experienced designers to manually perform power planning becomes inefficient.

Therefore, there is an urgent need to propose a novel power planning mechanism to increase the overall efficiency of the winding resources.

In view of the above, one of the objectives of the embodiments of the present invention is to propose a power-routing-driven macro-aware power planning method and chip, which can greatly improve the windability and according to the macro Position to promote the connection of the macro; propose an effective power winding width to improve the effective use of the overall winding resources; and provide a more accurate cost function, according to the dynamic programming algorithm to determine the position of the power line.

According to one embodiment of the present invention, the chip includes a substrate, a plurality of macros, and one or a plurality of vertical power lines. The macro is set on the substrate, and has a setting area, and the setting area is divided into a plurality of sub-areas according to the position of the macro. Vertical power lines are provided in each sub-region. At least one vertical power line is not aligned with the vertical power lines of the adjacent upper or lower sub-regions.

According to another embodiment of the present invention, a power planning method includes the following steps. (a) Provide a chip on which a plurality of macros are provided. (b) According to the position of the macro, the installation area of the wafer is divided into a plurality of sub-areas. (c) For each sub-region, determine the total power supply winding width of the vertical power supply line. (d) For each sub-region, divide the total power supply winding width by the effective power supply line width to obtain the number of vertical power supply lines. (e) For each sub-region, determine the position of the vertical power line.

The first figure shows a flowchart of a power planning method for macro-aware (hereinafter referred to as a power planning method) 110 that can be macro-aware according to an embodiment of the present invention.

In step 11, according to the position of the macro, the placement region of the chip is divided into a plurality of sub-regions (SR). In this specification, a chip (or microchip) refers to an integrated circuit, which contains an electronic circuit, such as an IP core or a macro, and is disposed on a semiconductor (eg, silicon) substrate. FIG. 2A shows a schematic top view of the wafer 200. The macro 21 (in the oblique area) is preset in the setting area 22.

As shown in Figure 2A, for each macro 21, a horizontal power strip (HPS) near (but not overlapping) the upper edge of the macro 21 is extended until it encounters another macro 21 or The boundary of the area 22 is set, and thus the first horizontal line is obtained. In a similar situation, the horizontal power line (HPS) close to (but not overlapping with) the lower edge of the macro 21 is extended until it meets the boundary of another macro 21 or the setting area 22, thereby obtaining a second horizontal line.

As shown in the second image B, the left edge of the macro 21 is extended until it meets the boundary of another macro 21 or the setting area 22, thus obtaining the first vertical line. In a similar situation, the right edge of the macro 21 is extended until it meets the boundary of another macro 21 or the setting area 22, thereby obtaining a second vertical line. Thereby, the first horizontal line, the second horizontal line, the first vertical line, and the second vertical line divide the installation area 22 of the wafer 200 into a plurality of sub-regions SR. As illustrated in the second B diagram, the solid lines represent (and define) the edges of these sub-regions SR. Therefore, any preset macro 21, regardless of its pin type, can be surrounded by a horizontal power line (HPS) and a vertical power strip (VPS) described below. In addition, according to the present embodiment, each sub-region SR can independently perform its power division, and thus the flexibility of power division can be greatly increased. In this embodiment, the horizontal power line (HPS) is provided on the first upper metal layer, and the vertical power line (VPS) is provided on the second upper metal layer, which is located under the horizontal power line and electrically insulated from each other.

Next, in step 12, at least one sub-region SR is merged with the adjacent sub-region SR. The second diagram C shows a schematic top view of the wafer 200 of the second diagram A, wherein the solid line represents the edge of the merged sub-region SR, and the dotted line represents the edge of the merged sub-region SR. In this way, some sub-regions with a small area (for example, less than a preset value) are merged into adjacent sub-regions SR to form a larger sub-region SR.

In one embodiment, vertical merge is performed first, followed by horizontal merge. Among them, each sub-region SR is checked in sequence. If the horizontal power line covered by the sub-region SR is less than a preset value (for example, two), the sub-region SR is merged into the lower sub-region SR (assuming that the sub-region SR exists and the two sub-regions SR have the same width ). Otherwise, the sub-region SR is merged into the higher sub-region SR (assuming that the upper sub-region SR exists and the two sub-regions SR have the same width). In a similar situation, if the vertical power lines covered by the sub-region SR are less than a preset value (for example, five), the sub-region SR is merged into the left sub-region SR (assuming that the left sub-region SR exists and the two sub-regions SR have the same height). Otherwise, the sub-region SR is merged into the right sub-region SR (assuming that the right sub-region SR exists and the two sub-regions SR have the same height).

In step 13, for each sub-region SR, the total power routing width (TPRW) of the vertical power line is determined, so that the minimum winding area can meet the voltage drop and electromigration conditions. The second diagram D shows a schematic top view of the wafer 200 of the second diagram A, wherein the dotted areas respectively represent the total power supply winding width TPRW of the vertical power supply lines of each sub-region SR. In this embodiment, the optimization sizing algorithm proposed by X.-D. Tan et al. is used to determine the total power supply winding width TPRW of the vertical power supply line. In this embodiment, the width of the horizontal power supply line is fixed, and the horizontal power supply lines are evenly spaced. For the details of the optimization estimation algorithm, please refer to "Reliability-Optimization of Power/Ground Reliability of Very Large Integrated Circuits by Sequential Linear Programming" proposed by X.-D. Tan et al. Constrained Area Optimization of VLSI Power/Ground Networks Via Sequence of Linear Programmings", published in Proceedings of DAC, pages 78~83, 2003, and its contents are considered as part of this manual.

Next, in step 14, the number of vertical power lines of each sub-region SR is determined. In this embodiment, the effective stripe width (ESW) is first determined. Next, the total power winding width TPRW (of step 13) is divided by the effective power line width (ESW) to obtain the number of vertical power lines in the sub-region SR.

(1) 其中T代表電源線所包含的軌道(track)數目，p為間距寬度，Δ(w)為二線之間的最小間隔，且W _min為最小金屬寬度。 According to "W.-H. Chang" et al. "Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad"Layer)", published in the IEEE Journal of Very Large Integrated Circuits (IEEE TVLSI), Volume 22, No. 5, pages 1069~1081, June 2013, the content of which is regarded as a part of this manual The width of non-redundant (irredundant) power line w _p can be expressed as a function of T:

(1) where T represents the number of tracks included in the power line, p is the pitch width, Δ(w) is the minimum interval between the two lines, and W _min is the minimum metal width.

(2) If w _v represents the width of the contact window (via contact), Δ _v2v represents the shortest distance between the two contact windows, and Δ _v2b represents the shortest distance between the contact window and the boundary of the coverage area. For the contact window array A _{rxs of} size _rxs , the width of the coverage area can be expressed as:

(2)

(3) 其中

表示頂函數(ceiling function)，其輸出值為大於或等於輸入值的最小整數。 The third figure illustrates a schematic diagram of the track occupied by the contact window array, which is used to connect different layers of metal of the power grid (mesh). A _rxs occupied by the winding number of the track T (A _rxs) can be expressed as follows:

(3) where

Represents a ceiling function, whose output value is the smallest integer greater than or equal to the input value.

(4) The formula (3) into the formula (1), to obtain the effective power line width (ESW) w _e as follows:

(4)

As described above, dividing the total power supply winding width TPRW (of step 13) by the effective power supply line width (ESW) (of equation (4)), the number of vertical power supply lines in the sub-region SR can be obtained.

Finally, in step 15, the position of the vertical power line VPS of each sub-region SR is determined. The second diagram E shows a schematic top view of the wafer 200 of the second diagram A, wherein the cross-hatched area represents the vertical power line VPS of each sub-region SR. In this embodiment, the dynamic programming algorithm proposed by Zhang et al. is used to determine the position of the vertical power line VPS of each sub-region SR. Unlike the algorithm proposed by Zhang et al., which is applied to the entire chip, this embodiment applies the algorithm to each sub-region SR, thus making the power line setting of this embodiment more flexible than Zhang's application. According to one of the features of this embodiment, the vertical power supply lines VPS are not uniformly arranged (although they have the same effective power supply line width), so in general, in the sub-region SR, the distance between adjacent vertical power supply lines VPS is not necessarily the same. Therefore, the sub-regions (or merged sub-regions) of this embodiment are called irregular regions, while the regions located in the macro 21 are called regular regions. In addition, since each sub-region SR individually determines the arrangement of the vertical power lines VPS, according to another feature of this embodiment, at least one vertical power line VPS and the vertical power lines VPS of the upper or lower sub-region SR are not aligned with each other. In other words, at least one vertical power line VPS is discontinuous at the boundary of the adjacent sub-region SR in the vertical direction.

其中

且

其中

代表C _i,j的平均值，σ代表標準差。 The fourth diagram A shows the winding area of the sub-region SR, divided into n tiles, where t _j represents the brick in the jth row, each brick contains m grids, and g _i,j represents t _j Grid i. e _i,j represents the horizontal top edge of the grid g _i,j . C _i,j represents the congestion value of the edge e _i,j , where C=d _i,j /c _i,j , c _i,j and d _i,j represent the winding capacity of the edge e _i,j respectively (routing capacity) and routing demand (which is related to the number of networks passing through e _i,j ). If δ _j represents the penalty or congestion cost of setting vertical power lines in brick t _j , it can be expressed as follows:

among them

And

among them

Represents the average value of C _i,j , and σ represents the standard deviation.

The fourth diagram B illustrates the congestion penalty value δ _{j of} each sub-region SR ₁ and SR ₂ , according to which the vertical power line VPS is set in the sub-regions SR ₁ and SR ₂ . For example, for the subregion SR ₁ , δ ₁ = (1/3)(100x(1/5)+(2/5)+(3/5))=7, δ ₂ = (1/3)((2 /5)+(2/5)+(2/5))=0.4. For the sub-region SR ₂ , δ ₂ = (1/2)(100x(2/3)+(1/3))=33.5.

According to the above embodiment, this embodiment proposes a row-based power mesh, which divides the chip 200 into a plurality of sub-regions SR according to the position of the macro 21. This embodiment can not only promote the power/ground connection of the macro 21, but also because the arrangement of the vertical power line has greater flexibility, so that the windability can be improved. Since the vertical power line of the traditional power network extends across the entire chip, a lot of winding resources are wasted in connecting these macros. FIG. 5A shows a schematic top view of a conventional design, in which multiple macros 41 have different pin 42 types. In this example, at least seven vertical power cables are required to connect to the power network. Figures 5B and 5C show schematic top views of embodiments of the present invention. Since the horizontal power line (HPS) has been distributed on the upper layer, in this embodiment, the wafer can be divided into multiple columns according to the position of the preset macro 41, as shown in the fifth B diagram. Then, the position of the vertical power line VPS of each sub-region can be independently planned. Therefore, in this embodiment, fewer vertical power lines VPS may be used to complete the power network, as shown in FIG. 5C. In addition, since the power lines of each sub-region can be adjusted independently, compared with the traditional use of longer (vertical) power lines, this embodiment can easily avoid the congestion region of the winding.

Based on the above, this embodiment also proposes a method to effectively determine an appropriate winding width. The width of the non-redundant power line proposed by Zhang et al. is determined according to the number of winding tracks occupied by the winding. This embodiment extends this concept, considering the contact window array to determine the power line width. The contact window array is usually located in the coverage area between the horizontal power line and the power line to reduce the impedance and improve the reliability of the power network. There are many options for the size of the contact window array, and larger arrays produce lower impedance. Since the width of the power line is restricted by the contact window array, when determining the width of the power line in this embodiment, the size of the contact window array must be considered.

It is worth noting that this embodiment starts power planning only after the placement phase is completed. According to the information of power consumption and winding congestion, a better power/ground power network can be designed. This embodiment proposes an accurate cost function. When setting the power line at a certain location, the relevant penalty value (or congestion cost) can be determined. According to the column-based power supply network and the better cost function, this embodiment can easily avoid the congested area of the winding when setting the power supply line.

The above are only the preferred embodiments of the present invention and are not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit of the invention should be included in the following Within the scope of patent application.

110‧‧‧Power planning method

11‧‧‧ Divide the setting area into sub-areas according to the position of the macro

12‧‧‧ merged sub-regions

13‧‧‧ Determine the total power winding width of the vertical power line in each sub-region

14‧‧‧decide the number of vertical power lines in each sub-region

15‧‧‧ Determine the position of the vertical power cord in each sub-region

200‧‧‧chip

21‧‧‧ Macro

22‧‧‧Set area

41‧‧‧Macro

42‧‧‧pin

SR‧‧‧Subregion

TPRW‧‧‧Total power supply winding width

VPS‧‧‧Vertical power cord

HPS‧‧‧Horizontal power cord

W _v ‧‧‧ Width of contact window

Δ _{v2v ‧‧‧The} shortest distance between contact windows

Δ _{v2b ‧‧‧The} shortest distance between the contact window and the boundary of the coverage area

W _Arxs ‧‧‧ width of coverage area

W _e ‧‧‧ effective power line width

t‧‧‧brick

g‧‧‧ grid

e‧‧‧ side

δ‧‧‧ Penalty

The first figure shows a flowchart of a power planning method that can be oriented to macro-cognition according to an embodiment of the present invention. Figures 2A to 2E show schematic top views of wafers with preset macros. The third figure illustrates a schematic diagram of the track occupied by the contact window array. The fourth image A shows the winding area of the sub-area. The fourth figure B illustrates the congestion penalty value of each sub-region. Figure 5A shows a schematic top view of a conventional design, with multiple macros having different pin types. Figures 5B and 5C show schematic top views of embodiments of the present invention.

110‧‧‧Power planning method

11‧‧‧ Divide the setting area into sub-areas according to the position of the macro

12‧‧‧ merged sub-regions

13‧‧‧ Determine the total power winding width of the vertical power line in each sub-region

14‧‧‧decide the number of vertical power lines in each sub-region

15‧‧‧ Determine the position of the vertical power cord in each sub-region

Claims (9)

A chip, comprising: a substrate; a plurality of macros, set on the substrate, having a setting area, the setting area is divided into a plurality of sub-regions according to the position of the plurality of macros; one or a plurality of vertical power lines are provided on Each of the sub-regions; and a plurality of horizontal power lines are provided on the first upper metal layer, the plurality of vertical power lines are provided on the second upper metal layer, which are located under the plurality of horizontal power lines; at least one of the vertical power lines and the phase The vertical power lines adjacent to the upper or lower subarea are not aligned with each other. The wafer according to item 1 of the scope of the patent application, in which the plurality of vertical power lines are arranged non-uniformly, therefore, the pitch of adjacent vertical power lines in the sub-region is not necessarily the same. The wafer according to item 1 of the scope of the patent application, wherein the plurality of horizontal power lines are evenly spaced. The wafer according to item 1 of the patent application scope, wherein at least two sub-regions have different numbers of vertical power lines. The wafer according to item 1 of the patent application scope, wherein at least two sub-regions have different total power supply winding widths. A power supply planning method includes: (a) providing a chip on which a plurality of macros are provided; (b) dividing the installation area of the chip into a plurality of sub-regions according to the position of the plurality of macros; (c) for each A sub-area determines the total power winding width of the vertical power line; (d) For each subregion, divide the total power supply winding width by the effective power supply line width to obtain the number of the vertical power supply lines; and (e) For each subregion, determine the position of the vertical power supply line; The step (b) includes: for each macro, extend the horizontal power line near the upper edge of the macro until it touches another macro or the boundary of the setting area, thus obtaining the first horizontal line; for each Macro, extend the horizontal power line near the lower edge of the macro until it meets another macro or the boundary of the setting area, thus obtaining a second horizontal line; for each macro, extend the left edge of the macro Until it meets another macro or the boundary of the setting area, and thus the first vertical line is obtained; for each macro, the right edge of the macro is extended until it meets the boundary of another macro or the setting area, thus A second vertical line is obtained; wherein the first horizontal line, the second horizontal line, the first vertical line, and the second vertical line of the complex macro divide the setting area into the complex sub-areas. The power planning method according to item 6 of the patent application scope, wherein if the vertical power line covered by the sub-region is less than the preset value, the sub-region is merged into the left sub-region, assuming that the left sub-region exists and these two The sub-regions have the same height; otherwise, the sub-region is merged into the right sub-region, assuming that the right sub-region exists and the two sub-regions have the same height. According to the power supply planning method described in Item 6 of the patent application range, in which the vertical power supply lines are arranged non-uniformly, the intervals between adjacent vertical power supply lines are not necessarily the same. According to the power planning method described in Item 6 of the patent application scope, at least one vertical power line is not aligned with the vertical power lines of the adjacent upper or lower sub-regions.

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