CN100578776C - Integrated circuit chip and its power line structure - Google Patents

Abstract

The invention relates to a power line structure which is manufactured on an integrated circuit chip, wherein the integrated circuit chip is provided with a main metal layer and a first metal layer. The power line structure comprises at least one power pattern, a plurality of first power strips and a plurality of first power main channels. The power pattern is formed on an edge of the main metal layer, the first power strips are formed on the first metal layer in parallel to each other, and the first power trunk is formed on the main metal layer in parallel to each other. The first power trunk is used for respectively connecting the first power strip to the power pattern, wherein the ratio of the trunk length to the width of each of the plurality of first power trunks is equal.

Description

Integrated circuit chip and its power line structure

technical field

The invention relates to the field of integrated circuit chips, in particular to an integrated circuit chip and a power line structure of the chip.

Background technique

With the increasing trend of functional diversification and integration of various consumer electronic products, integrated circuit chips must integrate more components such as transistors to achieve more expected functions. However, doing so relatively increases the dynamic power consumption of the integrated circuit chip, thus causing uneven distribution of voltage values. This phenomenon of uneven distribution of voltage values will cause differences in the voltages of the components in the integrated circuit chip, and in actual work, there may be results that do not meet the designer's expectations.

First, please refer to FIG. 1A , which is a top view of a conventional power line structure applied to an integrated circuit chip. As shown in FIG. 1A , a power line structure 1 is fabricated on an integrated circuit chip 19 . The power cord structure 1 has a plurality of first power strips 11 , a plurality of second power strips 12 and a power ring 13 . Meanwhile, a plurality of power patterns 10 are disposed on the edge of the integrated circuit chip 19 , and the power patterns 10 are electrically coupled to an external voltage source. The power ring 13 surrounds the integrated circuit chip 19 and is connected to the power pattern 10 through the via array 14 on each edge. The first power strips 11 and the second power strips 12 are interlaced to form a grid, and are respectively connected to the power rings 13 to form a power voltage network on the integrated circuit chip 19 .

Next, please refer to FIG. 1B , which is a schematic diagram of the voltage distribution of the integrated circuit chip 19 shown in FIG. 1A . As shown in FIG. 1B , when a power supply voltage of 1.8V is provided to the integrated circuit chip 19 , its operating voltage decreases from the periphery to the interior, and the voltage difference between the periphery and the interior is as high as 60 mV. The reason for this phenomenon is that the path for transmitting the power voltage between the first power strip 11 and the second power strip 12 itself has resistance, and the longer the transmission path, the lower the voltage; at the same time, generally speaking, the integrated circuit The components inside the chip 19 are densely distributed, therefore, the closer to the center, the greater the power consumption value. Both of the above are the causes of the uneven distribution of voltage values, and how to reduce the voltage difference value of the integrated circuit chip 19 is a problem that designers have always hoped to solve.

Please refer to FIG. 2A , which is a top view of another conventional power line structure applied to an integrated circuit chip. The structure of this prior art is disclosed in US Patent No. 6111310, which proposes a radially distributed grid-like power line structure in order to solve the above problems. As shown in FIG. 2A, the first power strip 21 and the second power strip 22 of the power cord structure 2 are respectively connected to the power ring 20, and the first power strip 21 and the second power strip 22 form a grid form interlaced with each other. . This prior art changes the widths of the first power strip 21 and the second power strip 22 along their positions relative to the center.

Next, please refer to FIG. 2B and FIG. 2C. FIG. 2B is a schematic diagram of the voltage distribution expected to be improved by using the structure of FIG. 2A, and FIG. 2C is a schematic diagram of the voltage distribution using the power line structure of the integrated circuit chip of FIG. From the comparison of FIG. 2B and FIG. 2C , it can be known that the 6111310 scheme can reduce the area of each voltage value difference. However, the voltage difference shown in FIG. 2C is still the same as that in FIG. 2B, which is 250 mV. It can be seen that this prior art cannot reduce the voltage difference value inside the chip.

In order to solve the above problems, the inventor of this case proposed the content of the invention in this case. The technology provided in this case can effectively reduce the voltage difference value inside the integrated circuit chip, and then can improve its working efficiency, thereby bringing many benefits to the field.

Contents of the invention

The purpose of the present invention is to provide an integrated circuit chip and its power line structure, which can effectively reduce the The voltage difference value of an integrated circuit chip.

In order to achieve the above object, the present invention discloses a power line structure, which is manufactured on an integrated circuit chip, and the integrated circuit chip has a main metal layer and a first metal layer. The power line structure includes at least one power pattern, a plurality of first power strips and a plurality of first power trunks. The power pattern is formed on the edge of the main metal layer. The plurality of first power strips are formed parallel to each other on the first metal layer. The multiple first power rails are formed parallel to each other on the main metal layer, and the multiple first power rails are used to respectively connect the multiple first power strips to the power pattern, wherein the multiple first power rails The ratio of the length of each main power supply main road to the width of the main road is equal.

In a specific embodiment of the present invention, the integrated circuit chip further has a second metal layer, and the power line structure further includes a plurality of second power strips and a plurality of second power trunks. The plurality of second power strips are formed parallel to each other on the second metal layer. The plurality of second power rails are formed parallel to each other on the main metal layer, and the plurality of second power rails respectively connect the plurality of second power strips to the at least one power pattern, wherein the plurality of second power The ratio of the length of each main power supply main road to the width of the main road is equal.

The invention also discloses an integrated circuit chip, which includes a first metal layer and a main metal layer. A plurality of first power strips are formed on the first metal layer, and the plurality of first power strips are parallel to each other. The main metal layer is parallel to the first metal layer, and at least one power pattern and a plurality of first power rails are formed on it. The at least one power pattern is formed on the edge of the main metal layer, the plurality of first power rails are parallel to each other, and respectively connect the plurality of first power strips to the at least one power pattern, wherein the plurality of first The ratio of the length of each power trunk to the width of the trunk is equal.

In a specific embodiment of the present invention, the integrated circuit chip further has a second metal layer. A plurality of second power strips are formed on the second metal layer, and the plurality of second power strips are parallel to each other. A plurality of second power supply trunks are also formed on the main metal layer, and the plurality of second power supply trunks respectively connect the plurality of second power supply strips to the at least one power supply pattern, wherein each of the plurality of second power supply trunks The ratio of the length of the trunk road to the width of the trunk road is equal.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

FIG. 1A is a top view of a conventional power line structure applied to an integrated circuit chip;

FIG. 1B is a schematic diagram of the voltage distribution of the integrated circuit chip of FIG. 1A;

FIG. 2A is a top view of another existing power line structure applied to an integrated circuit chip;

FIG. 2B is a schematic diagram of the voltage distribution expected to be improved by using the structure of FIG. 2A;

2C is a schematic diagram of voltage distribution using the power line structure of the integrated circuit chip of FIG. 2A;

3 is a top view of the first embodiment of the integrated circuit chip and its power line structure disclosed by the present invention;

Fig. 4 is a top view of the second embodiment of the integrated circuit chip and its power line structure disclosed by the present invention;

FIG. 5 is a schematic diagram of the voltage distribution of the integrated circuit chip in FIG. 4 .

Among them, reference signs:

1, 2, 3, 4-power cord structure

10, 30a, 30b, 40a, 40b, 40c, 40d-power pattern

11, 12-power belt

13, 20-power ring

14-via array

19, 39, 49 - integrated circuit chip

21, 31a, 31b, 31c, 31d, 31e, 31f, 41a, 41b, 41c, 41d,

41e, 41f - first power strip

35a, 35b, 35c, 35d, 35e, 35f-the first main power supply road

36, 47-conduction through hole

22, 42a, 42b, 42c, 42d, 42e, 42f - second power strip

45a, 45b, 45c, 45d, 45e, 45f-the first main power supply road

46a, 46b, 46c, 46d, 46e, 46f-the second main power supply

C1, C2-the first centerline

C3-Second Centerline

Detailed ways

First, please refer to FIG. 3 , which is a top view of the first embodiment of the integrated circuit chip and its power line structure disclosed by the present invention. As shown in FIG. 3 , a power line structure 3 is fabricated on an integrated circuit chip 39. The power line structure 3 is a network evenly distributed on the integrated circuit chip 39 for electrically coupling to an external voltage source. To transmit the power supply voltage to the components on the integrated circuit chip 39 .

In the first embodiment, the integrated circuit chip 39 has a main metal layer and a first metal layer (not shown), the main metal layer and the first metal layer are parallel to each other. In FIG. 3, the power line structure 3 has two power supply patterns 30a, 30b (hereinafter, unless otherwise specified, each power supply pattern is marked as 30), a plurality of first power strips 31a, 31b, 31c, 31d, 31e, 31f (unless otherwise specified below, mark each first power supply belt as 31) and multiple first power supply trunks 35a, 35b, 35c, 35d, 35e, 35f (unless otherwise specified below, each first power supply The main road is marked as 35). The power pattern 30a, 30b is formed on the edge of the main metal layer. The plurality of first power strips 31 are formed parallel to each other on the first metal layer. Meanwhile, the first power rails 35 are formed parallel to each other on the main metal layer, and are used to respectively connect the first power strips 31 to the power patterns 30a, 30b. Meanwhile, a dielectric layer is usually used as an insulating space between the main metal layer and the first metal layer. Therefore, each of the first power rails 35 disposed on the main metal layer is respectively connected to each of the first power rails 31 disposed on the first metal layer through a conductive via 36 . In the first embodiment, six first power strips 31 and six first power trunks 35 are used for example only, and are not intended to limit the scope of the present invention.

It must be mentioned that the power pattern 30 refers to a region that can be connected to an external voltage source to provide power. The power supply patterns 30a, 30b in FIG. 3 are disposed on two corresponding edges of the main metal layer in a manner of being separated from each other. Meanwhile, the power supply pattern 30 can also continuously surround the edge of the main metal layer. The power supply pattern 30 in the first embodiment is only an illustration and is not intended to limit the scope of the present invention.

At the same time, FIG. 3 shows a general layout of power lines, the first main power rail 35 is substantially vertically overlapped with the first power strip 31 . Moreover, based on a preferred layout method, the first power strip 31 is divided into two parts by the first central line _C1 of the integrated circuit chip 39 . That is to say, the first power supply belt 31 can be divided into M first power supply belts 31 and N first power supply belts 31 distributed continuously by the first central line _C1 parallel to it, and M and N are respectively a natural number , and the value of M is equal to the value of N. The first power rails 35 individually connect the M first power strips 31 and the N first power strips 31 to their respective adjacent power patterns 30 , so as to shorten the winding length.

As shown in FIG. 3 , the first power strip 31 is divided into three first power strips 31 a , 31 b , 31 c and another three first power strips 31 d , 31 e , 31 f by the first central line C ₁ . Among them, the first power strips 31a, 31b, 31c are respectively connected to the metal pattern 30a through the first power trunks 35a, 35b, 35c; to the metal pattern 30b.

As shown in Figure 3, the first main power supply roads 35a, 35b, 35c, 35d, 35e, 35f respectively have a main road length L, 2L, 3L, L, 2L, 3L and a main road width W, 2W, 3W, W, 2W , 3W. Obviously, the ratio of the trunk length to the trunk width of each first power trunk 35 is L/W. In order to reduce the difference in the voltage value of the integrated circuit chip 39, the inventor specially utilizes the first power trunk 35 with different trunk lengths and trunk widths to transmit the voltage source to the first power strip 31, and each first power trunk 35 The ratio of the length of the main road to the width of the main road is equal. In this way, as shown in formula (1), the resistances of each of the first power mains 35a, 35b, 35c, 35d, 35e, 35f are equal. The power supply voltage is firstly consumed by each first power supply trunk 35 and then supplied to each first power supply belt 31 .

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; L</span>}}{\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; L</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; \&times;</span>\frac{\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; <figure-callout\; id="3W"\; label="L"\; filenames="C2007100911760016H1.png"\; state="\{\{state\}\}">L</figure-callout></span>}}{\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; W</span>}}<span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; .</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

In formula (1), R _S is the resistance value per unit area of the length L and the width W.

Next, please refer to FIG. 4 , which is a top view of a second embodiment of the integrated circuit chip and its power line structure disclosed by the present invention. As shown in FIG. 4 , the power line structure 4 is fabricated on an integrated circuit chip 49 . The integrated circuit chip 49 has a main metal layer, a first metal layer and a second metal layer (not shown in the figure) parallel to each other. The power line structure 4 includes four power supply patterns 40a, 40b, 40c, 40d (if not specified below, each power supply pattern is marked as 40), a plurality of first power strips 41a, 41b, 41c, 41d, 41e, 41f (unless otherwise specified below, mark each first power supply belt as 41), a plurality of second power supply belts 42a, 42b, 42c, 42d, 42e, 42f (unless otherwise specified below, each second power supply belt marked as 42), a plurality of first power supply trunks 45a, 45b, 45c, 45d, 45e, 45f (hereinafter, unless otherwise specified, each first power supply trunk is marked as 45) and a plurality of second power supply trunks 46a, 46b, 46c, 46d, 46e, 46f (unless otherwise specified below, each second power supply trunk is marked as 46).

As shown in FIG. 4, the first power strip 41 and the second power strip 42 are respectively formed on the first metal layer and the second metal layer in parallel, and the power pattern 40, the first power rail 45 and the second Power rails 46 are formed on the main metal layer. Wherein, the difference between this second embodiment and the aforementioned first embodiment is that, in this embodiment, the first power supply strip 41 and the second power supply strip 42 of the power supply line structure 4 form a mutually vertical interlaced network. format. The first power trunk 45 is perpendicular to the first power belt 41 , and at the same time, the second power trunk 46 is perpendicular to the second power strip 42 .

Based on the preferred layout mode, the first power strip 41 is divided into two parts by the first central line _C2 of the integrated circuit chip 49; Centerline C ₃ is divided into two parts. That is to say, the first power supply belt 41 can be divided into M first power supply belts 41 and N first power supply belts 41 distributed continuously by the first central line _C2 parallel thereto; the second power supply belt 42 can be It is divided into P second power strips 42 and Q second power strips 42 distributed continuously by the second central line _C3 parallel to it, M, N, P, and Q are each a natural number, and the value of M is equal to the value of N, and The P value is equal to the Q value. The first power trunk 45 respectively connects the M first power strips 41 and the N first power strips 41 to their respective adjacent power patterns 40; the second power trunk 46 respectively connects the M second The power strips 42 and the N second power strips 42 are connected to their respective adjacent power patterns 40 to shorten the winding length.

As shown in FIG. 4 , the first power strip 41 is divided into three first power strips 41a, 41b, 41c and another three first power strips 41d, 41e, 41f by the first central line _C2 . Each first power strip 41 is connected to its respective adjacent power pattern 40 to shorten the winding length. Among them, the first power supply belts 41a, 41b, 41c are respectively connected to the power pattern 40a through the first power trunk roads 45a, 45b, 45c; to power pattern 40b.

Similarly, the second power strip 42 is divided into three second power strips 42a, 42b, 42c and another three second power strips 42d, 42e, 42f by the second central line _C3 . Each second power strip 42 is connected to its respective adjacent power pattern 40 to shorten the winding length. Wherein, the second power supply belts 42a, 42b, 42c are respectively connected to the power supply pattern 40c through the second power main roads 46a, 46b, 46c; the second power supply belts 42d, 42e, 42f are respectively connected through the second power main roads 46d, 46e, 46f to power pattern 40d.

Each of the above-mentioned first power rails 45 and each of the second power rails 46 are respectively connected to each of the first power strips 41 and each of the second power strips 42 through a conductive through hole 47 .

Meanwhile, the first power trunks 45a, 45b, 45c, 45d, 45e, 45f respectively have a trunk length L, 2L, 3L, L, 2L, 3L and a trunk width W, 2W, 3W, W, 2W, 3W. And the second power trunks 46a, 46b, 46c, 46d, 46e, 46f respectively have a trunk length L, 2L, 3L, L, 2L, 3L and a trunk width W, 2W, 3W, W, 2W, 3W. The ratio of the trunk length to the trunk width of each first power trunk 45 and each second power trunk 46 is L/W.

Next, please refer to FIG. 5 , which is a voltage distribution diagram of the integrated circuit chip 49 in FIG. 4 . In order to prove that the proposed scheme can reduce the voltage difference of the integrated circuit chip 49 , the inventor especially used voltage drop analysis software to simulate the voltage distribution of the integrated circuit chip 49 according to the second embodiment of the present invention. According to the simulation result of FIG. 5, the voltage structure of the integrated circuit chip 49 forms four blocks, and the voltage value of each block gradually decreases from the periphery to the inside, and the voltage difference is only 15mV, which is far lower than that of the prior art. Voltage differential values for several power cord configurations are provided.

From the above specific examples, it can be known that the integrated circuit chip and its power line structure disclosed in the present invention utilize the main power line with the same resistance value to connect the power strip to the power pattern. In this way, the voltage difference between the inside and outside of the integrated circuit chip can be reduced, and the uniformity of the voltage value can be improved, so that the working performance of the integrated circuit chip can meet the expected result of the designer.

Of course, the present invention can also have other various embodiments, and those skilled in the art can make various corresponding changes and deformations according to the present invention without departing from the spirit and essence of the present invention, but these corresponding Changes and deformations should all belong to the protection scope of the appended claims of the present invention.

Claims (27)

1, a kind of power line structure is characterized in that, this power line structure is produced on the integrated circuit (IC) chip, and this integrated circuit (IC) chip has a main metal level and a first metal layer, and this power line structure comprises:

At least one power supply pattern is formed on the edge of this main metal level;

Many first Power supply belts are formed on this first metal layer in parallel to each other;

Many first power supply arterial highways, be formed in parallel to each other on this main metal level, these many first power supply arterial highways were in order to should be connected to this at least one power supply pattern by many first Power supply belts respectively, and wherein the arterial highway length of every power supply arterial highway of these many first power supply arterial highways equates with the ratio of arterial highway width.

2, power line structure as claimed in claim 1 is characterized in that, these many first power supply arterial highways are overlapped in these many first Power supply belts with vertical in form.

3, power line structure as claimed in claim 1 is characterized in that, these many first power supply arterial highways are connected to these many first Power supply belts by the conducting perforation respectively.

4, power line structure as claimed in claim 1, it is characterized in that, these many first Power supply belts are divided into M bar first Power supply belt and N bar first Power supply belt of continuous distribution by one first center line of this integrated circuit (IC) chip, M and N are respectively a natural number, and this first center line is parallel to this first Power supply belt.

5, power line structure as claimed in claim 4 is characterized in that, this M value equates with this N value.

6, power line structure as claimed in claim 4 is characterized in that, these many first power supply arterial highways are connected to its this at least one power supply pattern of institute's adjacency respectively with this M bar first Power supply belt and this N bar first Power supply belt respectively.

7, power line structure as claimed in claim 6 is characterized in that, this integrated circuit (IC) chip also has one second metal level, and this power line structure also comprises:

Many second source bands are formed on this second metal level in parallel to each other;

Many second source arterial highways, be formed in parallel to each other on this main metal level, these many second source arterial highways should be connected to this at least one power supply pattern by many second source bands respectively, and wherein, the arterial highway length of every power supply arterial highway of these many second source arterial highways equates with the ratio of arterial highway width.

8, power line structure as claimed in claim 7 is characterized in that, these many second source arterial highways are connected to this many second source bands by the conducting perforation respectively.

9, power line structure as claimed in claim 8 is characterized in that, these many second source bands are overlapped in these many first Power supply belts with vertical in form, and these many second source arterial highways are overlapped in this many second source bands with vertical in form.

10, power line structure as claimed in claim 9, it is characterized in that, these many second source bands are divided into the P bar second source band and the Q bar second source band of continuous distribution by one second center line of this integrated circuit (IC) chip, P and Q are respectively a natural number, and this second center line is parallel to this second source band.

11, power line structure as claimed in claim 10 is characterized in that, this P value and this Q value equate.

12, power line structure as claimed in claim 10 is characterized in that, these many second source arterial highways are connected to its this at least one power supply pattern of institute's adjacency respectively with this P bar second source band and this Q bar second source band respectively.

13, power line structure as claimed in claim 7 is characterized in that, the arterial highway length of every power supply arterial highway of these many first power supply arterial highways and these many second source arterial highways equates with the ratio of arterial highway width.

14, a kind of integrated circuit (IC) chip is characterized in that, comprising:

One the first metal layer is formed with many first Power supply belts on this first metal layer, these many first Power supply belts are parallel to each other;

One main metal level, be parallel to this first metal layer, be formed with at least one power supply pattern and many first power supply arterial highways on this main metal level, this at least one power supply pattern is formed on the edge of this main metal level, these many first power supply arterial highways are parallel to each other, and should be connected to this at least one power supply pattern by many first Power supply belts respectively, wherein, the arterial highway length of every power supply arterial highway of these many first power supply arterial highways equates with the ratio of arterial highway width.

15, integrated circuit (IC) chip as claimed in claim 14 is characterized in that, these many first power supply arterial highways are overlapped in these many first Power supply belts with vertical in form.

16, integrated circuit (IC) chip as claimed in claim 14 is characterized in that, these many first power supply arterial highways are connected to this first Power supply belt by the conducting perforation respectively.

17, integrated circuit (IC) chip as claimed in claim 14, it is characterized in that, these many first Power supply belts are divided into M bar first Power supply belt and N bar first Power supply belt of continuous distribution by one first center line of this integrated circuit (IC) chip, M and N are respectively a natural number, and this first center line is parallel to this first Power supply belt.

18, integrated circuit (IC) chip as claimed in claim 17 is characterized in that, this M value equates with this N value.

19, integrated circuit (IC) chip as claimed in claim 17 is characterized in that, these many first power supply arterial highways are connected to its this at least one power supply pattern of institute's adjacency respectively with this M bar first Power supply belt and this N bar first Power supply belt respectively.

20, integrated circuit (IC) chip as claimed in claim 19 is characterized in that, also has one second metal level, is formed with many second source bands on this second metal level, and these many second source bands are parallel to each other.

21, integrated circuit (IC) chip as claimed in claim 20, it is characterized in that, also be formed with many second source arterial highways on this main metal level, these many second source arterial highways should be connected to this at least one power supply pattern by many second source bands respectively, and wherein the arterial highway length of every power supply arterial highway of these many second source arterial highways equates with the ratio of arterial highway width.

22, integrated circuit (IC) chip as claimed in claim 21 is characterized in that, these many second source bands are overlapped in these many first Power supply belts with vertical in form, and these many second source arterial highways are overlapped in this many second source bands with vertical in form.

23, integrated circuit (IC) chip as claimed in claim 21 is characterized in that, this second source arterial highway is connected to this second source band by the conducting perforation respectively.

24, integrated circuit (IC) chip as claimed in claim 21, it is characterized in that, these many second source bands are divided into the P bar second source band and the Q bar second source band of continuous distribution by one second center line of this integrated circuit (IC) chip, P and Q are respectively a natural number, and this second center line is parallel to this second source band.

25, integrated circuit (IC) chip as claimed in claim 24 is characterized in that, this P value and this Q value equate.

26, integrated circuit (IC) chip as claimed in claim 24 is characterized in that, these many second source arterial highways are connected to its this at least one power supply pattern of institute's adjacency respectively with this P bar second source band and this Q bar second source band respectively.

27, integrated circuit (IC) chip as claimed in claim 21 is characterized in that, the arterial highway length of every power supply arterial highway of these many first power supply arterial highways and these many second source arterial highways equates with the ratio of arterial highway width.

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