JPS60158645A - Semiconductor integrated circuit wiring method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a wiring system in a semiconductor integrated circuit, and particularly to a wiring system for a circuit device having a multilayer wiring structure.

[Background of the invention]

With the advancement of LSI manufacturing technology, the wiring layers used for wiring between elements have changed to conventional polysilicon layers (Ps layers) and metal layers (
From a total of two layers (typically AQ layer) to three-layer wiring with the addition of a metal layer, it is becoming a reality. When this wiring layer is an automatic wiring method, the running direction of the wiring in each layer is defined in advance. For example, each wiring on the two wiring layers 1° 2. ) are defined by mutually orthogonal wiring grids. Here, the wirings 1a, lb... on the wiring layer 1 are AQ
, the wirings 2a, 2b, . . . on the wiring layer 2 are made of AQ, and the wiring on the wiring layer 3 is made of polysilicon Ps.

Connections between each layer are made by contact holes (also called through holes, not shown) placed at the intersections of the grid.

Now, each element on the LSI as shown in FIG.
The input/output terminals 6, 7 of the ND gates 4, 5, etc. are usually on a polysilicon layer, so if the terminal connections between the gates are automatically wired using conventional two-layer wiring (polysilicon layer and AQ-IJW), This is done using a polysilicon layer 9 in the X direction and an AQ-1 layer 10 in the X direction. 11 is a contact hole.

However, the wiring resistance of polysilicon is nearly 1000 times that of AQ, and as a result of automatic wiring, the polysilicon wiring in the X direction becomes too long.
I had a problem with signal delay.

[Summary of the invention]

In the present invention, in the layout design (also referred to as placement and wiring design) of an LSI chip, two wiring layers having different resistance values are referred to as JL and B layer for convenience. It is assumed that layer A has a lower resistance than layer B. -For example, the A layer is an aluminum wiring layer,
BW corresponds to a polysilicon wiring layer. ) is used selectively and has strict constraints on signal delay (nets 1-).
By using the A layer for terminals connected with the same signal (a set of terminals connected with the same signal) and the Bl wiring layer for other terminals 1 to 1, the signal delay caused by the wiring length can be avoided without increasing the depth area. This invention relates to an LSI automatic wiring system that enables control of

Here, as shown in the above-mentioned FIG. 1, by providing the second aluminum wiring layer (AQ-2 layer) 2 in the X direction, signal delay caused by the increase in the wiring length in the X direction due to the polysilicon can be prevented. We can expect that. However, if all X-direction wiring is done with AQ-2M2, as can be easily seen from Figure
- Twice the number of grids is required compared to the above case, which results in an increase in the chip area. The increase in chip area is
This is a problem because it causes a decrease in LSI manufacturing yield.

"On the other hand, if the distance between the gate terminals to be connected to each other is short, it is possible to use the wiring 3 made of a polysilicon layer without using the AQ-2 layer 2.

Therefore, a polysilicon layer is used for short distance wiring.

By switching the wiring layer used depending on the situation, such as using the AQ-2 layer for long-distance wiring, we can effectively utilize each wiring layer to suppress the increase in depth area and maintain signal delay within the specified level. can be realized.

The present invention automates such processing, and step number 3 thereof will be explained below.

[Embodiments of the invention]

Figure 3 (a) schematically shows an example of the arrangement of elements.
Each element is a logical unit (cell C) as shown in the same figure (b).
For example, NAND, NOR gates, flip-flops, etc.), and this cell serves as a unit of arrangement in layout design. In this example, there are three cell columns CA□, CA2 .
It consists of CAg. This arrangement is realized by a program in a process called automatic arrangement, but since the present invention does not deal with arrangement processing, the details thereof will be omitted.

Now, one of the LS and I configuration methods targeted by the present invention is a custom LSI using the so-called building block method.
There is. This differs from the other LSI configuration methods, the gate array type or master slice type, in that the cell placement position is not fixed, and the absolute position of the cell cannot be determined until all wiring is completed. It is confirmed. Therefore, at the end stage of the automatic placement process,
For each cell C shown in , the permutation within one column CA, etc. is only determined, and the y-coordinate of each cell column is in an undetermined state.

However, in the automatic wiring at the later stage, in order to achieve the above-mentioned requirement, ``wire between distant terminals with AQ-2 layer, and between nearby terminals with polysilicon layer.'' It is necessary to know the X-direction coordinates between the terminals of each cell when the arrangement is completed. Also, 5.1 above [distant, near]
It is necessary to understand this expression in terms of quantitative values.

The procedure realized by the present invention will be explained below using FIG. 4.

Step I: For each cell column in which the relative permutation of cells is defined, wiring between each cell column is performed using a wiring method called "channel assignment method j."

The channel allocation method is to
Regarding the terminals on the upper and lower sides of the area, line segment II formed by the leftmost and rightmost terminals of each net
This refers to a method of extracting I (this is called a trunk line) and arranging it in a wiring grid number two so that the trunk lines of each net do not overlap with each other. (Refer to the document rMO8-LSI Layout CAD: Ozawa, Horino (1972 Federation of Electrical Engineers of Japan Conference)") This calculates the number of main lines in each wiring area, and by counting the number of main lines in the y direction, the wiring area The height of is reduced.

This is designated as H4 (i is each wiring area number).

Step 2 Find a cell with an output terminal in each net, and find the distance in the y direction to the input terminal in screws 1 to 1.

The following formula is used to calculate the distance.

(lj = ΣH, +C-, m Qj: Distance in the y direction from the output terminal to the terminal j within the net Hk: Each wiring area that traverses from the output terminal to the terminal j within the screw 1 Height C, ,: Height of the cell row extending vertically from the output terminal to the terminal j inside the screw 1 Step 3 For each QJ, compare 9.1 and θ.Here, θ is the polysilicon This is the criterion value for switching between modes for AQ-2, and is a value that can be set externally.

If Q''≦0, a polysilicon layer is used for wiring in the y direction between the output terminal and the terminal j.

(t”>θ, the y direction between the output terminal and terminal j is Δ
ff-2 layer].

Repeat steps 2 and 3 for all nets.

The above is the processing procedure of the present invention.

〔Effect of the invention〕

According to the present invention, the vertical distance between each terminal is accurately estimated based on the arrangement state, and the obtained value is used to estimate the vertical distance between two terminals with different resistance values.
By selecting two wiring layers more precisely, it becomes possible to perform automatic wiring that can control signal delays caused by wiring length while suppressing an increase in chip area. It is extremely effective.

[Brief explanation of drawings]

Fig. 1 is a diagram schematically showing the multilayer arrangement structure, Fig. 2 is a schematic diagram showing the wiring state between elements, Fig. 3 is a schematic diagram showing the arrangement state of cells, and Fig. 4 is a detailed diagram of the present invention. To explain the relationship between cell placement and wiring, Figure 2 and Figure 3 (A) (0)

Claims (1)

[Scope of Claims] At least two wiring layers have wiring running in the same direction, and each of the two wiring layers has three or more layers each made of two different materials, a high-resistance wiring material and a low-resistance wiring material. Regarding wiring between terminals in a multilayer wiring semiconductor integrated circuit, (1) For each terminal group connected by the same signal, among the coordinates of the terminal group within the group, the coordinate component h 1 that is the same as the running direction of the high resistance wiring layer. t h2 y・・・・・・
hn (n is the number of terminals in the group); (2) Among the extracted coordinate components, the coordinate component h of the output terminal
Difference Q between coordinate components of o++l and input terminal (j), +=l
(3) Compare the above QJ with the preset reference value θ. (4) Depending on the magnitude of the comparison result, (a) If Q, ≦θ, use a high resistance wiring layer for wiring)
A semiconductor integrated circuit wiring method characterized in that if Q, 〉θ, wiring is performed using a low resistance wiring layer.