TWI682440B - Method of manufacturing a semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device for suppressing channeling during ion implantation of a polycrystalline silicon layer (4) is to use a patterned first photoresist layer (5) for the polycrystalline silicon layer (4) ) Exposed at the opening of the second photoresist layer (8), using the first photoresist layer (5) as a mask for the gate electrode (4-1) formed of the polycrystalline silicon layer (4), Ion implantation of impurities.

Description

Method for manufacturing semiconductor device

The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of forming an ion implanted impurity layer for self-aligning the pattern of a polycrystalline silicon layer.

As one example of the use of the formation of the self-aligned impurity layer for the pattern of the polycrystalline silicon layer, in the manufacture of conventional MOS transistors, the source of the transistor is formed. Impurity layer in the drain area. Take the project shown below.

First, as shown in FIG. 2( a ), for example, an element isolation insulating film 12 and a gate insulating film 13 are formed on a silicon substrate 11. Next, after the polycrystalline silicon layer 14 is formed on the entire surface of the silicon substrate 11, a photoresist is applied, and a patterned photomask corresponding to the polycrystalline silicon layer 14 is exposed to form a first photoresist layer 15.

Next, as shown in FIG. 2(b), using the first photoresist layer 15 as a masking material, the polycrystalline silicon layer 14 is etched away to form a gate electrode 14-1 made of the polycrystalline silicon layer 14, After 14-2, resistance 14-3 and wiring, remove The first photoresist layer 15.

Next, as shown in FIG. 2(c), the source of the MOS transistor, for example, with the gate electrode 14-1 as the electrode, is expected. The drain can be formed in the desired way, the second photoresist layer 16 is patterned, and the source is selectively formed by ion implantation. Drain impurity layer 17.

At this time, the opening of the second photoresist layer 16 in which ion implantation of impurities is performed is not only the source of the desired MOS transistor. In the drain field, it is formed even on the gate electrode 14-1. Therefore, the gate electrode 14-1 becomes a mask during ion implantation, enabling the source electrode to be self-aligned on the gate electrode 14-1. Drain impurity layer 17.

This has the advantages shown below.

(1) No need to consider the source. The alignment of the drain impurity layer and the photoresist pattern processing of the gate electrode is deviated, and the miniaturization of this part of the transistor becomes possible.

(2) No need to source. The photoresist pattern for the drain impurity layer is finely processed to be more than necessary, and at least the source electrode can be made more easily. Processing for drain impurity layer.

As shown above, the gate electrode pattern for the polycrystalline silicon layer self-aligns to form the holding source. MOS transistor of drain impurity layer.

As shown in FIG. 2(d), as necessary, for example, for the MOS transistor with the gate electrode 14-2 as the electrode, repeat the above-mentioned process of FIG. 2(c) in the desired field to form the source. The drain impurity layer 18 forms a plurality of MOS transistors.

Hold the source self-aligned. The MOS transistor of the drain impurity layer and its manufacturing method are commonly known, for example, disclosed in Non-Patent Document 1 by The above project to form the source of MOS transistor. The method of draining the impurity layer.

[Advanced technical literature] [Non-patent literature]

[Non-Patent Document 1] Kishino is just writing "Super LSI Materials. The Foundation of the Process" Ohmsha, Ltd., December 25, 1961, p. 11-12

However, the method of manufacturing the MOS transistor shown in Non-Patent Document 1 has the following disadvantages.

Since the polycrystalline silicon layer that is generally used as the gate electrode of the transistor is composed of an aggregate of single crystal grains, it is at the source. The ion implantation of the drain impurity penetrates the gate electrode formed by the polycrystalline silicon layer through the channel phenomenon of implanting the impurity through the gap between the crystal grains, and the channel area of the transistor of the silicon substrate under the gate electrode is also Inject impurities.

This is one of the important factors that determine the critical value of the transistor. The large deviation of the impurity concentration in the channel area becomes the main factor, which hinders the stability of the transistor performance.

Therefore, in the present invention, it is a problem to provide a method for manufacturing a MOS transistor that can prevent the channel phenomenon and stabilize the critical value of the transistor.

In order to solve the above problems, the present invention is directed to the pattern of polycrystalline silicon layer When the impurity layer is formed in self-alignment, the method described below is used.

(1) The patterned first photoresist layer used for the polycrystalline silicon layer is left, and impurities are ion implanted.

(2) The patterned first photoresist layer for the polycrystalline silicon layer is left, the second photoresist layer for the impurity layer is patterned, and impurities are ion implanted.

In the present invention, the first photoresist layer is left in the pattern of the polycrystalline silicon layer, and ion implantation for forming the impurity layer is performed, thereby having the effects described below.

(1) The channel phenomenon during ion implantation through the pattern of the polycrystalline silicon layer can be suppressed. For example, even if the gate electrode of the polycrystalline silicon layer is self-aligned, the source of the MOS transistor is formed by ion implantation. The drain impurity layer can also stabilize the critical value of the transistor because no impurity is injected into the channel area of the transistor.

(2) It is not necessary to remove the first photoresist layer on the pattern of the polycrystalline silicon layer before ion implantation. In the subsequent photoresist removal process, for example, the first photoresist layer is removed when the second photoresist layer is removed, Therefore, construction can be reduced.

1. 11‧‧‧ Silicon substrate

2. 12‧‧‧component separation insulating film

3. 13‧‧‧ Gate insulating film

4, 14‧‧‧ polycrystalline silicon layer

4-1, 4-2, 14-1, 14-2 ‧‧‧ gate electrode

4-3, 14-3‧‧‧Wiring made of polycrystalline silicon layer Resistance film

5, 15‧‧‧The first photoresist layer

6‧‧‧Resistant hardened layer

7, 9, 10, 17, 18 ‧‧‧ source Drain impurity layer

8, 16‧‧‧ 2nd photoresist layer

FIG. 1 is an engineering cross-sectional view showing a method of manufacturing a semiconductor device of the present invention.

2 is an engineering cross-sectional view showing a conventional method of manufacturing a semiconductor device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, as shown in FIG. 1( a ), for example, an element isolation insulating film 2 and a gate insulating film 3 are formed on a silicon substrate 1. Next, after the polycrystalline silicon layer 4 is formed on the entire surface of the silicon substrate 1, a photoresist is applied, and a patterned mask corresponding to the polycrystalline silicon layer 4 is exposed to form a first photoresist layer 5.

Next, the surface of the silicon substrate on which the first photoresist layer 5 is patterned is irradiated with UV (ultraviolet rays), and a resist hardened layer 6 having solvent resistance and exposure resistance is formed on the surface of the photoresist layer 5.

The UV irradiation at this time is a condition that the temperature is 170 to 190° C. and the UV exposure is in the range of 12 to 15 J/cm ² , and the resist hardened layer 6 having solvent resistance and exposure resistance can be formed for the purpose.

Generally, the photoresist is exposed. After developing and forming a pattern, baking is performed at a slightly high temperature, and the organic solvent in the photoresist is discharged to the outside. Although the process of adding a baking resist layer, such simple baking cannot be expected. The effect of solvent resistance or exposure resistance on the surface of the photoresist layer.

Next, as shown in FIG. 1(b), using the first photoresist layer 5 having the resist hardened layer 6 as a mask material, the polycrystalline silicon layer 4 is etched away to form the polycrystalline silicon layer 4 Gate electrodes 4-1, 4-2, resistance film 4-3 and wiring. As the gate electrode or the resistance film, in addition to the polycrystalline silicon layer, a single-layer film or a laminated film of a high-melting-point metal such as titanium, tantalum, or tungsten, such metal silicide, or the like can also be used.

Next, the first photoresist layer 5 having the resist hardening layer 6 may be left on the gate electrodes 4-1, 4-2, the resistance film 4-3, and the wiring, as required, Ion implantation is performed on the silicon substrate 1 in its entirety, and the gate electrodes 4-1 and 4-2 formed of the polycrystalline silicon layer are self-aligned to form the source electrode. Drain impurity layer 7. Since the gate electrode 4-1, 4-2, the resistive film 4-3, and the wiring are provided with the first photoresist layer 5 having the resist hardening layer 6, the channel phenomenon of impurity ions implanted by ions can be suppressed .

Next, as shown in FIG. 1(c), the second photoresist layer 8 is applied onto the first photoresist layer 5 having the resist hardened layer 6 and then patterned. Since the first photoresist layer 5 is patterned and the underlying polycrystalline silicon layer 4 is etched, the thickness of the first photoresist layer 5 plus the thickness of the polycrystalline silicon layer 4 is present on the surface of the silicon substrate Of difference. This step difference may hinder the spreading of the coating of the second photoresist layer 8 and cause uneven coating.

By making the amount of the dripping of the resist in the application of the resist in the formation of the second photoresist layer larger than that in the formation of the first photoresist layer, the above coating can be avoided Uneven distribution. In the formation of the third photoresist layer described later, the amount of the dropping of the resist during the application of the resist during the formation of the third photoresist layer is similar to that during the application of the resist during the formation of the first photoresist layer. The more dripping amount of the resist can avoid the above-mentioned uneven coating. In addition, even if the amount of the dripping of the resist forming the second photoresist layer is the same as the amount of the dripping of the resist forming the third photoresist layer. By using the technique of making the viscosity of the resist applied in the formation of the second and third photoresist layers higher than that of the resist applied in the formation of the first photoresist layer, Can avoid uneven coating.

Secondly, the source of the MOS transistor with the gate electrode 4-1 as an electrode, for example. The drain can be formed in the desired field by providing an opening in the second photoresist layer 8 and selectively forming it by ion implantation Source. Drain impurity layer 9. At the opening, the first photoresist layer 5 having the resist hardened layer 6 that is initially formed is exposed.

The opening of the second photoresist layer 8 for ion implantation of impurities is not only the source of the desired MOS transistor. In the drain field, even the gate electrode 4-1 is also formed. However, since the double resist method for forming the second photoresist layer 8 on the first photoresist layer 5 is used, the first The photoresist layer selectively shields the desired gate electrode. For the gate electrode made of the polycrystalline silicon layer, impurities are injected into the gate electrode only in the desired part, and the impurities are selectively and self-aligned. Ion Implantation. Since the first photoresist layer 5 having the resist hardened layer 6 is provided on the gate electrode 4-1, the channel phenomenon of impurity ions implanted by ions is suppressed.

This has the advantages shown below.

(1) No need to consider the source. The alignment of the drain impurity layer and the photoresist pattern processing of the gate electrode is deviated, and the miniaturization of this part of the transistor becomes possible.

(2) No need to source. The photoresist pattern for the drain impurity layer is finely processed to be more than necessary, and at least the source electrode can be more easily processed. Processing for drain impurity layer.

(3) Since there is a photoresist layer on the gate electrode made of the polycrystalline silicon layer, the channel phenomenon at the time of impurity ion implantation can be suppressed.

(4) Since it is not necessary to remove the first photoresist layer on the pattern of the polycrystalline silicon layer before ion implantation, the first photoresist can be removed in the subsequent photoresist removal process, for example, when the second photoresist layer is removed Layer, so it can cut down on engineering.

Furthermore, since the first photoresist layer 5 shown in FIG. 1(a) has a resist hardening layer 6, even if the second photoresist layer 8 is applied, the solvent will not be impregnated Through the first photoresist layer 5, the pattern of the first photoresist layer is not deformed.

In addition, when the second photoresist layer 8 needs to be reworked, the surface of the silicon substrate coated with the second photoresist layer or patterned may be fully exposed without using a photomask. Even if the second photoresist layer is patterned and the first photoresist layer 5 is exposed, because the resist hardened layer 6 has exposure resistance and solvent resistance, full exposure and the second photoresist for the subsequent The alkaline solvent treatment for removing the agent layer does not affect the first photoresist layer. As shown above, the gate electrode pattern for the polycrystalline silicon layer self-aligns to form the holding source. MOS transistor of drain impurity layer.

In addition, although the first photoresist layer 5 is not patterned, but the polysilicon layer 4 is etched and the UV-irradiated resist hardened layer 6 is formed, exposure resistance and solvent resistance can also be obtained The effect of the first photoresist layer is reduced by baking under general UV irradiation, so the first layer of the resist hardening layer 6 is formed on the inner side of the pattern of the etched polycrystalline silicon layer 4 1 In the photoresist layer 5, the part where the resist has receded is where the surface of the polycrystalline silicon layer will be exposed.

The exposed part of the surface of this polycrystalline silicon layer is the subsequent source. In ion implantation of drain impurities, only a polycrystalline silicon layer is used as a mask material. Due to the channel phenomenon of ion implantation mentioned as the aforementioned problem, the channel field of the transistor of the silicon substrate under the gate electrode is also Impurities are injected to widen the critical value deviation of the transistor. Moreover, if the degree is serious, the source electrode is also formed directly under the exposed portion of the surface of the polycrystalline silicon layer. The drain field incurs an obstacle to self-alignment of the gate electrode pattern to form the source. Drain impurity layer.

On the other hand, as described in the embodiment of the present invention, after the patterning of the first photoresist layer 5, UV irradiation is performed before the etching of the polycrystalline silicon layer 4, and if the resist hardened layer 6 is formed, the polycrystalline silicon layer The etching is performed using the retracted photoresist pattern as a mask, so that the entire upper surface of the gate electrode of the polycrystalline silicon layer after etching can be maintained with the first photoresist layer holding the resist hardening layer 6 The covered state becomes the source. A complete masking material for the implantation of drain impurity ions, so the source can be carried out perfectly. The prevention of the self-alignment of the gate electrode or the channel phenomenon by the drain impurity layer.

In addition, as shown in FIG. 1(d), if necessary, for example, for the MOS transistor using the gate electrode 4-2 as an electrode, the above-mentioned process of FIG. 1(c) is repeated in the desired field, thereby Form the source. The drain impurity layer 10 can form multiple types of MOS transistors. That is, changing the applied photoresist layer, openings, and impurities to repeat: after selectively removing the second photoresist layer, after applying the third photoresist layer on the first photoresist layer Patterning, a second opening is provided in a part of the third photoresist layer, the first photoresist layer is exposed to the second opening, and then the second impurity is ion implanted from the second opening to form a source. The drain impurity layer forms multiple types of MOS transistors.

When the process of FIG. 1(c) is repeated, the source formed as a double mask on the first photoresist layer on the polycrystalline silicon layer. The photoresist layer for the drain impurity layer is the source. If the ion implantation concentration of the drain impurity layer is 5×10 ¹⁴ atms/cm ² or less, even the wet method, that is, only the solvent for removing the photoresist can be removed, so as long as the first photoresist has the resist hardened layer After the solvent layer continues to be solvent-resistant, the impurity layer with the first photoresist layer left on the polycrystalline silicon layer can be subjected to photoresist layer formation and ion implantation treatment multiple times.

On the other hand, the first photoresist layer holding the resist hardened layer is subjected to an ashing process of a photoresist that is generally applied to the photoresist layer after high concentration implantation and the like. Although there is a resist hardened layer 6 in the first photoresist layer 5, since only the surface portion of the resist is used, the resist hardened layer 6 can be removed by ashing treatment. After the resist hardened layer 6 is removed, the A common photoresist removal solvent removes both the first photoresist layer and the photoresist layer formed as a double mask.

Of course, after removing the photoresist layer formed as a double mask, the first photoresist is subjected to ashing treatment, and there is no problem in removing the first photoresist by solvent treatment.

In addition, the source of the present invention. The drain impurity layer is not limited to a high-concentration N-type or P-type impurity layer, and is also included in the final form of the MOS transistor to form the source. Part of the drain, such as LDD (Lightly Doped Drain) or DDD (Double Diffused Drain), as the source. A pocket cloth implant or a ring cloth implant of a punch-through stopper.

Similarly, although the present invention cites the source of MOS transistors. The method for manufacturing the drain impurity layer is an example, but not limited to this. Of course, it can also be applied to a method for manufacturing an impurity layer formed by self-aligning the pattern of the polycrystalline silicon layer.

1‧‧‧Si substrate

2‧‧‧Component isolation insulating film

3‧‧‧Gate insulating film

4‧‧‧Polycrystalline silicon layer

4-1, 4-2‧‧‧ Gate electrode

4-3‧‧‧Wiring made of polycrystalline silicon layer Resistance film

5‧‧‧First photoresist layer

6‧‧‧Resistant hardened layer

7, 9, 10‧‧‧ source Drain impurity layer

8‧‧‧The second photoresist layer

Claims (11)

A method of manufacturing a semiconductor device, which is a method of manufacturing a semiconductor device in which an impurity layer is formed in a self-aligned pattern on a polycrystalline silicon layer on a semiconductor substrate, and is characterized by the following steps: forming polycrystalline silicon on a semiconductor substrate The process of the layer; the process of patterning after coating the first photoresist layer constituting the double mask on the polycrystalline silicon layer; the process of performing UV irradiation on the patterned first photoresist layer; The first photoresist layer after UV irradiation is used as a mask to etch the polycrystalline silicon layer to form a gate electrode and a resistive film made of the polycrystalline silicon layer; the first photoresist after the UV irradiation A step of applying a second photoresist layer on the agent layer and patterning, providing an opening in a part of the second photoresist layer to expose the first photoresist layer in the opening; and the opening The process of ion implantation of the first impurity. A method for manufacturing a semiconductor device as claimed in item 1 of the patent scope further includes: a process of removing the second photoresist layer following the process of ion implanting the first impurity; and a process of removing the second photoresist layer; on the first photoresist layer A process of applying and patterning a third photoresist layer, providing a second opening in a part of the third photoresist layer, and exposing the first photoresist layer to the second opening; and 2 The process of ion implantation of the second impurity in the opening. A method for manufacturing a semiconductor device as claimed in item 2 of the patent scope, wherein a solvent for removing the photoresist is used in the process of removing the second photoresist layer. A method for manufacturing a semiconductor device as claimed in item 1 of the patent scope, wherein the opening is formed at least in the field of the source and drain impurity layer formation of the MOS transistor. The method for manufacturing a semiconductor device as claimed in item 1 of the patent scope further includes: after the process of forming the gate electrode and the resistive film made of the polycrystalline silicon layer, the first light after the UV irradiation is left The resist layer is ion implanted over the entire semiconductor substrate, and the source electrode and the drain impurity layer are self-aligned for the gate electrode formed by the polycrystalline silicon layer. A method of manufacturing a semiconductor device as claimed in item 1 or 5 of the patent application, wherein after the process of patterning the first photoresist layer and before the process of etching the polycrystalline silicon layer, the patterning is performed The above-mentioned first photoresist layer is irradiated with UV. The method for manufacturing a semiconductor device as described in any one of claims 2 to 4, wherein after the process of patterning the first photoresist layer and before the process of etching the polycrystalline silicon layer To perform UV irradiation on the patterned first photoresist layer. The method for manufacturing a semiconductor device as described in any one of claims 1 to 5, wherein the amount of the resist dripping that forms the second photoresist layer is larger than the resistance that forms the first photoresist layer The amount of the agent dropped more. Half as described in any of items 2 to 4 of the patent application scope In the method of manufacturing a conductor device, the amount of dripping of the resist forming the third photoresist layer is larger than the amount of dripping of the resist forming the first photoresist layer. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the viscosity of the resist forming the second photoresist layer is higher than that of the resist forming the first photoresist layer The viscosity of the agent is higher. The method for manufacturing a semiconductor device according to any one of claims 2 to 4, wherein the viscosity of the resist forming the third photoresist layer is higher than that of the resist forming the first photoresist layer The viscosity of the agent is higher.

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