TWI681509B - Resistive random access memory and method for forming the same - Google Patents

Abstract

A method for forming a resistive random access memory device includes forming a layer stack, patterning the layer stack to form a plurality of stack structures, forming a protection layer along a sidewall of the plurality of stack structures, forming a first isolation structure between the plurality of stack structures, forming at least one recess in at least one stack structure to define a plurality of filament units, and forming a second isolation structure in the at least one recess. The layer stack includes a bottom electrode and a resistive switching layer on the bottom electrode.

Description

Resistance random access memory and its forming method

The present invention relates to semiconductor manufacturing technology, in particular to resistive random access memory and its forming method.

Resistive random access memory has low power consumption, low operating voltage, short write and erase time, long durability, long data retention time, non-destructive read operation, multi-state, simple manufacturing , And the advantages of expandable nature, thus becoming the emerging mainstream of non-volatile memory. The basic structure of a resistive random access memory includes a bottom electrode, a resistance conversion layer, and a metal-insulator-metal (MIM) stack of a top electrode. When a positive setting voltage is applied to the resistance random access memory, a conductive path can be formed in the resistance conversion layer to change from the high resistance state to the low resistance state. This process is called a SET operation. When a reverse reset voltage is applied to the resistive random access memory, the conductive path in the resistance conversion layer will be disconnected to change from the low resistance state to the high resistance state. This process is called reset (RESET) operating. In this way, the difference in the polarity of the applied voltage controls the level of the resistance, thereby achieving the purpose of information storage.

Due to the high degree of integration of modern memory chips, the structure of a single memory cell is small enough to be easily affected by cosmic rays and/or alpha particles, which may cause bit flips and cause data errors. Errors caused by these phenomena are called soft errors, so there is an urgent need for resistive random access memory The soft errors provide further improvement.

The embodiment of the invention provides a method for forming a resistive random access memory. The method includes forming a film layer stack, patterning the film layer stack to form a plurality of stack structures, forming a protective layer along the sidewalls of the stack structure, forming a first isolation structure between the stack structures, and forming at least one stack At least one groove is formed in the structure to define a plurality of physically separated electric wire units in the at least one stacked structure, and a second isolation structure is formed in the at least one groove. The above film layer stack includes a bottom electrode layer and a resistance conversion layer on the bottom electrode layer.

An embodiment of the present invention provides a resistive random access memory including a plurality of stacked structures, wherein the stacked structures are separated from each other by a first isolation structure. Each stack structure described above includes a bottom electrode, a plurality of electric wire units, and a protective layer. The plurality of electric wire units are disposed on the bottom electrode, and are physically separated from each other by at least one second isolation structure, and each electric wire unit includes a resistance conversion structure located on the bottom electrode. The protective layer is along the sidewall of the stacked structure.

The resistive random access memory according to the embodiments of the present invention can be applied to various types of semiconductor devices. The drawings are described in detail below.

10, 20‧‧‧ resistive random access memory

100‧‧‧ substrate

101‧‧‧Intermetallic dielectric layer

102, 108‧‧‧ conductive structure

104‧‧‧dielectric layer

106, 304‧‧‧ conductive layer

200‧‧‧Bottom electrode layer

200'‧‧‧Bottom electrode

202, 202'‧‧‧ resistance conversion layer

202"‧‧‧Resistance conversion structure

204, 204'‧‧‧ first barrier layer

204"‧‧‧The first barrier structure

206, 206'‧‧‧ oxygen exchange layer

206"‧‧‧oxygen exchange structure

208, 208'‧‧‧ second barrier layer

208"‧‧‧Second barrier structure

210, 210'‧‧‧ Top electrode layer

210A, 210B‧‧‧Top electrode

211、215‧‧‧Photoresist layer

212‧‧‧Protective layer

214‧‧‧Isolated structure

216‧‧‧groove

217‧‧‧Insulation

217A‧‧‧Notch

218‧‧‧Wire unit

220, 220’‧‧‧Second isolation junction Construct

222‧‧‧The third isolation structure

300‧‧‧Intermetallic dielectric layer

302‧‧‧Conductive contact

400‧‧‧Transistor

406‧‧‧Source/Drain

W1, W2‧‧‧Width

The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale It is for illustrative purposes only. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

FIGS. 1A-1I are schematic cross-sectional views of the resistive random access memory at different intermediate stages in accordance with some embodiments.

Figures 2A-2G are schematic cross-sectional views of a resistive random access memory production device at different intermediate stages according to other embodiments.

The following disclosure provides many different embodiments or examples to show the different features of the present disclosure. The following will disclose specific examples of components and arrangements in this specification to simplify the disclosure. Of course, these specific examples are not intended to limit this disclosure. For example, if the following summary of the description of this specification describes the formation of the first component on or above the second component, it means that it includes an embodiment where the formed first and second components are in direct contact, and also includes Additional components can be formed between the first and second components, and the first and second components are embodiments that are not in direct contact. In addition, various examples in this disclosure may use repeated element symbols. The purpose of these element symbols is to simplify and clarify, not to limit the relationship between various embodiments and/or the configurations.

Although the steps in some of the described embodiments are performed in a specific order, these steps may also be performed in other logical orders. In different embodiments, some of the described steps may be replaced or omitted, and some other operations may be performed before, during, and/or after the steps described in the embodiments of the present invention. The resistive random access memory in the embodiments of the present invention may incorporate other features. In different embodiments, some features may be replaced or omitted.

One transistor-one resistor (1 transistor-1 resistor, 1T1R) junction A structured resistive random access memory (resistive random access memory, RRAM) device has only one filament unit (ie, a filament transmission channel) in a single memory cell. The 1T1R structure is easy to generate soft error bits during the setting/resetting process after the wire is formed. Because the soft error bits are randomly generated and the probability of unpredictable occurrence, the current method mostly uses two transistors-two resistors (2T2R ) Structure, the 2T2R resistive random access memory has two wire units in a single memory unit, and the sensing method (sensing method) is combined with the combination mode or differential in the circuit design Differential mode to solve this problem. However, the size of the memory cell has also increased, and there are still soft errors.

The invention provides a resistive random access memory and a method for forming the same, in particular to a resistive random access memory having a plurality of electric wire units in a single memory unit of 1T1R structure. Since there are multiple electric wire units in a single memory unit, the number of bits generated by a single memory unit can be increased without increasing the size of the memory unit, thereby improving the probability of occurrence of soft error bits. For example, when using the sensing method to operate in the combined mode, even if a soft error bit occurs, other transmission channels are still reserved to reduce the probability of soft error bit generation.

FIGS. 1A-1I are schematic cross-sectional views of the resistive random access memory at different intermediate stages in accordance with some embodiments. Please refer to FIG. 1A to provide a substrate 100 first. The substrate 100 may be a semiconductor substrate or a silicon-on-insulator substrate. For example, the material of the semiconductor substrate may include doped or undoped semiconductor materials, such as silicon, germanium, gallium arsenide, silicon carbide, indium arsenide, or indium phosphide. In addition, the substrate 100 may be formed to have active elements Components and/or passive components. Active components may include transistors, diodes, etc., while passive components may include resistors, capacitors, inductors, etc. In some embodiments, the substrate 100 may include a memory control element (to be described in detail later in FIG. 1I). The memory control element includes an active control element (eg, transistor) and an interconnect structure (eg, Conductive layers, contacts, etc.).

As shown in FIG. 1A, an intermetal dielectric layer 101 is formed on the substrate 100. The inter-metal dielectric layer 101 may include or be an oxide (such as silicon oxide, silicon dioxide), nitride, or low-k dielectric material (for example, a material with a dielectric constant lower than silicon dioxide ), silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorine-doped silicate glass, organic silicate glass, SiOxCy , Carbon silicon material or a combination of the above. In one embodiment, the thickness of the intermetal dielectric layer 101 may be about 300 nm to about 400 nm. In addition, the inter-metal dielectric layer 101 is formed with a conductive structure 102 for connecting the resistive random access memory to the active control element and/or interconnect structure in the substrate 100. In one embodiment, the conductive structure 102 may include aluminum, copper, tungsten, or other suitable conductive materials.

With continued reference to FIG. 1A, next, a film layer stack is formed on the intermetal dielectric layer 101. Specifically, the formed film layer stack may include a bottom electrode layer 200, a resistive switching layer 202, a first barrier layer 204, an oxygen exchange layer 206, and a second resistor formed in sequence The barrier layer 208 and the top electrode layer 210.

In an embodiment, the bottom electrode layer 200 may include tungsten, platinum, aluminum, titanium, titanium nitride, or a combination of the foregoing, and the thickness may be about 25 nm to about 35 nm. In one embodiment, the resistance conversion layer 202 may include a transition metal oxide, such as hafnium oxide, titanium oxide, tungsten oxide, tantalum oxide, zirconium oxide, or a combination of the foregoing, and the thickness may be about 3 nm to 10 nm. In an embodiment, the first barrier layer 204 and the second barrier layer 208 may include aluminum oxide (Al ₂ O ₃ ) or silicon nitride (SiN ₄ ), and the thickness may be about 0.4 nm to 1 nm. In one embodiment, the first barrier layer 204 is thicker than the second barrier layer 208 described above. In one embodiment, the oxygen exchange layer 206 may include aluminum, titanium, or a combination of the foregoing, and the thickness may be approximately 20 nm to 40 nm. In one embodiment, the bottom electrode layer 200, the resistance conversion layer 202, the first barrier layer 204, and the oxygen exchange for the film stack can be sequentially formed by electron beam evaporation, sputtering, or physical vapor deposition Layer 206 and second barrier layer 208.

Referring to FIG. 1B, a patterning process is performed on the film stack to form stack structures corresponding to the conductive structures 102, respectively. In detail, a patterned photoresist layer 211 exposing a portion of the top surface of the film layer stack may be formed on the film layer stack. Next, a patterning process is performed on the film stack by patterning the photoresist layer 211 to sequentially pattern the bottom electrode layer 200, the resistance conversion layer 202, the first barrier layer 204, the oxygen exchange layer 206, and the second resistance The barrier layer 208 and the top electrode layer 210 form a plurality of stacked structures on the intermetal dielectric layer 101. Each stacked structure is a memory unit. Each stack structure includes a bottom electrode 200', a resistance conversion layer 202', a first barrier layer 204', an oxygen exchange layer 206', and a second barrier layer 208' sequentially stacked on the intermetal dielectric layer 101 And the top electrode layer 210'. Then, the patterned photoresist layer 211 can be removed through processes such as ashing or wet stripping.

In one embodiment, a photoresist layer can be formed on the above film layer stack by, for example, a spin coating process, and the photoresist can be patterned by exposing the photoresist using an appropriate photomask. The exposed or unexposed portions of the photoresist can then be removed, depending on whether a positive or negative photoresist is used to form the patterned photoresist layer 211.

Next, referring to FIG. 1C, a protective layer 212 is compliantly formed along the sidewalls of the above-mentioned stacked structure and on the top surface of the stacked structure, and a first isolation structure 214 is formed between the stacked structures. In some embodiments, the method of forming the first isolation structure 214 is, for example, first blanket forming the above-mentioned insulating material on the substrate 100, and then using a planarization process on the above-mentioned insulating material until the protective layer 212 on the stacked structure is exposed, In order to form the first isolation structure 214 (as shown in FIG. 1C) between the stacked structures. In other embodiments, the above planarization process may be performed until the top surface of the stacked structure (ie, the patterned top electrode layer 210') is exposed, so that the top surface of the stacked structure is flush with the insulating material (not shown). In some embodiments, the above planarization process may include a chemical mechanical polishing process or an etch back process. The protective layer 212 and the first isolation structure 214 include different materials. The difference in energy band between the two prevents electron migration, thereby preventing adjacent memory cells from interfering with each other to ensure the functionality of the resistance random access memory . The protective layer 212 may include a metal oxide, such as aluminum oxide (Al ₂ O ₃ ) or silicon nitride (SiN ₄ ), and the thickness may be about 0.4 nm to 1 nm. The protective layer 212 may be formed by an atomic layer deposition process, a chemical vapor deposition process, or a combination thereof. The first isolation structure 214 may include or be an insulating material, such as oxide (eg, silicon oxide), nitride, or a combination thereof. The above insulating materials can be filled in the stack by, for example, high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (flowable CVD, FCVD), or any suitable deposition technique Between structures.

As shown in FIG. 1D, a patterned photoresist layer 215 is formed on the stack structure. In some embodiments, the light used to form the patterned photoresist layer 215 The mask may be the same as the mask used to form the patterned photoresist layer 211 in FIG. 1B without using an additional mask. For example, different types of photoresists are used to form a patterned photoresist layer 215 having a complementary pattern inverse to the patterned photoresist layer 211 in FIG. 1B. In some embodiments, the patterned photoresist layer 211 is a positive photoresist, and the patterned photoresist layer 215 is a negative photoresist. In other embodiments, an additional photomask can also be used to form the patterned photoresist layer 215.

Please continue to refer to FIG. 1D, and then form an insulating layer 217 on the patterned photoresist layer 215 by a suitable deposition process, such as chemical vapor deposition or atomic layer deposition. In some embodiments, the insulating layer 217 may include or be oxide (eg, silicon oxide), nitride, or a combination of the foregoing. As shown in FIG. 1D, the insulating layer 217 has a plurality of notches 217A. The bottom of the notch 217A has a width W1, and the width W1 ranges from about 1/20 to 3/20 of the width W2 of the top surface of the stacked structure.

Referring to FIG. 1E, the patterned photoresist layer 215 and the insulating layer 217 are used as an etching mask to etch the stack structure to form the groove 216. The groove 216 passes through the stacked structure to the bottom electrode 200' and exposes a part of the bottom electrode 200'. The groove 216 defines two physically separated electric wire units 218 and a top electrode 210A on each electric wire unit 218 in the above-mentioned stacked structure. As shown in FIG. 1E, the wire unit 218 includes a resistance conversion structure 202", a first barrier structure 204", an oxygen exchange structure 206", and a second barrier structure 208". The wire unit 218 is a wire transmission channel. The oxygen exchange structure 206" may assist the resistance conversion structure 202" to form an electric wire. Specifically, after the electric wire is formed in the resistance conversion structure 202", free oxygen ions may be stored in the oxygen exchange structure 206". In addition, the first and second barrier structures 204" and 208" can help confine free oxygen ions to the oxygen exchange structure 206" to allow more stable wire shapes It is built into the wire unit 218 and enables the resistance random access memory to have a better wire reproducibility. In some embodiments, the step of etching the stacked structure may include any suitable anisotropic dry etching process, such as reactive ion etching, neutral beam etching (NBE), or a combination thereof. Next, the patterned photoresist layer 215 and the insulating layer 217 are removed. For example, the patterned photoresist layer 215 may be removed using, for example, ashing or wet stripping processes. For example, the insulating layer 217 can be formed using, for example, a wet stripping process or a suitable etching process. In some embodiments, the width of the groove 216 is about 1/20 to 3/20 of the width W2 of the stacked structure.

Although FIG. 1E shows that each stacked structure has one groove 216, in other embodiments, more than two grooves 216 may be formed in each stacked structure. In other words, more than three wire units 218 can be defined in each stack structure. For example, two grooves 216 may be formed in each stacked structure to form three wire units 218.

As shown in FIGS. 1F-1 and 1F-2, a second isolation structure 220 is formed in the groove 216 and an intermetal dielectric layer 300 is formed on the above-mentioned stacked structure. In some embodiments, the second isolation structure 220 may include or be an insulating material, such as oxide (eg, silicon oxide), nitride, or a combination thereof. In some embodiments, the inter-metal dielectric layer 300 may include oxides (eg silicon oxide, silicon dioxide), nitrides, and low dielectric constant dielectric materials (eg, materials having a dielectric constant lower than silicon dioxide ), silicon oxynitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, fluorine-doped silicate glass, organic silicate glass, SiO _x C _y , carbon-silicon material, the above compound, the above compound, or a combination of the above. In some embodiments, the thickness of the intermetal dielectric layer 300 may be about 200 nm to about 400 nm.

In some embodiments, as shown in FIG. 1F-1, the second isolation structure 220 and the inter-metal dielectric layer 300 may be formed in different steps. In this embodiment, the above-mentioned insulating material can be filled into the groove 216 by any suitable deposition process (such as HDP-CVD or FCVD), and the above-mentioned stacked structure can be covered with excess insulating material. Then, a planarization process (for example, a chemical mechanical polishing process or an etch-back process) is performed on the above-mentioned insulating materials to remove excess insulating material on the stacked structure, so that the top surface of the stacked structure is flush with the insulating material, so that the concave The second isolation structure 220 is formed in the groove 216. Then, any suitable deposition process may be used to form the inter-metal dielectric layer 300 over the stack structure and the second isolation structure 220.

In other embodiments, as shown in FIG. 1F-2, the second isolation structure 220' and the inter-metal dielectric layer 300 may be formed in the same deposition process. In this embodiment, the above-mentioned insulating material can be deposited at least on the stacked structure by any suitable deposition process to form the intermetal dielectric layer 300 on the stacked structure. Compared with the deposition process described in relation to FIG. 1F-1, a deposition process and/or parameters with high trench filling capacity may not be required, so the above insulating material may not be filled in the groove 216, or may only partially fill the recess The groove 216 to form a second isolation structure 220' including an air gap, as shown in FIG. 1F-2. It should be noted that although the second isolation structure 220 is completely filled in the structure shown in FIG. 1F-1, the second isolation structure 220 including an air gap may also be formed during the manufacturing process.

Referring to FIG. 1G, a conductive contact 302 corresponding to each top electrode 210A is formed through the intermetal dielectric layer 300 and the protective layer 212. Specifically, it can be formed on the intermetal dielectric layer 300 and the protective layer 212 by a lithography and etching process An opening corresponding to and exposing each top electrode 210A is formed in. Next, a liner layer (for example, a diffusion barrier layer, an adhesion layer, or a similar film layer) and a conductive material are formed in the opening. The liner layer may include titanium, titanium nitride, tantalum, and tantalum nitride. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel. Then, a planarization process such as chemical mechanical polishing may be performed to remove the liner layer and the conductive material on the intermetal dielectric layer 300, and form a conductive contact 302 in the opening, as shown in FIG. 1G. In other embodiments, the conductive contact 302 can also be formed using, for example, a damascene process.

Next, referring to FIG. 1H, a plurality of conductive layers 304 are formed on the intermetal dielectric layer 300. In some embodiments, the conductive layer 304 may be formed using a damascene process or a dual damascene process. The conductive layer 304 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or similar materials.

FIG. 11I illustrates an example of a resistive random access memory 10 including a control element according to an embodiment of the invention. As shown in FIG. 1I, in addition to the structure made in 1H, the resistive random access memory 10 further has a transistor 400 formed on the substrate 100, and source/drain regions on both sides of the transistor 400 406, a dielectric layer 104 between the substrate 100 and the intermetal dielectric layer 101, a conductive layer 106 formed in the dielectric layer 104 to electrically connect the conductive structure 102 to the source/drain region 406, and conductive Structure 108.

In the embodiment shown in FIGS. 1A-1I, the resistive random access memory includes a plurality of memory cells, wherein the memory cells are separated from each other by a first isolation structure 214. Each memory cell includes a bottom electrode 200', a plurality of wire units 218 disposed on the bottom electrode 200', a top electrode 210A formed on each wire unit 218, a second isolation structure 220, and a bottom electrode 200', a protective layer 212 formed on the side walls of the wire unit 218 and the top electrode 210A on the same plane. The material of the first isolation structure 214 and the material of the protective layer 212 are different materials. The difference in energy bands between the two can prevent electron migration, thereby preventing adjacent memory cells from interfering with each other to ensure resistive random access memory Functionality of the body.

The wire units are physically separated from each other by the second isolation structure 220. Each wire unit includes a resistance conversion structure 202' on the bottom electrode 200', a first barrier structure 204' on the resistance conversion structure 202', and an oxygen exchange structure 206' on the first barrier structure 204' And a second barrier structure 208' located on the oxygen exchange structure 206'. Since there are physically separated electric wire units in each memory unit, multiple bits can be formed without increasing the volume of the memory unit. In this way, when combining the combined mode/differential mode with the sensing method, the occurrence rate of soft error bits can be reduced.

Figures 2A-2G are schematic cross-sectional views of the resistive random access memory at different intermediate stages of production according to other embodiments. This embodiment is similar to the previous embodiment of FIGS. 1A-1I except that in this embodiment, multiple wire units in a single memory unit share a top electrode. Details of this embodiment that are similar to the previously described embodiments will not be repeated here.

Please refer to FIG. 2A to provide the substrate 100 first. Next, the intermetal dielectric layer 101 is formed on the substrate 100. The inter-metal dielectric layer 101 includes a conductive structure 102 for connecting the resistive random access memory to the active control element and/or interconnect structure in the substrate 100. Next, a film layer stack is formed on the intermetal dielectric layer 101. The film layer stack may include a bottom electrode layer 200, a resistance conversion layer 202, a first barrier layer 204, an oxygen exchange layer 206, and Second barrier layer 208. The difference between the embodiment shown in FIG. 2A and the previous embodiment shown in FIG. 1A is that the top electrode layer 210 is not included in the above film layer stack.

Next, the same or similar processes as described above with respect to FIGS. 1B to 1E are performed to form the structure as shown in FIG. 2B. Please refer to FIG. 2B. As mentioned previously, the groove 216 defines two physically separated wire units 218 on the bottom electrode 200'. The wire unit 218 includes a resistance conversion structure 202" and a first barrier Structure 204", oxygen exchange structure 206", and second barrier structure 208". As shown in FIG. 2B, the protective layer 212 is along the coplanar side walls of the bottom electrode 200', the resistance conversion structure 202", the first barrier structure 204", the oxygen exchange structure 206", and the second barrier structure 208", And is located on the top surface of the second barrier structure 208". In another embodiment, the protective layer 212 only runs along the bottom electrode 200', the resistance conversion structure 202", the first barrier structure 204", and the oxygen exchange structure 206 ", and the second barrier structure 208" are coplanar side walls, but are not located on the top surface of the second barrier structure 208" (not shown).

Next, referring to FIG. 2C, a second isolation structure 220 is formed in the groove 216, and a top electrode layer 210 is formed on the wire unit 218. The process and materials for forming the top electrode layer 210A are similar to those in FIG. 1A, and will not be described here. The processes and materials for forming the second isolation structure are similar to those in FIGS. 1F-1 and 1F-2, and are not repeated here. Similar to those mentioned in FIGS. 1F-1 and 1F-2, the second isolation structure 220 may be an insulating material (FIG. 2C), or may include an air gap (not shown). For convenience, in the subsequent 2D-2G diagrams, only the second isolation structure 220 is depicted as completely filled.

Next, referring to FIG. 2D, a patterning process is performed on the top electrode layer 210 using a suitable patterned photoresist (not shown) to form a plurality of top electrodes 210B. As shown in FIG. 2D, each top electrode 210B corresponds to a bottom electrode 200', and cover two electric wire units 218 at the same time.

It is worth mentioning that the photomask used here can be the same as the photomask used in the previous steps of forming a plurality of stacked structures without using an additional mask. In other embodiments, when a plurality of second isolation structures 220 and a plurality of electric wire units 218 are formed on each stacked structure, the top electrode 210B simultaneously covers the plurality of electric wire units 218 on the stacked structure.

Referring to FIG. 2E, a third isolation structure 222 is formed between the top electrodes 210B and an intermetal dielectric layer 300 is formed on the top electrode 210B. In some embodiments, the third isolation structure 222 may include an insulating material, such as oxide (eg, silicon oxide), nitride, or a combination thereof. The processes and materials for forming the inter-metal dielectric layer 300 are similar to those in FIGS. 1F-1 and 1F-2, and will not be repeated here.

In some embodiments, the third isolation structure 222 and the inter-metal dielectric layer 300 may be formed in different steps. In this embodiment, the above-mentioned insulating material can be filled between the top electrodes 210B by a suitable deposition process (such as HDP-CVD or FCVD), and the top electrode 210B is covered with excess insulating material. Next, a planarization process (such as a chemical mechanical polishing process or an etch-back process) is performed to remove excess insulating material on the top electrode 210B, so that the top surface of the top electrode 210B is flush with the insulating material so that the top electrode 210B The third isolation structure 222 is formed. Next, any suitable deposition process may be used to form the inter-metal dielectric layer 300 over the top electrode 210B.

In other embodiments, the third isolation structure 222 and the inter-metal dielectric layer 300 may be formed in the same step. In this embodiment, the above insulating material can be blanket formed on the substrate 100 to serve as the third isolation structure 222 and the inter-metal dielectric layer 300.

Referring to FIG. 2F, a conductive contact 302 corresponding to each top electrode 210B is formed through the intermetal dielectric layer 300. Next, a plurality of conductive layers 304 are formed on the intermetal dielectric layer 300. The processes and materials for forming the conductive contact 302 and the conductive layer 304 are similar to those in FIGS. 1G and 1H, and will not be repeated here.

FIG. 2G is an example of a resistive random access memory 20 including a control element according to another embodiment of the invention. In this embodiment, except that a plurality of electric wire units in a single memory unit share a top electrode, the other parts are similar to the embodiment of FIG. 1I, and will not be repeated here.

In the embodiment shown in FIGS. 2A-2G, the resistive random access memory includes a plurality of memory cells, wherein the memory cells are separated from each other by the first isolation structure 214, respectively. Each memory cell includes a bottom electrode 200', a plurality of wire units 218 disposed on the bottom electrode 200', a top electrode 210B covering the plurality of wire units 218, and along the bottom electrode 200' and the wire unit 218 The protective layer 212 is formed on the side walls of the coplanar surface. The material of the first isolation structure 214 and the material of the protective layer 212 are different materials. The difference in energy bands between the two can prevent electron migration, thereby preventing adjacent memory cells from interfering with each other to ensure resistive random access memory Functionality of the body.

The electric wire units 218 are physically separated from each other by at least one second isolation structure 220. Each wire unit includes a resistance conversion structure 202' on the bottom electrode 200', a first barrier structure 204' on the resistance conversion structure 202', and an oxygen exchange structure 206' on the first barrier structure 204' And a second barrier structure 208' located on the oxygen exchange structure 206'. Each memory cell has physically separated electric wire cells, which can form multiple bits without increasing the volume of the memory cell. In this way, combining the combined mode/differential mode with the sensing method In the formula, the incidence of soft error bits can be reduced.

Although the embodiments shown in FIGS. 1A-1I and FIGS. 2A-2G show that a plurality of wire units 218 share a bottom electrode, each wire unit 218 may also have an independent bottom electrode. In other words, the plurality of electric wire units 218 may have an independent top electrode/common bottom electrode (as in FIG. 1I), a common top electrode/common bottom electrode (as in FIG. 2G), and a common top electrode/independent bottom electrode (not shown) Shown), or independent top electrode/independent bottom electrode (not shown).

The resistive random access memory shown in FIGS. 1I and 2G can be used to solve the soft error bit problem of the resistive random access memory of 1T1R structure. Forming multiple wire units in a single memory unit can form multiple bits without increasing the volume of the memory unit. In this way, when combining the combined mode/differential mode with the sensing method, the occurrence rate of soft error bits can be reduced. In addition, the protective layer formed on the side wall of the memory cell can form an energy band difference with the isolation structure between the memory cells, thereby preventing adjacent memory cells from interfering with each other and ensuring the functionality of the resistance random access memory.

The above outlines the features of several embodiments of the present disclosure, so that those with ordinary knowledge in the art can more easily understand the present disclosure. Anyone with ordinary knowledge in the technical field should understand that this specification can be easily used as a basis for changes or design of other structures or processes to perform the same purposes and/or obtain the same advantages as the embodiments of the present disclosure. Any person with ordinary knowledge in the technical field can also understand that the structure or process equivalent to the above does not deviate from the spirit and scope of the disclosure, and can be changed or replaced without departing from the spirit and scope of the disclosure With retouch.

10‧‧‧Resistance random access memory

100‧‧‧ substrate

101‧‧‧Intermetallic dielectric layer

102‧‧‧Conductive structure

104‧‧‧dielectric layer

106, 304‧‧‧ conductive layer

108‧‧‧Conductive structure

200'‧‧‧Bottom electrode

202"‧‧‧Resistance conversion structure

204"‧‧‧The first barrier structure

206"‧‧‧oxygen exchange structure

208"‧‧‧Second barrier structure

210A‧‧‧Top electrode

212‧‧‧Protective layer

214‧‧‧Isolated structure

218‧‧‧Wire unit

220‧‧‧Second isolation structure

300‧‧‧Intermetallic dielectric layer

302‧‧‧Conductive contact

400‧‧‧Transistor

406‧‧‧Source/Drain

Claims (20)

A method for forming a resistive random access memory includes: forming a film layer stack, wherein the film layer stack includes: a bottom electrode layer; and a resistance conversion layer on the bottom electrode layer; patterning the film layer Stacking to form a plurality of stacked structures; forming a protective layer along the sidewalls of the stacked structures; forming a first isolation structure between the stacked structures; forming at least one groove in at least one stacked structure to A plurality of physically separated filament units are defined in the at least one stacked structure; and a second isolation structure is formed in the at least one groove. The method for forming a resistive random access memory as described in item 1 of the patent application scope, wherein the film layer stack further includes: a first barrier layer on the resistance conversion layer; and an oxygen exchange layer on the On the first barrier layer; and a second barrier layer on the oxygen exchange layer. The method for forming a resistive random access memory as described in item 1 of the patent application scope, before forming the film layer stack, further includes forming a plurality of conductive layers, each conductive layer is electrically connected to the stack structures One. The method for forming a resistive random access memory as described in item 3 of the patent application scope, before forming the conductive layers, further includes forming a plurality of transistors, each of the transistors One of the stacked structures is electrically connected. Resistive random access memory as described in item 2 of patent scope Forming method, wherein the film layer stack further includes a top electrode layer located on the second barrier layer, and wherein the step of forming the at least one groove further includes forming a plurality of top electrodes located on each electrode On the wire unit. The method for forming a resistive random access memory as described in item 5 of the patent application scope, wherein the top electrodes are physically separated from each other. The method for forming a resistive random access memory as described in item 1 of the scope of the patent application further includes: after forming the at least one groove, forming a top electrode structure on the stacked structures respectively. The method for forming a resistive random access memory as described in item 1 of the patent scope, wherein the second isolation structure includes an air gap. The method for forming a resistive random access memory as described in item 1 of the patent application scope, wherein the material of the first isolation structure and the material of the protective layer are different materials. The method for forming a resistive random access memory as described in item 1 of the patent scope, wherein the protective layer includes aluminum oxide or silicon nitride. The method for forming a resistive random access memory as described in item 1 of the patent scope, wherein the resistance conversion layer includes hafnium oxide, titanium oxide, tungsten oxide, tantalum oxide, zirconium oxide, or a combination of the foregoing. The method for forming a resistive random access memory as described in item 1 of the patent scope, wherein the oxygen conversion layer includes aluminum, titanium, or a combination of the foregoing. A resistive random access memory includes a plurality of stacked structures, wherein the stacked structures are separated from each other by a first isolation structure, and each of the stacked structures includes: A bottom electrode; and a plurality of electric wire units, disposed on the bottom electrode, and physically separated from each other by at least a second isolation structure, and wherein each electric wire unit includes a resistance conversion structure located on the bottom electrode ; And a protective layer formed on the side wall of the bottom electrode and each of the wire unit coplanar. The resistance random access memory as described in item 13 of the patent application scope, wherein the wire unit further includes: a first barrier structure located on the resistance conversion structure; and an oxygen exchange structure located on the first resistance On the barrier structure; and a second barrier structure on the oxygen exchange structure. The resistance random access memory as described in item 13 of the patent application scope further includes a plurality of conductive layers, and each conductive layer is electrically connected to one of the stacked structures. The resistance random access memory as described in item 15 of the patent application scope further includes a plurality of transistors, each transistor is electrically connected to one of the stacked structures through each conductive layer. The resistive random access memory as described in item 13 of the patent application scope, wherein each stacked structure further includes a plurality of top electrodes respectively located on the wire units. The resistive random access memory as described in item 13 of the patent application scope, wherein each stacked structure further includes a top electrode located on the wire units. Resistive random access memory as described in item 13 of patent scope The second isolation structure includes an air gap. The resistive random access memory as described in item 13 of the patent application scope, wherein the material of the first isolation structure and the material of the protective layer are different materials.

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