KR20070060346A - Method of manufacturing semiconductor device - Google Patents

Abstract

The present invention discloses a method for manufacturing a semiconductor device. The disclosed method comprises the steps of providing a semiconductor substrate partitioned into a cell region and a peripheral circuit region and having a first interlayer dielectric film having contact holes for bit lines in the respective regions, and on the first interlayer dielectric film. Forming a bit line including a stacked layer of a metal film and a hard mask film to fill a bit line contact hole, and forming a mask pattern covering a cell region on the first interlayer insulating film on which the bit line is formed; Etching the hard mask layer of the peripheral circuit region using the mask pattern as an etch barrier, removing the mask pattern, and covering the bit line of the cell region and the bit line from which the hard mask layer of the peripheral circuit region is removed. Forming a second interlayer insulating film on the first interlayer insulating film.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1G are cross-sectional views of processes for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

100 semiconductor substrate 101 device isolation film

102 gate 103 gate spacer

104: junction region 105: insulating film

106: landing plug 107: first interlayer insulating film

108: barrier film 108a: etched barrier film

109: tungsten film 109a: etched tungsten film

110: hard mask film 110a: hard mask pattern

111: second interlayer insulating film 112: contact plug for storage node

113: third interlayer insulating film 114: fourth interlayer insulating film

H: Bit line contact hole BL1, BL2, BL2 ': Bit line

CH: Capacitor hole SN: Storage electrode

DL: Dielectric Film PN: Plate Electrode

CP: Capacitor MH: Contact hole for metal wiring

MC: Contact Plug for Metal Wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to improve a buried property of an interlayer insulating layer formed to cover a bit line in a peripheral circuit area, and to further improve the embedding of a bit line when wiring is in contact with the bit line. It relates to a method for manufacturing a semiconductor device that can improve the not open problem.

As is well known, aluminum and tungsten, which are excellent in electrical conductivity, are mainly used as wiring materials for semiconductor devices such as DRAM. Among them, tungsten has a slightly lower electrical conductivity than aluminum, but has excellent thermal stability and excellent buried characteristics, so that tungsten has been widely used as a bit line material in a cell region. The bit line is formed to be in contact with the junction region of the cell region, and supplies a current through the channel to store the charge in the capacitor, or amplifies the difference in the amount of charge between the capacitors so that the charge stored in the capacitor can be converted into data. / A).

In addition, the tungsten serves to electrically control the cell region and is also used as a wiring material in a peripheral circuit region including an amplifier and a sub wordline (SWD). The junction region is formed to be in contact with the gate as well. Here, the tungsten wiring of the peripheral circuit region is different from the bit line of the cell region. However, since the tungsten wire is formed of the same material at the same stage as the bit line of the cell region, it is called a bit line.

Hereinafter, a manufacturing method of a conventional semiconductor device including a bit line forming method using tungsten will be briefly described.

The bit line of the semiconductor device is formed to be in individual contact with the lower structure of the cell region and the peripheral circuit region. The bit line of the semiconductor device is generally composed of a laminated film of a diffusion barrier film such as a Ti / TiN film and a hard mask film made of a tungsten film and a nitride film. Here, the hard mask layer is an etch mask layer for etching the tungsten layer, and also serves to protect the tungsten layer of the bit line when forming the contact plug for the storage node in the cell region.

After forming a bit line composed of the diffusion barrier film, the tungsten film and the hard mask film, a layer insulating film made of an oxide film is formed to cover the bit lines. In the cell region, a contact plug for a storage node is formed in the interlayer insulating film, and then a capacitor contacted with the contact plug for the storage node is formed. Meanwhile, in the peripheral circuit region, after forming another interlayer insulating layer on the interlayer insulating layer, a metal contact plug for contacting the bit line is formed in the interlayer insulating layers, and then a metal wiring contacting the contact plug for the metal wiring. To form.

Subsequently, subsequent steps are performed in order to complete the manufacturing process of the semiconductor device.

However, as the design rule of the semiconductor device is drastically reduced to 100 nm or less, the gap-fill gap of the interlayer insulating film formed to cover the bit lines in the peripheral circuit region by decreasing the interval between the bit lines in the peripheral circuit region. (fill) problem. The reason for this is explained in more detail as follows.

In the highly integrated device having the line width of the word line of 100 nm or less, the interval between the bit lines in the peripheral circuit region is designed to be equal to or slightly larger than the interval between the bit lines in the cell region, but in the case of the bit lines in the peripheral circuit region, The final CD (critical dimension) becomes larger than the original designed CD through the lithography process of exposure and etching. Therefore, filling the space between the bit lines in the peripheral circuit area becomes more difficult than filling the space between the bit lines in the cell area.

For the above reasons, when the buried characteristic of the interlayer insulating film formed to fill the inter-bit line space in the peripheral circuit region including the amplifying element and the sub word line becomes poor, the contact plugs for metal wiring formed in the interlayer insulating film are subsequently formed. A bridge phenomenon may occur, thereby reducing the reliability of the metallization and the manufacturing yield of the device.

In addition, in the above-described conventional technology, when forming a contact hole exposing a tungsten film of a bit line to form a contact plug for metal wiring in the peripheral circuit region, an interlayer insulating film made of oxide material and a hard mask film made of nitride film are sequentially etched. In this case, since the contact hole is minute and the nitride film is not easily etched, and it is difficult to completely remove the hard mask layer, a problem may occur that the contact hole is not open.

Accordingly, the present invention has been made to solve the above-mentioned general problems, and improves the buried characteristics of the interlayer insulating film formed so as to cover the bit line in the peripheral circuit area and at the time of forming the wiring contacting the bit line. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve a problem of not open of a bit line.

The semiconductor device manufacturing method of the present invention for achieving the above object is divided into a cell region and a peripheral circuit region, and provides a semiconductor substrate having a first interlayer insulating film having a contact hole for the bit line in each region; Doing; Forming a bit line formed of a stacked layer of a metal film and a hard mask film to fill a bit line contact hole on the first interlayer insulating film; Forming a mask pattern covering a cell region on the first interlayer insulating layer on which the bit lines are formed; Etching the hard mask layer of the peripheral circuit area by using the mask pattern as an etch barrier; Removing the mask pattern; And forming a second interlayer dielectric layer on the first interlayer dielectric layer so as to cover the bit line of the cell region and the bit line from which the hard mask layer of the peripheral circuit region is removed.

In addition, after the forming of the second interlayer insulating layer, the method may further include forming a contact hole for metal wiring to expose the bit line by etching the second interlayer insulating layer in the peripheral circuit region.

(Example)

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1A to 1G are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1A, a semiconductor substrate 100 is provided, which is divided into a cell region C and a peripheral circuit region P, and a trench type device isolation layer 101 is formed in the substrate 100 of each region.

Next, a gate 102 and a gate spacer 103 are formed on the substrate 100, and a junction region 104 is formed in the substrate 100 on both sides of the gate 102 including the gate spacer 103. do. Next, an insulating film 105 and a landing plug 106 about the height of the gate 102 are formed on the substrate 100 including the junction region 104 between the gate 102 including the gate spacer 103. do.

Here, the insulating film 105 and the landing plug 106 is formed at a height lower than the height of the gate 102 as shown, which is higher than the gate hard mask film formed at the upper end of the gate 102. This is because the etching speed of the 106 is fast, and this phenomenon is called dishing.

In the meantime, the gate in the cell region C is covered by the insulating film 105 and the landing plug 106 and is not shown in the drawing.

Referring to FIG. 1B, a first interlayer insulating film 107 is formed by planarizing the surface of the substrate through chemical mechnical polishing (CMP) to cover lower structures including the gate 102 and the landing plug 106. After forming, the first interlayer insulating layer 107 and a portion of the lower structure are etched to form bit line contact holes H in the cell region C and the peripheral circuit region P. Referring to FIG.

Then, a barrier film 108 made of a metal material such as a Ti / TiN film is formed on the surface of the bit line contact hole H and the first interlayer insulating film 107, and then the contact hole for the bit line ( The tungsten film 109 and the hard mask film 110 made of a nitride film are sequentially formed on the barrier film 108 to fill H).

Referring to FIG. 1C, a photoresist pattern (not shown) defining a bit line formation region is formed on the hard mask layer 110, and the hard mask layer is etched using the photoresist pattern (not shown) as an etching mask. The hard mask pattern 110a is formed. Then, the photoresist pattern (not shown) is removed.

Next, using the hard mask pattern 110a as an etch barrier, the tungsten film and the barrier film below are sequentially etched to sequentially etch the barrier film 108a etched in each of the cell region C and the peripheral circuit region P. Bit lines BL1 and BL2 formed of a laminated film of the etched tungsten film 109a and the hard mask pattern 110a are formed. Reference numeral BL1 denotes a bit line of the cell region C, and BL2 denotes a bit line of the peripheral circuit region, respectively.

Referring to FIG. 1D, a mask pattern M made of a photosensitive film material covering the cell region C is formed on the first interlayer insulating layer 107 on which the bit lines BL1 and BL2 are formed.

Referring to FIG. 1E, the hard mask pattern 110a of the peripheral circuit region P is selectively etched and removed using the mask pattern M as an etch barrier.

The etching of the hard mask pattern 110a may be performed by a dry etching process using a mixed gas of CF4, CHF3, O2 and Ar as an etching gas, or using a cleaning solution for removing a nitride film having a high etching selectivity for the nitride film. It is performed by a wet etching process.

Referring to FIG. 1F, in the state where the mask pattern is removed, although not shown, the bit line BL2 ′ in which the bit line BL1 of the cell region C and the hard mask pattern 110a of the peripheral circuit region P are removed is removed. After the bit line spacers are formed on both sidewalls of the semiconductor light emitting device, the second interlayer insulating film 111 is disposed on the first interlayer insulating film 107 to cover the bit lines BL1 and BL2 'including the bit line spacers (not shown). ).

As described above, the present invention can reduce the height of the bit line in the peripheral circuit region P by selectively removing the hard mask pattern 110a for the bit line in the peripheral circuit region P. FIG. Therefore, the present invention can improve the buried characteristics of the interlayer insulating film formed to cover the bit line of the peripheral circuit region P, thereby eliminating the bridge phenomenon between the contact plugs for metal wiring formed in the interlayer insulating film. It is possible to improve the reliability of the metal wiring and the manufacturing yield of the device.

Referring to FIG. 1G, a storage node contact plug 112 is formed in the second interlayer insulating layer 111 and the first interlayer insulating layer 107 of the cell region C to contact a predetermined landing plug 106. The third interlayer dielectric layer 113 is formed on the entire surface of the substrate product on which the contact node 112 for the storage node is formed.

Next, after forming the capacitor hole CH exposing the storage node contact plug 112 in the third interlayer insulating layer 113 of the cell region, the storage hole (H) is embedded while filling the capacitor hole H. A capacitor CP including a stacked film of the SN, the dielectric film DL, and the plate electrode PN is formed.

Next, after the fourth interlayer insulating film 114 is formed on the entire surface of the substrate product on which the plate electrode PN is formed, the fourth interlayer insulating film 114 and the third interlayer insulating film 113 of the peripheral circuit region P are formed. ) And the second interlayer insulating film 111 are formed to form contact holes MH for exposing the etched tungsten film 109a of a predetermined bit line. In this case, since the fourth interlayer insulating film 114, the third interlayer insulating film 113, and the second interlayer insulating film 111 are all oxide materials, etching of the interlayer insulating films 114, 113, and 111 is performed under an oxide etching condition. Do it sequentially.

Then, the metal wiring contact hole MH is filled with a conductive film to form a metal wiring contact plug MC contacting the etched tungsten film 109a of a predetermined bit line of the peripheral circuit region P.

Since the peripheral circuit region bit line includes a hard mask pattern made of a nitride film at an upper end thereof, an etching method for etching the hard mask pattern made of a nitride film is performed after etching the interlayer insulating films for forming the contact hole for metal wiring. Had to be done separately. However, in this case, since the hard mask pattern is not easily etched, there is a problem that the contact hole for metal wiring is not open.

However, according to the present invention, since the bit line hard mask pattern 110a of the peripheral circuit region P is removed, when the metal wiring contact hole MH is formed, the etching process for removing the hard mask pattern of the nitride film material is performed. There is no need to perform the step, and only the interlayer insulating films of an oxide film material, which are easily etched, need to be etched, thereby improving the problem that the contact hole for metal wiring is not open.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention selectively removes the hard mask film portion of the peripheral circuit region from the hard mask film portion, which is one of the constituent films of the bit line, thereby lowering the height of the bit line in the peripheral circuit region to cover the bit line. The buried characteristics of the interlayer insulating film formed so as to be improved can be improved. Accordingly, the present invention can prevent a bridge phenomenon between the contact plugs for metal wiring, which may be caused by a poor filling of the interlayer insulating film.

In addition, the present invention does not need to perform a separate etching process for etching a hard mask film made of a nitride film during etching for forming a metal wiring contact hole exposing a conductive film of a bit line in a peripheral circuit region. Since only the interlayer insulating layers made of an oxide material need to be etched, a problem of not opening the contact hole for metal wiring can be improved.

Therefore, the present invention can improve the reliability of the metal wiring and the manufacturing yield of the device.

Claims (2)

Providing a semiconductor substrate partitioned into a cell region and a peripheral circuit region, the first interlayer insulating film having a bit line contact hole in each region; Forming a bit line formed of a stacked layer of a metal film and a hard mask film to fill a bit line contact hole on the first interlayer insulating film; Forming a mask pattern covering a cell region on the first interlayer insulating layer on which the bit lines are formed; Etching the hard mask layer of the peripheral circuit area by using the mask pattern as an etch barrier; Removing the mask pattern; And And forming a second interlayer insulating film on the first interlayer insulating film so as to cover the bit line of the cell region and the bit line from which the hard mask film of the peripheral circuit area is removed. The method of claim 1, further comprising, after the forming of the second interlayer insulating layer, forming a contact hole for metal wiring to expose the bit line by etching the second interlayer insulating layer in the peripheral circuit region. Method of manufacturing a semiconductor device.

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