TWI680569B - Semiconductor structure and method for forming the same - Google Patents

Abstract

A semiconductor structure includes a plurality of stacks, a plurality of active pillar elements, and an insulating material. The stacks are separated from each other by a plurality of grooves. The active pillar-shaped elements are disposed in the trenches, and are separated from each other in each of the trenches. The active columnar element includes two n-type heavily doped portions on its two sides, respectively. The n-type heavily doped portions each extend in a substantially vertical direction. The n-type heavily doped portions are respectively connected to two corresponding stacks of the stacks. The insulating material is located in the remaining spaces in the trenches between the active pillar-shaped elements. The insulating material is a silicon glass, which includes an element applicable as an n-type dopant.

Description

Semiconductor structure and forming method thereof

This disclosure relates to a semiconductor structure and a method for forming the same. This disclosure relates in particular to a semiconductor structure including an n-type heavily doped portion extending in a substantially vertical direction and having a uniform doping concentration from top to bottom, and a method of forming the same.

For reasons such as volume reduction, weight reduction, increased power density, and improved portability, three-dimensional (3D) semiconductor structures have been developed. Typically, a stack including a plurality of layers may be formed on a substrate and separated from each other by trenches having a high aspect ratio. In some types of 3D semiconductor structures, a doped portion extending in a vertical direction may be further disposed in the trench. Such doped portions can be fabricated by a process of forming a vertically-arranged polycrystalline silicon layer and a subsequent (ion) implantation process. However, since the implantation process is typically performed from above the overall structure, and these portions are vertically arranged in the trench with a high aspect ratio, it is difficult to obtain a uniform doping concentration in the vertical direction. Generally, the doping concentration near the top is higher than the doping concentration near the bottom. This situation may cause electrical differences between devices near the top and devices near the bottom.

This disclosure is directed to a semiconductor structure and a method for forming the same. According to the present disclosure, an n-type heavily doped portion extending in a substantially vertical direction and having a uniform doping concentration from top to bottom can be provided in the semiconductor structure.

According to some embodiments, the semiconductor structure includes a plurality of stacks, a plurality of active pillar elements, and an insulating material. The stacks are separated from each other by a plurality of grooves. The active pillar-shaped elements are disposed in the trenches, and are separated from each other in each of the trenches. The active columnar elements each include two n-type heavily doped portions on two sides thereof. The n-type heavily doped portions each extend in a substantially vertical direction. The n-type heavily doped portions are respectively connected to two corresponding stacks of the stacks. The insulating material is located in the remaining spaces in the trenches between the active pillar-shaped elements. The insulating material is a silicon glass, which includes an element applicable as an n-type dopant.

According to some embodiments, a method of forming such a semiconductor structure includes the following steps. First, an initial structure is provided. The initial structure includes a plurality of stacks that are separated from each other by a plurality of trenches. A plurality of semi-finished products of active columnar elements are formed in the trench. The semi-finished active columnar element is separated from each other in each of these grooves. An insulating material is filled into the remaining spaces in the trenches between the semi-finished products of the active columnar elements. The insulating material is a silicon glass, which includes an element applicable as an n-type dopant. Then, by performing a thermal process for driving the element applicable as an n-type dopant into the semi-finished product of the active columnar element, a plurality of n-type heavily doped portions are formed between the semi-finished product of the active columnar element and the insulating material. .

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

100‧‧‧Semiconductor Structure

102‧‧‧ stacked

104‧‧‧Conductive strip

106‧‧‧Insulation tape

108‧‧‧ Trench

110‧‧‧Active cylindrical element

112‧‧‧n-type heavily doped portion

114‧‧‧Memory layer

116‧‧‧Channel layer

118‧‧‧ Insulation

120‧‧‧n-type heavily doped sites

122‧‧‧ Insulation parts

124‧‧‧Insulation material

200‧‧‧ initial structure

202‧‧‧ substrate

204‧‧‧ stacked

206‧‧‧ conductive strip

208‧‧‧Insulation tape

210‧‧‧stress compensation layer

212‧‧‧Trench

214‧‧‧Initial Memory Layer

216‧‧‧Initial channel layer

218‧‧‧Gate control area

220‧‧‧p-type doped region

222‧‧‧ Insulation

224‧‧‧ intrinsic materials

226‧‧‧contact plug

228‧‧‧ Semi-finished product of active columnar element

230‧‧‧Insulation material

232‧‧‧n-type heavily doped portion

234‧‧‧Contact

BL11, BL12, BL21, BL22‧‧‧bit lines

SL11, SL12, SL21, SL22‧‧‧ source line

R‧‧‧ area

FIG. 1 illustrates an exemplary semiconductor structure according to an embodiment.

FIGS. 2A to 2B to 15A to 15B illustrate different stages of a semiconductor structure during an exemplary method of forming a semiconductor structure according to an embodiment.

In the following, various embodiments will be described in more detail in conjunction with the accompanying drawings, which are only used for description and explanation purposes, and not for limiting purposes. For clarity, components may not be drawn to scale. In addition, some elements and / or element symbols may be omitted from certain drawings. It is expected that elements and features in one embodiment can be advantageously incorporated in another embodiment without further elaboration.

The semiconductor structure according to the embodiment includes a plurality of stacks, a plurality of active pillar elements, and an insulating material. The stacks are separated from each other by a plurality of grooves. The active pillar-shaped elements are disposed in the trenches, and are separated from each other in each of the trenches. The active columnar elements include two n-type heavily doped portions on two sides thereof. The n-type heavily doped portions each extend in a substantially vertical direction. The n-type heavily doped portions are respectively connected to two corresponding stacks of the stacks. The insulating material is located in the remaining spaces in the trenches between the active pillar-shaped elements. The insulating material is a silicon glass, which includes an element applicable as an n-type dopant.

An example of such a semiconductor structure is shown in FIG. in order to For clarity, the semiconductor structure is shown as a 3D AND flash memory device (3D and flash memory devices), and the insulating material in the region R is removed. However, it can be appreciated that the embodiments of the present disclosure are not limited thereto.

Referring to FIG. 1, an exemplary semiconductor structure 100 includes a plurality of stacks 102. The stack 102 may include a plurality of conductive strips 104 and a plurality of insulating strips 106 that are alternately stacked. The number of the conductive strips 104 and the number of the insulating strips 106 are not particularly limited. Although not shown in FIG. 1, the stack 102 may further include one or more other layers, respectively. The stack 102 is separated from each other by a plurality of trenches 108.

The semiconductor structure 100 further includes a plurality of active pillar-shaped elements 110. The active columnar elements 110 are disposed in the trenches 108 and are separated from each other in each of the trenches 108. The active columnar element 110 includes two n-type heavily doped portions 112 on its two sides, respectively. The two n-type heavily doped portions 112 respectively extend in a substantially vertical direction. Here, the vertical direction means a direction perpendicular to one major surface of the semiconductor structure (for example, an upper surface of a substrate (not shown in FIG. 1) on which the stack 102 is formed). In the drawing, the vertical direction is the Z direction, and as shown in the figures 2A to 15A, the upper surface of the substrate extends in the X-Y plane. The term "substantially vertical direction" allows a slight deviation from a precise vertical direction to an angle slightly acceptable in a semiconductor device. Such deviations may, for example, be the result of process limitations. The two n-type heavily doped portions 112 are respectively connected to two corresponding stacks 102 in the stack 102. More specifically, in the X-Y plane, the n-type heavily doped portion 112 may extend in a direction perpendicular to the extending direction of the stack 102.

As an AND flash memory device, in the semiconductor structure 100, the active columnar element 110 may further include two memory layers 114, two channel layers 116, and an insulating layer 118, respectively. Two memory layers 114 are respectively arranged in two corresponding stacks 102 On the side walls. Two channel layers 116 are disposed between the two memory layers 114. The two channel layers 116 are respectively disposed on the sidewalls of the memory layer 114. The insulating layer 118 is disposed between the two channel layers 116. The two channel layers 116 and the insulating layer 118 are located between the two n-type heavily doped portions 112. Although not shown in FIG. 1, the active columnar elements 110 may further include one or more other elements, respectively. For example, the active pillar elements 110 may further include a contact plug disposed on the insulating layer 118. The contact plug undergoes a p-type implant. The active pillar elements 110 may further include a p-type doped region disposed under the insulating layer 118.

Correspondingly, the n-type heavily doped portion 112 may include two n-type heavily doped portions 120 and an insulating portion 122, respectively. The two n-type heavily doped sites 120 are respectively disposed near two corresponding stacks 102. The insulating portion 122 is disposed between the two n-type heavily doped portions 120. More specifically, the positions of the two n-type heavily doped portions 120 correspond to the positions of the two channel layers 116, and the positions of the insulating portions 122 correspond to the positions of the insulating layer 118. According to some embodiments, the contact plug (not shown in FIG. 1) has a first doping concentration, the two n-type heavily doped sites 120 have a second doping concentration, and the second doping concentration is higher than First doping concentration.

As an AND flash memory device, in the semiconductor structure 100, a plurality of memory cells can be defined at the intersection of the conductive strip 104 and the channel layer 116. According to some embodiments, the conductive strip 104 may be a word line, and for each of the active pillar elements 110, one of the two n-type heavily doped portions 112 is electrically connected to the bit. Line, the other is electrically connected to the source line. In the semiconductor structure 100, the active columnar elements 110 are arranged in an alternating manner. Correspondingly, bit line pairs such as bit lines BL11 and BL12 and BL21 and BL22 are provided, and source line pairs such as source lines SL11 and SL12 and SL21 and SL22 are provided. Can It can be appreciated that other types of configurations can be applied to the active columnar element 110 and the corresponding bit line and source line.

The semiconductor structure 100 further includes an insulating material 124. The insulating material 124 is located in the remaining spaces in the trenches 108 between the active pillar elements 110. The insulating material 124 is a silicon glass, which includes an element applicable as an n-type dopant. For example, the silicon glass may be phosphorous silicon glass (PSG) or arsenic silicon glass (ASG).

A method of forming a semiconductor structure according to an embodiment includes the following steps. First, an initial structure is provided. The initial structure includes a plurality of stacks that are separated from each other by a plurality of trenches. A plurality of semi-finished products of active columnar elements are formed in the trench. The semi-finished active columnar element is separated from each other in each of these grooves. An insulating material is filled into the remaining spaces in the trenches between the semi-finished products of the active columnar elements. The insulating material is a silicon glass, which includes an element applicable as an n-type dopant. Then, by performing a thermal process for driving the element applicable as an n-type dopant into the semi-finished product of the active columnar element, a plurality of n-type heavily doped portions are formed between the semi-finished product of the active columnar element and the insulating material .

The different stages of the semiconductor structure in this type of method are shown in Figures 2A ~ 2B to 15A ~ 15B, where the pattern indicated by "A" and the pattern indicated by "B" are shown separately A perspective view and a corresponding cross-sectional view, the cross-sectional view is along the corresponding CC "line in the drawing indicated by" A ". For clarity, only a portion of a stack and two adjacent trenches are shown. The semiconductor structure is illustrated as a 3D AND flash memory device. However, it can be appreciated that the embodiments disclosed herein are not limited thereto.

Please refer to FIGS. 2A-2B to provide an initial structure 200. initial The structure 200 includes a substrate 202. The initial structure 200 further includes a plurality of stacks 204 that can be formed on the substrate 202. The stack 204 may include a plurality of conductive strips 206 and a plurality of insulating strips 208, which are alternately stacked on each other. The conductive strip 206 may be formed of doped polycrystalline silicon or any other suitable material. The insulating strip 208 may be formed of silicon oxide. In some embodiments, the stack 204 further includes a stress compensation layer 210 located above the conductive strip 206 and the insulating strip 208. The stress compensation layer 210 compensates the tensile stress and prevents the high-aspect-ratio stack 204 from collapsing or bending. The stress compensation layer 210 may be formed of silicon nitride. The stack 204 is separated from each other by a plurality of trenches 212.

Referring to FIGS. 3A to 3B, an initial memory layer 214 is formed on the initial structure 200 in a conformal manner. The initial memory layer 214 may be a BE-SONOS (energy-gap engineering silicon-oxide-nitride-oxide-silicon) layer, an ONONO (oxide-nitride-oxide-nitride-oxide) layer, or any other Suitable layer.

Referring to FIGS. 4A-4B, an initial channel layer 216 is formed on the initial memory layer 214 in a conformal manner. The initial channel layer 216 may be formed of polycrystalline silicon. The initial channel layer 216 includes a plurality of gate control regions 218 corresponding to the conductive strips 206, as shown in FIG. 4B.

Please refer to FIGS. 5A-5B. Optionally, a p-type dopant can be used to implant the portion of the initial channel layer 216 located at the bottom of the trenches 212. Thereby, a plurality of p-type doped regions 220 are formed. This step ensures that the bottom portion of the channel is p-type doped, thereby reducing the leakage path. The p-type doped region 220 may be further cut at a subsequent stage (for example, a stage described with reference to FIGS. 12A to 12B), and the active pillar-shaped element 110 disposed under the insulating layer 118 described with reference to FIG. 1 is formed. p-type doped region.

Please refer to Figures 6A ~ 6B. A plurality of insulating layers 222 are formed in a corresponding manner. The insulating layer 222 may be formed of an oxide. Then, a planarization process can be performed, as shown in FIGS. 7A to 7B. The planarization process ends at the portion of the initial memory layer 214 on the stack 204. The planarization process may be a chemical mechanical planarization (CMP) process, an etching back process, or any other suitable planarization process.

Referring to FIGS. 8A to 8B, the top portion of the insulating layer 222 is removed. Next, referring to FIGS. 9A to 9B, an intrinsic material 224, such as polycrystalline silicon, is filled into the space created by the step of removing the top portion of the insulating layer 222. As shown in FIGS. 9A-9B, the intrinsic material 224 can form a layer on the semiconductor structure. Therefore, a planarization process can be performed, as shown in FIGS. 10A to 10B. The planarization process also ends at the portion of the initial memory layer 214 on the stack 204. Please refer to FIGS. 11A-11B to perform an implantation process using a p-type dopant. In particular, an intrinsic material 224 (polycrystalline silicon) is implanted using the p-type dopant. The p-type dopant may be, but is not limited to, boron (B). According to some embodiments, the doping concentration of the polycrystalline silicon implanted using the p-type dopant may fall on the order of 10 ¹⁵ cm ^-3 . Thereby, a plurality of contact plugs 226 of the semi-finished products of the active columnar elements are formed. The contact plug 226 provides a sufficient silicon portion thickness for the landing of the contact. An implantation process using a p-type dopant can provide a p-type doped contact plug 226, especially a p-type heavily doped contact plug 226, which can reduce the plug resistance and avoid punch through )occur.

Next, referring to FIGS. 12A to 12B, at least a portion of the initial channel layer 216 and the insulating layer 222 located in each of the trenches is cut. In this way, a plurality of semi-finished products 228 of active columnar elements are formed in the trench 212. In each of these grooves 212, the semi-finished active columnar element 228 is separated from each other. Active column The shaped element semi-finished products 228 may be, but are not limited to, arranged in an alternating manner. The opening formed by the cutting step may extend into the substrate 202, as shown in FIG. 12B. Alternatively, the openings may terminate in the initial memory layer 214 without extending to the substrate 202.

Referring to FIGS. 13A to 13B, an insulating material 230 is filled into the remaining spaces in the trenches 212 between the semi-finished products 228 of the active columnar elements (ie, the openings formed in the previous stage). The insulating material is a silicon glass, which includes an element applicable as an n-type dopant. For example, the silica glass may be a phosphorous silica glass (PSG) or an arsenic silica glass (ASG). In other words, the element that can be used as an n-type dopant in silica glass is phosphorus (P) or arsenic (As). In some embodiments, the use of PSG is preferred because the phosphorus in PSG has a higher rate of thermal diffusion than arsenic in ASG. According to some embodiments, the doping concentration of the p-type dopant implanted polycrystalline silicon in the stage described with reference to FIGS. 8A to 8B is lower than that driven from the insulating material 230 to the active pillar in the subsequent thermal process. The doped element semi-finished product 228 can be applied as a doping concentration of the element of the n-type dopant, so that the portion of the initial channel layer 216 and the contact plug 226 near the insulating material 230 after cutting is formed after the thermal process The n-type heavily doped portion 232 (shown in FIGS. 14A to 14B). For example, when the doping concentration of polycrystalline silicon implanted with p-type dopants falls in the order of 10 ¹⁵ cm ^-3 , the application of n-type doping from the driving of insulating materials to semi-finished products of active columnar elements can be applied. The doping concentration of the impurity element may be equal to or higher than 5 × 10 ²⁰ cm ^-3 . Correspondingly, in the insulating material 230, the doping concentration of the element applicable to the n-type dopant is equal to or higher than 5 × 10 ²⁰ cm ⁻³ .

Please refer to FIGS. 14A to 14B. By performing a thermal process of driving an element applicable as an n-type dopant into the semi-finished product 228 of the active columnar element, a plurality is formed between the semi-finished product 228 and the insulating material 230 N-type weight Doped portion 232. In this way, the active columnar element described with reference to FIG. 1 can be formed. An element that can be applied as an n-type dopant can be driven into the undoped or doped polycrystalline silicon portion of the semi-finished product 228 of the active columnar element by a thermal process because it is more inclined to stay In polycrystalline silicon. According to some embodiments, the thermal process may be performed at 950 ° C for 30 minutes. It can be appreciated that higher temperatures and / or longer heating times may be used. As described above, when the p-type dopant is used to implant polycrystalline silicon, the doping concentration is lower than the doping concentration of the element that can be used as the n-type dopant in the semi-finished product of the active columnar element driven from the insulating material Next, the portion of the cut initial channel layer 216 and the contact plug 226 near the insulating material 230 forms an n-type heavily doped portion 232 after the thermal process, as shown in FIGS. 14A-14B.

Referring to FIGS. 15A to 15B, a plurality of contacts 234 can be formed on the n-type heavily doped portions 232 respectively. The two n-type heavily doped portions 232 of each active pillar element can be used as the source region and the drain region, respectively, and the contacts 234 thereon can be used to provide electrical connection to the source electrode to be disposed above the structure. Line and bit line (as shown in Figure 1). It can be understood that after the stages shown in FIGS. 15A-15B, some further processes may be performed, such as a process of forming bit lines and source lines.

According to the disclosure, the dopants used in the implantation process of an n-type heavily doped portion extending in a substantially vertical direction are obtained from a lateral implantation source (that is, including an n-type Doped elemental silicon glass). Thus, a uniform doping concentration can be obtained in the vertical direction. The silica glass can be used to replace insulating materials traditionally used in semiconductor structures to isolate vertically extending elements. Therefore, the above process can be easily performed in a self-aligned and controlled manner without much additional cost. In addition, these processes are compatible with the general manufacturing of semiconductor devices. Cheng.

The exemplary 3D AND flash memory device and the exemplary formation method thereof can be used in various applications, particularly those in which doped portions having a strong doping concentration in a vertical direction are strongly required. One example is the field of AI memory applications. Furthermore, although the above embodiments are exemplified for a 3D memory device, it can be appreciated that the concepts disclosed herein can be applied to other semiconductor structures that require a uniform n-type heavily doped portion extending in a substantially vertical direction .

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (10)

A semiconductor structure includes: a plurality of stacks separated from each other by a plurality of trenches; a plurality of active pillar-shaped elements disposed in the trenches and separated from each other in each of the trenches, wherein the These active pillar-shaped elements each include two n-type heavily doped portions on two sides thereof, the n-type heavily doped portions each extend in a substantially vertical direction, and the n-type heavily doped portions are respectively Connecting two corresponding stacks of the stacks; and an insulating material located in the remaining spaces between the active pillar-shaped elements in the trenches, wherein the insulating material is a silicon glass, the silicon glass includes An element that can be applied as an n-type dopant. The semiconductor structure according to item 1 of the scope of patent application, wherein the stacks respectively include a plurality of conductive strips and a plurality of insulating strips that are alternately stacked; wherein the active columnar elements further include: two memory layers, Respectively disposed on the sidewalls of the two corresponding stacks; two channel layers are disposed between the two memory layers, wherein the two channel layers are respectively disposed on the sidewalls of the two memory layers; and an insulating layer , Disposed between the two channel layers; wherein the two channel layers and the insulating layer are located between the two n-type heavily doped portions; and wherein a plurality of memory cell lines are defined in the conductive strips Intersections with these channel layers. The semiconductor structure according to item 2 of the scope of patent application, wherein the active columnar elements further include: a contact plug, which is disposed on the insulating layer; and a p-type doped region, which is disposed on the insulating layer. under. The semiconductor structure according to item 3 of the scope of the patent application, wherein the n-type heavily doped portions respectively include: two n-type heavily doped portions, which are respectively disposed near the two corresponding stacking portions; and an insulating portion, It is disposed between the two n-type heavily doped sites. The semiconductor structure according to item 4 of the application, wherein the contact plug undergoes p-type implantation and has a first doping concentration, and the two n-type heavily doped sites have a second doping concentration. And the second doping concentration is higher than the first doping concentration. The semiconductor structure according to item 1 of the scope of the patent application, wherein the silica glass is phosphosilicate glass (PSG) or arsenic silica glass (ASG). A method for forming a semiconductor structure includes: providing an initial structure including a plurality of stacks, the stacks being separated from each other by a plurality of trenches; and forming a plurality of semi-finished products of active columnar elements in the trenches, wherein The semi-finished products of active columnar elements are separated from each other in the trenches; an insulating material is filled into the remaining spaces in the trenches between the semi-finished products of active columnar elements, wherein the insulating material It is a silicon glass, which includes an element applicable as an n-type dopant; and a heat that drives the element applicable as an n-type dopant into the semi-finished products of the active columnar elements by driving In the manufacturing process, a plurality of n-type heavily doped portions are formed between the semi-finished products of the active columnar elements and the insulating material. The method for forming a semiconductor structure according to item 7 of the scope of the patent application, wherein the step of forming the semi-finished products of the active columnar elements includes: forming an initial memory layer in a conformal manner on the initial structure; and in the initial memory layer An initial channel layer is formed in a conformal manner on the top; a portion of the initial channel layer at the bottom of the trenches is implanted with a p-type dopant; and the corresponding spaces are formed in the remaining spaces of the trenches respectively A plurality of insulating layers; performing a planarization process, the planarization process ends at the portion of the initial memory layer on the stacks; removing a top portion of the insulating layers, and forming the active columnar elements A plurality of contact plugs of the semi-finished product; and cutting at least a portion of the initial channel layer and the insulating layers in each of the trenches. The method for forming a semiconductor structure according to item 8 of the scope of the patent application, wherein a doping concentration of the polycrystalline silicon implanted with a p-type dopant falls in the order of 10 ¹⁵ cm ^-3 and is driven from the insulating material to the In the semi-finished products of the active columnar elements, a doping concentration of the element that can be applied as an n-type dopant is equal to or higher than 5 × 10 ²⁰ cm ^-3 , so that the cut initial channel layer and the contacts are Portions of the plug near the insulating material form the n-type heavily doped portions after the thermal process. The method for forming a semiconductor structure according to item 8 of the application, wherein the step of forming the contact plugs includes: filling polysilicon into a space generated by the step of removing the top portion of the insulating layers. ; And performing an implantation process using p-type dopants.