CN106992182B - Memory device, method for manufacturing the same, and electronic equipment including the same - Google Patents

Abstract

A storage device, a method for manufacturing the same, and an electronic device including the storage device are disclosed. According to an embodiment, a memory device may include a plurality of columnar active regions formed on a substrate and extending upward from the substrate; and a plurality of columnar active regions arranged in sequence from bottom to top on the substrate, spaced apart from each other, and respectively surrounding the columnar active regions. Multi-layer gate electrode layers, wherein each gate electrode layer faces each columnar active region through a storage gate dielectric stack, wherein the columnar active region includes a first doped region opposite to each gate electrode layer and a first doped region located in each first A second doped region on opposite sides of the doped region, wherein the doping characteristic in the first doped region is different from the doping characteristic in the second doped region.

Description

Memory device, method for manufacturing the same, and electronic equipment including the same

technical field

The present disclosure relates to the field of semiconductors, and in particular, to a vertical device-based memory device, a method of manufacturing the same, and an electronic device including such a memory device.

Background technique

In a horizontal type device such as a metal oxide semiconductor field effect transistor (MOSFET), the source, gate and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, the horizontal type device cannot easily be further reduced. In contrast, in a vertical device, the source, gate, and drain are arranged in a direction generally perpendicular to the substrate surface. Therefore, vertical type devices are easier to shrink than horizontal type devices.

In a vertical device based memory device, there are stacked memory cells such that the respective resistances of the memory cells are connected in series. Thus, the total resistance increases, and the performance of the memory device deteriorates. Since the active regions (including the channel regions and the source/drain regions) are generally formed integrally in conventional vertical memory devices, the types and concentrations of dopants in the channel regions and the source/drain regions are substantially the same. Therefore, it is difficult to reduce the total resistance by increasing the doping concentration of the source/drain regions, because this will also increase the doping concentration in the channel region, thereby increasing the leakage current between the source and drain.

SUMMARY OF THE INVENTION

In view of this, an object of the present disclosure is, at least in part, to provide a vertical-type device-based memory device, a method of fabricating the same, and an electronic device including such a memory device, wherein the channel region and the source/drain region can be adjusted separately Doping type/concentration.

According to one aspect of the present disclosure, there is provided a memory device including: a plurality of columnar active regions formed on a substrate and extending upward from the substrate; and sequentially arranged on the substrate from bottom to top, spaced apart from each other and Multi-layer gate electrode layers respectively surrounding each columnar active region, wherein each gate electrode layer faces each columnar active region through a stack of storage gate dielectrics, wherein the columnar active region includes a first gate electrode layer opposite to each gate electrode layer. Doping regions and second doping regions on opposite sides of each of the first doping regions, wherein doping properties in the first doping regions are different from doping properties in the second doping regions.

According to another aspect of the present disclosure, there is provided a method of fabricating a memory device comprising: disposing an alternating stack of dopant source layers and gate electrode layers on a substrate, wherein the dopant source layer includes a type of dopant dopant; forming holes in the stack; filling the holes with semiconductor material, and thermally treating the holes to drive dopants from the dopant source layer into the semiconductor material; and between the gate electrode layer and the semiconductor material A storage gate dielectric stack is formed therebetween.

According to another aspect of the present disclosure, there is provided an electronic device including the above memory device.

According to embodiments of the present disclosure, different regions of the active region (eg, channel regions and source/drain regions) may be doped differently, and thus may have different doping characteristics. For example, the source/drain regions can be further doped using a dielectric solid-phase dopant source as a diffusion source to increase the doping concentration therein, thereby lowering the resistance of the source/drain regions and thus lowering the stacked memory The total series resistance of the cell. Thus, the number of stacked memory cells can be increased, and thus the integration density can be increased.

Description of drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

1-10 are schematic diagrams illustrating a flow of manufacturing a memory device according to an embodiment of the present disclosure;

11 and 12 are flowcharts illustrating some stages of a process for manufacturing a memory device according to another embodiment of the present disclosure;

13 and 14 illustrate flowcharts of some stages in a process for fabricating a memory device according to yet another embodiment of the present disclosure.

Throughout the drawings, the same or similar reference numbers refer to the same or similar parts.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

Memory devices according to embodiments of the present disclosure are based on vertical devices, and thus may include a plurality of columnar active regions formed on a substrate extending upward (eg, substantially perpendicular to the substrate surface) from the substrate. The columnar active regions can be solid or hollow (where a dielectric can be filled). Based on these vertically extending columnar active regions, vertical devices can be formed by forming gate stacks around their peripheries. The gate stack may be a memory gate stack in order to implement a memory function. For example, the gate stack may include a storage gate dielectric stack formed on at least a portion of an outer wall of the columnar active region, and a gate electrode layer facing the columnar active region via the storage gate dielectric stack. The gate electrode layer extends in a direction intersecting the extending direction of the columnar active region (eg, substantially parallel to the substrate surface), thereby intersecting the columnar active region, and thus may define a channel region (and thus can define a channel region in the columnar active region). Source/drain regions are defined accordingly, ie the portions of the active region on opposite sides of the channel region). A conductive channel may be formed between the source/drain regions through the channel region.

Multiple gate electrode layers arranged in sequence from bottom to top, spaced apart from each other and surrounding each columnar active region, respectively, can be provided, thereby correspondingly defining a plurality of channel regions (and thus a plurality of memory cells) in each columnar active region. , each memory cell includes a corresponding channel region and source/drain regions on opposite sides of the channel region). The respective source/drain regions of upper and lower adjacent memory cells may be connected together (eg, physically integrated). Here, the storage unit may be a flash memory (flash) unit.

The columnar active regions may be arranged in an array (eg, typically a two-dimensional array arranged in rows and columns). In addition, the memory device may be a three-dimensional (3D) array since they extend vertically on the substrate as described above and define multiple layers of memory cells through the multiple layers of gate electrode layers, respectively. In this 3D array, each columnar active region defines a string of memory cells.

Herein, the so-called "storage gate dielectric stack" refers to the portion of the storage gate stack between the gate electrode layer and the active region (or the channel region). The stack as a whole exhibits dielectric properties, ie, such that the gate electrode layer is not directly electrically connected to the channel region, thus being called a "dielectric" stack, but this does not preclude the possibility that one or more layers may be included in the stack conductive layer. The storage gate dielectric stack may include a charge trapping layer, a floating gate layer, or a ferroelectric material, etc., in order to realize a storage function. For example, the storage gate dielectric stack may include a first gate dielectric layer, a floating gate layer or charge trapping layer, and a second gate dielectric layer stacked in sequence, or may include a first metal layer, a ferroelectric material layer, a second metal layer and gate dielectric layer. There are various memory gate stack configurations capable of realizing the memory function in the art, and details are not described herein again.

The columnar active region may include a first doping region opposite to each gate electrode layer and a second doping region located on opposite sides of each first doping region. For example, the first doped region may correspond to the channel region, and the second doped region may correspond to the source/drain region. According to embodiments of the present disclosure, doping characteristics in the first doped region may be different from doping characteristics in the second doped region. Here, the "doping characteristics" are different means that there is a difference in at least one of the doping concentration and the doping type. For example, there may be at least one of the following: (1) the doping concentration in the first doped region is different from the doping concentration in the second doped region; (2) the doping type in the first doped region is different The doping type in the second doping region; (3) the doping concentration in the first doping region is different from the doping concentration in the second doping region, and the doping type in the first doping region is different Doping type in the second doped region.

According to embodiments of the present disclosure, the doping concentration in the second doping region may be increased (while the doping concentration in the first doping region may be kept relatively small to avoid leakage current increase). Thus, the total series resistance of the memory cells stacked on each other can be reduced.

According to embodiments of the present disclosure, the semiconductor material in the columnar active region can be homogeneous (eg, a common silicon material) and can be doped differently to achieve a desired doping profile in the columnar active region . For example, a relatively high doping concentration in the second doped region can be achieved by moving from a dopant source layer disposed between the gate electrode layers (and thus aligned with where the source/drain regions are located) to the columnar active region This is achieved by driving in dopants.

Such a memory device can be manufactured, for example, as follows. In particular, alternating stacks of dopant source layers and gate electrode layers may be provided on the substrate. The lowermost of the stack may be a dopant source layer, and the uppermost may also be a dopant source layer. The dopant source layer may be a dielectric layer that contains a certain type and concentration of dopants. For example, dopants may be introduced therein by doping the dopant source layer in situ as it is formed, eg, deposited. At each dopant source layer and each gate electrode layer, a diffusion barrier layer may also be formed to suppress undesired diffusion of dopants in the dopant source layer.

Then, several holes can be formed in the stack. Subsequently, active regions will be formed in these holes (corresponding to the shape of the holes and thus may be "pillars", including but not limited to cylinders). These holes may extend along the stacking direction (vertical direction) of the stack and may penetrate the stack. In the following processing, these holes are machined channels.

A memory gate dielectric stack may be formed on sidewalls of the hole at least corresponding to the gate electrode layer. The storage gate dielectric stack thus formed together with the gate electrode layer constitutes a storage gate stack. The holes can then be filled (doped) with semiconductor material to form (columnar) active regions. The semiconductor material can completely fill the hole to form a solid columnar active region, or only along the inner wall of the hole to form a hollow columnar active region (which can be further filled with a dielectric layer). The active region cooperates with each storage gate stack to form a storage cell.

Subsequently, thermal processing may be performed to drive dopants from the dopant source layer into the semiconductor material. Due to the dopant from the dopant source layer, the doping concentration in the portion (source/drain region) of the columnar active region corresponding to the dopant source layer will increase, and thus the source/drain can be reduced resistance of the area.

In addition to changing the doping profile in the active region by driving in dopants from the dopant source layer, the doping profile in the channel region can also be individually adjusted according to embodiments of the present disclosure. For example, this can be achieved by separately forming (at least part of) the channel region. To this end, some processing may be performed on the site where the channel region is to be formed (ie, where the gate electrode layer is located). For example, the gate electrode layer may be selectively etched through the holes so as to be recessed to some extent. These recesses can then accommodate channel regions. Depending on the fabrication process, only these recesses can be filled with semiconductor material for the channel region (usually can be lightly doped). Such filling can be carried out, for example, as follows. In particular, the holes may be filled with semiconductor material via the holes (eg, simultaneously doped in situ). During filling, the semiconductor material can likewise enter the recess. The filled semiconductor material can then be etched back through the hole. In this way, the semiconductor material can remain within the recesses while the semiconductor material in the holes is substantially removed. The holes can then be filled with semiconductor material (which can be doped differently, eg, can be moderately doped, to adjust the threshold voltage) forming the rest of the active region. The active regions thus formed may be heavily doped at the source/drain regions after receiving dopants driven in from the dopant source layer.

In conjunction with this process, the storage gate dielectric stack can also be limited to the channel region instead of being formed on the entire inner wall of the hole. For example, after the semiconductor material is filled in the recess, the storage gate dielectric stack can be selectively etched using the filled semiconductor material as a mask, so that the storage gate dielectric stack remains only under these semiconductor materials (also That is, only at the channel region).

The present disclosure may be presented in various forms, some examples of which are described below.

1-10 show schematic diagrams of a flow of fabricating a memory device according to an embodiment of the present disclosure.

As shown in FIG. 1, a substrate 1001 is provided. The substrate 1001 may be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like. In the following description, for the convenience of description, a bulk Si substrate is used as an example for description.

In the substrate 1001, for example, by ion implantation, a well region 1001w is formed. The well region 1001w can then serve as a common ground potential plane of the memory device, and the source/drain regions of the respective lower layers of the lowermost memory cells in the memory device can be connected to the common ground potential plane. If the memory cell is an n-type device, the well region 1001w may be doped to be n-type; if the memory cell is a p-type device, the well region 1001w may be doped to be p-type.

On the substrate 1001, a first dopant source layer 1003, a first gate electrode layer 1005, a second dopant source layer 1007, a second gate electrode layer 1009 and a third dopant layer can be sequentially formed by, for example, deposition Agent source layer 1011 . The first dopant source layer 1003, the second dopant source layer 1007, and the third dopant source layer 1011 may each include a suitable dielectric material, such as an oxide, and contain a certain type of dopant (eg, for p type devices contain p-type dopants and n-type dopants for n-type devices), with a thickness of about 20-50 nm. The dopant can be introduced into the dopant source layer at the same time as the dopant source layer is formed, for example, by in-situ doping. In one example, each dopant source layer may comprise n-type doped phosphosilicate glass (PSG) or arsenic silicate glass (AsSG) (for n-type devices), or p-type doped borosilicate glass (BSG) (For p-type devices), the dopant may be included at a concentration of about 0.01-10%. The first gate electrode layer 1005 and the second gate electrode layer 1009 may include a suitable gate electrode material such as doped polysilicon or metal, with a thickness of about 10-100 nm. The steps of forming the gate electrode layer and the dopant source layer may be repeated up to the desired number of layers.

In addition, a hard mask may also be formed over these grown layers for the purpose of facilitating patterning in subsequent processing and providing appropriate stop layers. For example, a nitride (eg, silicon nitride) layer 1015 may be formed to a thickness of, eg, about 10-100 nm.

Subsequently, the location of the active region can be defined. As shown in the top view of FIG. 2, the substrate may include memory cell regions in which memory cells may be formed and contact regions in which various electrical contacts may be formed. Of course, the substrate may also include other regions, such as circuit regions for forming related circuits, and the like. In the memory cell region, a photoresist 1017 may be formed on the structure shown in FIG. 1 . By photolithography (exposure and development), the photoresist 1017 is patterned to expose the underlying nitride layer 1015 at the locations of the active regions. The layout of the holes depends on the layout of the memory cells, for example, the holes may be arranged in a two-dimensional array in rows and columns.

Next, as shown in FIG. 3 (a cross-sectional view along the line AA' in FIG. 2 ), a hole may be opened downward through the photoresist. Specifically, the nitride layer 1015 , the third dopant source layer 1011 , the second gate electrode layer 1009 , the second dopant source layer 1007 , the first gate electrode layer 1009 , the second dopant source layer 1007 , the first gate electrode layer 1015 , the second dopant source layer 1007 , the first gate electrode layer 1005 and first dopant source layer 1003 to form holes. For example, RIE may be performed in a direction generally perpendicular to the substrate surface, resulting in holes extending in a direction generally perpendicular to the substrate surface. Afterwards, the photoresist 1017 can be removed. In this example, the hole may penetrate the stack of the gate electrode layer and the dopant source layer.

Here, the holes are shown as circular, but the present disclosure is not limited thereto. The holes can be of any shape suitable for machining.

Then, as shown in FIG. 4, the gate electrode layers 1005, 1009 may be selectively etched (with respect to the dopant source layer) via the holes. For example, a suitable etchant can be chosen that etches the gate electrode layer (much) more than the dopant source layer. Thus, the gate electrode layers 1005, 1009 may be recessed relative to the dopant source layers 1003, 1007, 1011 to provide space to accommodate (at least a portion of) the channel region. Here, the amount of etching can be controlled so that the concavities formed in the gate electrode layers 1005 and 1009 are annular around each hole, and at the same time, there is no communication between the holes.

Afterwards, as shown in FIG. 5 , a storage gate dielectric stack 1019 may be formed on the inner wall of the hole. For example, the layers in the storage gate dielectric stack can be sequentially deposited on the structure shown in FIG. 4 (the layer configuration in the stack is not shown in the figure), so that the storage gate dielectric stack can be formed in FIG. 4 each exposed on the surface. For example, the storage gate dielectric stack 1019 may include a first gate dielectric layer (eg, oxide or high-K dielectric such as HfO ₂ , about 1-10 nm thick), a charge trapping layer (eg, nitride, thick about 1-20 nm) and a second gate dielectric layer (eg, oxide or high-K dielectric with a thickness of about 1-10 nm).

Alternatively, the storage gate dielectric stack 1019 may include a first gate dielectric layer (eg, oxide or high-K dielectric such as HfO ₂ , with a thickness of about 1-10 nm), a floating gate layer (eg, metal, thickness of about 1-20 nm) and a second gate dielectric layer (eg, oxide or high-K dielectric, thickness of about 1-10 nm).

Alternatively, the storage gate dielectric stack 1019 may comprise a ferroelectric material. For example, the storage gate dielectric stack 1019 may include a first metal layer, a ferroelectric material layer, a second metal layer, and a gate dielectric layer (eg, an oxide or a high-K dielectric such as HfO ₂ , having a thickness of about 1- 10nm). For example, the ferroelectric material may include hafnium oxide such as HfO ₂ , zirconium oxide such as ZrO ₂ , tantalum oxide such as TaO ₂ , hafnium zirconium oxide Hf _x Zr _1-x O ₂ (where x is in the range of (0, 1)) Such as Hf _0.5 Zr _0.5 O ₂ , hafnium tantalum oxide Hf _x Ta _1-x O ₂ (where x is in the range of (0, 1)) such as Hf _0.5 Ta _0.5 O ₂ , HfO ₂ containing Si, and Al-containing HfO ₂ , BaTiO ₃ , KH ₂ PO ₄ or SBTi, each of the first metal layer and the second metal layer may include TiN. In this case, one side of the gate dielectric layer in the storage gate dielectric stack 1019 faces the gate electrode layer.

The recesses may then be filled with semiconductor material 1021 for the channel region, such as polysilicon. Here, the semiconductor material 1021 may be lightly doped to reduce channel resistance. For junction devices, the semiconductor material 1021 may be n-type doped for p-type devices and p-type doped for n-type devices; and for junctionless devices, the semiconductor material 1021 may be p-type doped for p-type devices, for n-type devices are n-type doped.

For example, as shown in FIG. 5, the holes and recesses can be filled with semiconductor material 1021 by deposition, which can be simultaneously doped in situ. The filled semiconductor material 1021 should completely fill the holes and recesses with excess. The semiconductor material 1021 may be planarized, such as chemical mechanical polishing (CMP), to remove portions thereof outside the holes and recesses. For example, the planarization process can be stopped at the hard mask layer 1015 (so that the storage gate dielectric stack on its top surface can also be removed, see FIG. 6).

Then, as shown in FIG. 6, the semiconductor material 1021 may be etched back, leaving it in the recess. For example, the semiconductor material 1021 may be etched back by RIE in a direction substantially perpendicular to the substrate surface. Due to the presence of the layers above the recess, the semiconductor material 1021 in the recess may be shaded, and thus may remain. This portion of (lightly doped) semiconductor material 1021 (which may be referred to as the "first doped region") remaining in the recess may then be used for the channel region. The remaining semiconductor material 1021 is self-aligned to the gate electrode layer due to formation in the recesses in the gate electrode layer.

In conjunction with this, as shown in FIG. 7, the storage gate dielectric stack 1019 can be selectively etched to be confined to the channel region, especially in the case where the storage gate dielectric stack 1019 includes a conductive layer . In this example, the storage gate dielectric stack 1019 is also left in the recess due to shading by the semiconductor material 1021 .

Of course, the present disclosure is not limited thereto. For example, the storage gate dielectric stack 1019 can also be left on the inner wall of the hole, especially the sidewall (the part on the bottom wall can be removed, for example, by vertical RIE), especially if the storage gate dielectric stack 1019 does not include a conductive layer case, this will not affect the operation of the device.

Subsequently, as shown in FIG. 8 , the holes can be filled with semiconductor material 1023 for the rest of the active region. Here, the materials of the semiconductor material 1023 and the semiconductor material 1021 may be the same, such as polysilicon. Here, the semiconductor material 1023 may be moderately doped to adjust the device threshold voltage. For junction devices, the semiconductor material 1023 may be n-type doped for p-type devices and p-type doped for n-type devices; and for junctionless devices, the semiconductor material 1023 may be p-type doped for p-type devices and p-type doped for p-type devices n-type devices are n-type doped.

For example, the holes can be filled with semiconductor material 1023 by deposition, which can be simultaneously doped in situ. The filled semiconductor material 1023 should completely fill the hole with excess. The semiconductor material 1023 may be subjected to a planarization process, such as CMP, to remove its portion outside the hole. For example, the planarization process may stop at the hard mask layer 1015 .

The semiconductor materials 1021 and 1023 together form a (columnar) active region. The active region is filled in the hole so as to have substantially the same shape as the hole and like the hole extends vertically on the substrate.

As shown in FIG. 9, a thermal treatment such as annealing at a temperature of about 700°C-1100°C may be performed to drive dopants from the dopant source layers 1003 , 1007 , 1011 into the active regions 1021 , 1023 . The dopants originating from the dopant source layer form a certain distribution in the active region, resulting in a heavily doped second doped region, which can be used as the source/drain region S/D (in the In the case of a junction device, the dopant originating from the dopant source layer may invert the doping type in the portion of the active region into which it diffuses), as shown by the dashed box in FIG. 9 . Since the dopant source layers serving as diffusion sources are located on the upper and lower sides of the gate electrode layer, the second doped regions or source/drain regions S/D obtained therefrom can be aligned with the dopant source layers, and correspondingly The ground is located on the upper and lower sides of the channel region (including the first doping region, and possibly a part of the semiconductor material 1023, such as the part between the source/drain regions S/D). Since the first doped region and the second doped region can each be self-aligned to the gate electrode layer and the dopant source layer, respectively, the doping profile in the first doped region can be the same as the doping profile in the second doped region. The doping profile is substantially aligned (specifically, the upper end of the doping profile of the first doping region may be substantially aligned with the lower end of the doping profile of the second doping region above, and the doping profile of the first doping region The lower end of the can be substantially aligned with the upper end of the doping profile of the second doped region below).

Since the dopant source layer surrounds the perimeter of each active region, diffusion can proceed inward from the outer walls of the active region. The diffusion may not be bridged in the radial direction, so that the source/drain regions S/D may be annular. In addition, the source and drain regions S/D may have a certain overlap with the semiconductor material 1021, and the lowermost source and drain regions S/D may have a certain overlap with the common ground potential plane 1001w.

Therefore, in the memory cell region, vertical strings of memory cells are formed, each memory cell including a corresponding channel region and source/drain regions located on the upper and lower sides of the channel region. Since the source/drain regions are shared between adjacent memory cells, each string of memory cells is connected to each other in series.

In this example, the dopant source layer is left. However, the present disclosure is not limited thereto. For example, the dopant source layer can be removed by, for example, forming machined holes in the contact regions and selectively etched through the machined holes. The space left by the removal of the dopant source layer can be filled with dielectric material, for example, by deposition through a machined hole.

Also, in this example, polysilicon is left as the gate. However, the present disclosure is not limited thereto, and a replacement gate structure may be further formed. For example, the polysilicon layer may be removed by, for example, forming machined holes in the contact regions, and selectively etching through the machined holes. The space left by the removal of the polysilicon layer may, for example, be filled by deposition through a machined hole to fill the gate electrode and/or the storage gate dielectric stack (in this case, it may not be necessary as described above in connection with FIGS. 5 and 6 A storage gate dielectric stack is preformed on the inside of the hole).

In addition, in this example, its doping profile is individually adjusted for the channel region. However, the present disclosure is not limited thereto. For example, after opening the holes as described above in connection with FIG. 3, a storage gate dielectric stack can be formed on the sidewalls of the holes, and filled with (lightly or moderately doped) semiconductor material on the inside thereof as active regions. Dopants can then be driven into the active regions by thermal processing to form heavily doped source/drain regions.

Subsequently, various electrical contacts can be made to achieve the desired electrical connections. For three-dimensional arrays, there are several ways in the art to make interconnects. For example, the gate electrode layers in the contact regions may be patterned in a stepped shape to form electrical contacts to the various gate electrode layers.

The memory device after the electrical contacts are formed is shown in FIG. 10 . As shown in FIG. 10, a dielectric layer 1025 (eg, oxide) may be formed over the device. In the dielectric layer 1025, electrical contacts 1027-1 to the common ground potential plane 1001w (and thus to the source/drain regions of all lowermost memory cells), to the respective gate electrode layers 1005, 1009, may be formed 1027-2, 1027-3, and electrical contacts 1027-4, 1027-5, 1027-6 to the source/drain regions of the respective uppermost memory cells. Such electrical contacts can be made by forming contact holes in a dielectric layer and filling them with a conductive material such as tungsten (W).

Thus, the memory device according to this embodiment is obtained. As shown in FIG. 10, the memory device may include multiple layers of memory cells (in this example, only two layers are shown), each layer of memory cells including an array of memory cells. Each memory cell includes a channel region opposite to the corresponding gate electrode layer and source/drain regions on both sides of the channel region. The memory cells in the same column-shaped active region extending in the vertical direction are vertically connected in a string, connected to the corresponding electrical contact at the upper end, and connected to the common ground potential plane at the lower end. The memory cells in each layer share the same gate electrode layer.

A certain memory cell layer can be selected by electrical contact to the gate electrode layer. In addition, through the source/drain contacts, a certain memory cell string can be selected.

In this example, electrical contacts are formed for the source/drain regions of each memory cell of the uppermost layer. The density of such source/drain contacts is greater due to the greater density of memory cells. According to another embodiment, electrodes arranged in rows (or columns) may be formed that are electrically connected to the source/drain regions of the lowermost memory cells, and columns arranged to be electrically connected to the source/drain regions of the uppermost memory cells may be formed (or row) array of electrodes. In this way, through the electrodes on the upper side and the electrodes on the lower side (crossing each other to form an array corresponding to the array of memory cells), a corresponding string of memory cells can be selected.

According to the embodiments of the present disclosure, since the doping concentrations at different regions can be individually adjusted, different doping profiles can be achieved. For example, the doping concentration of the first doping region may be about 1E16-1E18 cm ⁻³ , the doping concentration of the second doping region may be about 1E18-5E21 cm ⁻³ , the first doping region and the second doping region in the active region The doping concentration of the portion outside the doped region may be about 1E17-5E19 cm ⁻³ .

According to an embodiment of the present disclosure, in the normal direction of the storage gate dielectric stack, the active region may have a doping concentration profile. For example, the active region may include a region located inside the first doped region and having a higher doping concentration than in the first doped region. This distribution facilitates control of short channel effects. For example, the doping concentration in the first doped region may be about 1E16-3E18 cm ⁻³ , while the doping concentration in the region is about 1E17-2E19 cm ⁻³ .

11 and 12 illustrate flowcharts of some stages in a process for fabricating a memory device according to another embodiment of the present disclosure. Hereinafter, the difference between this embodiment and the above-described embodiment will be mainly described.

After forming the storage gate dielectric stack 1019 and semiconductor material 1021 in the recess as described above in connection with FIG. 9, instead of filling the hole with semiconductor material 1023, as shown in FIG. 11, the semiconductor may be formed along the inner walls of the hole Material 1023' (for its material and doping, see the description above for semiconductor material 1023). Thus, a hollow active region can be formed, the inner side of which can be filled with a dielectric layer 1029 (eg, oxide). Such a structure can be formed, for example, as follows. Specifically, on the structure shown in FIG. 9, a semiconductor material 1023' (eg, about 5-20 nm thick) may be formed in a substantially conformal manner, eg, by deposition, and then an oxide may be deposited. Subsequently, the deposited semiconductor material 1023' and oxide may be subjected to a planarization process such as CMP. The planarization process may stop at the hard mask layer 1015 .

Subsequent processing can be performed as described above, and details are not repeated here. Thus, the structure shown in FIG. 12 can be obtained. In this example, since the thickness of the active region on the inner wall of the hole (the dimension in the horizontal direction in the figure) is small, the source/drain regions S/D can extend over the entire thickness, effectively reducing resistance.

13 and 14 illustrate flowcharts of some stages in a process for fabricating a memory device according to yet another embodiment of the present disclosure. Hereinafter, the difference between this embodiment and the above-described embodiment will be mainly described.

In this embodiment, as shown in FIG. 13 , a diffusion barrier layer 1013 may be provided between each dopant source layer 1003 , 1007 , 1011 and each gate electrode layer 1005 , 1009 . For example, the diffusion barrier layer 1013 may include nitride with a thickness of about 1-3 nm. On the one hand, the diffusion barrier layer 1013 can inhibit undesired diffusion of dopants in the dopant source layer; on the other hand, the thickness of the diffusion barrier layer 1013 can also be used to control the diffusion of dopants into the channel region (diffusion The thicker the barrier layer 1013, the less impurities or dopants diffuse into the channel region). Subsequent processing can be performed as described above, and details are not repeated here. Thus, the structure shown in FIG. 14 can be obtained.

In addition, according to the embodiments of the present disclosure, a selection transistor may be added to the uppermost end and/or the lowermost end of the columnar active region, which will not be repeated here. This selection transistor can also be a vertical type device.

The memory device according to the embodiment of the present disclosure may be applied to various electronic devices. For example, a storage device may store various programs, applications, and data required for the operation of an electronic device. The electronic device may also include a processor in cooperation with the memory device. For example, a processor may operate an electronic device by allowing a program stored in a storage device. Such electronic devices are, for example, smart phones, computers, tablet computers (PCs), wearable smart devices, power banks, robots, smart chips, and the like.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (24)

1. A memory device, comprising:

a plurality of pillar-shaped active regions formed on the substrate and extending upward from the substrate; and

a plurality of gate electrode layers arranged on the substrate in sequence from bottom to top, spaced apart from each other and surrounding the respective columnar active regions, wherein each gate electrode layer faces each columnar active region via the memory gate dielectric stack,

the columnar active region comprises first doping regions opposite to the gate electrode layers and second doping regions located on two opposite sides of the first doping regions, and the doping characteristics in the first doping regions are different from the doping characteristics in the second doping regions.

2. The memory device of claim 1, wherein a doping concentration in the second doped region is higher than a doping concentration in the first doped region.

3. The memory device of claim 1, wherein a doping type in the first doped region is the same as or different from a doping type in the second doped region.

4. The storage device of any of claims 1-3, further comprising:

a dopant source layer between the gate electrode layers, wherein the dopant source layer comprises a dopant of the same type as the second doped region.

5. The memory device of claim 4, wherein the second doped region has a ring shape and an outer wall of the second doped region is an outer wall of the pillar-shaped active region.

6. The memory device of claim 4, further comprising: a diffusion barrier layer between each gate electrode layer and each dopant source layer.

7. The memory device of claim 4, wherein the dopant source layer comprises n-type doped phospho-or arseno-silicate glass, or p-type doped borosilicate glass, wherein the dopant is included at a concentration of 0.01% -10%.

8. The memory device of claim 1, wherein the gate electrode layer comprises doped polysilicon or metal.

9. The memory device of claim 1, wherein the semiconductor material in the pillar active regions is homogenous.

10. The memory device of claim 1, wherein a portion of the columnar active region where the first doped region is located protrudes outward relative to a remaining portion of the columnar active region, and a portion of the columnar active region outside the first doped region and the second doped region has a concentration higher than the first doped region and lower than the second doped region.

11. The memory device of claim 10, wherein the first doped region has a doping concentration of 1E16cm^-3-1E18cm^-3The doping concentration of the second doping region is 1E18cm^-3-5E21cm^-3The doping concentration of the part of the columnar active region outside the first doping region and the second doping region is 1E17cm^-3-5E19cm^-3。

12. The memory device of claim 1, wherein the pillar active region is hollow and filled with a dielectric.

13. The memory device of claim 1, wherein the storage gate dielectric stack comprises a first gate dielectric layer, a charge trapping layer, and a second gate dielectric layer stacked in sequence.

14. The memory device of claim 1, wherein a doping profile in the first doped region is substantially aligned with a doping profile in the second doped region.

15. The memory device of claim 1, wherein the columnar active region comprises a region inside the first doped region and having a higher doping concentration than in the first doped region in a normal direction of the memory gate dielectric stack.

16. The memory device of claim 15, wherein a doping concentration in the first doped region is 1E16cm^-3-3E18cm^-3。

17. The memory device of claim 15, wherein the doping concentration in the region is 1E17cm-³-2E19cm^-3。

18. A method of manufacturing a memory device, comprising:

providing an alternating stack of dopant source layers and gate electrode layers on a substrate, wherein the dopant source layers comprise a type of dopant;

forming a plurality of holes in the stack;

filling semiconductor material into the holes to form a columnar active region, and performing heat treatment to drive dopants into the semiconductor material from the dopant source layer, and forming a first doping region opposite to each gate electrode layer and second doping regions on two opposite sides of each first doping region in the columnar active region, wherein the doping characteristics in the first doping regions are different from the doping characteristics in the second doping regions; and

a storage gate dielectric stack is formed between the gate electrode layer and the semiconductor material.

19. The method of claim 18, further comprising: the gate electrode layer is selectively etched through the hole to be recessed,

wherein filling the hole with the semiconductor layer includes: filling the recess with a lightly doped semiconductor material through a hole; the hole is filled with a moderately doped semiconductor material.

20. The method of claim 19, wherein forming a storage gate dielectric stack comprises:

forming a storage gate dielectric stack on the inner wall of the hole before filling the lightly doped semiconductor material; and

after filling the lightly doped semiconductor material, the storage gate dielectric stack is selectively etched.

21. The method of claim 19, wherein a hollow, medium doped semiconductor material is formed along an inner wall of the hole, the method further comprising: the medium-doped semiconductor material is filled with a dielectric layer on the inside.

22. The method of claim 18, wherein providing alternating tiers further comprises:

a diffusion barrier layer is disposed between the gate electrode layer and the dopant source layer.

23. An electronic device comprising a memory device as claimed in any one of claims 1-17.

24. The electronic device of claim 23, comprising a smartphone, a computer, a wearable smart device, a mobile power source, a robot, a smart chip.

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