TW202027257A - Semiconductor structure and method for forming the same - Google Patents

Abstract

A semiconductor structure includes a plurality of stacks, a plurality of active pillars, and an insulating material. The stacks are separated from each other by a plurality of trenches. The active pillars are disposed in the trenches and separated from each other in each of the trenches. Each of the active pillars comprises two n-type heavily doped portions at two sides thereof. Each of the two n-type heavily doped portions extends in a substantially vertical direction. Each of the two n-type heavily doped portions connects corresponding two stacks of the plurality of stack. The insulating material is located in remaining spaces of the trenches between the active pillars. The insulating material is a silicon glass comprising an element which is applicable as a n-type dopant.

Description

Semiconductor structure and its forming method

This disclosure relates to a semiconductor structure and its forming method. The present disclosure particularly relates to a semiconductor structure including an n-type heavily doped portion extending in a substantially vertical direction and having a uniform doping concentration from top to bottom, and a method for forming the semiconductor structure.

For reasons such as reducing volume, reducing weight, increasing power density, and improving portability, three-dimensional (3D) semiconductor structures have been developed. Typically, a stack including multiple layers can be formed on a substrate and separated from each other by trenches with a high aspect ratio. In some types of 3D semiconductor structures, a doped portion extending in a vertical direction may be further configured in the trench. Such doped portions can be manufactured by a process of forming a polysilicon layer in a vertical configuration and a subsequent (ion) implantation process. However, since the implantation process is typically performed from above the overall structure, and these parts are vertically arranged in the trenches with high aspect ratio, it is difficult to obtain a uniform doping concentration in the vertical direction. Generally speaking, the doping concentration near the top is higher than the doping concentration near the bottom. This situation may cause electrical differences between devices near the top and devices near the bottom.

This disclosure is directed to a semiconductor structure and its forming method. According to the present disclosure, an n-type heavily doped portion extending in a substantially vertical direction and having a uniform doping concentration from top to bottom can be provided in the semiconductor structure.

According to some embodiments, the semiconductor structure includes a plurality of stacks, a plurality of active columnar elements, and an insulating material. The stacks are separated from each other by a plurality of trenches. The active columnar elements are arranged in the trenches and separated from each other in each of the trenches. The active columnar elements respectively include two n-type heavily doped portions on both sides of each of the active columnar elements. The n-type heavily doped portions respectively extend in a substantially vertical direction. The n-type heavily doped part respectively connects two corresponding stacks of the stacks. The insulating material is located in the remaining spaces between the active columnar elements in the trenches. The insulating material is a silicon glass that includes an element that can be used as an n-type dopant.

According to some embodiments, the method for forming such a semiconductor structure includes the following steps. First, provide an initial structure. The initial structure includes a plurality of stacks separated from each other by a plurality of trenches. A plurality of semi-finished active column elements are formed in the groove. The semi-finished active columnar element is separated from each other in each of the grooves. An insulating material is filled into the remaining spaces between the semi-finished active column elements in the trenches. The insulating material is a silicon glass that includes an element that can be used as an n-type dopant. Afterwards, by performing a thermal process for driving the element that can be used as n-type dopants into the semi-finished product of the active columnar device, a plurality of n-type heavily doped portions are formed between the semi-finished product of the active columnar device and the insulating material. .

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

Various embodiments will be described in more detail below in conjunction with the accompanying drawings. The accompanying drawings are only used for description and explanation purposes and not for limitation purposes. For clarity, the components may not be drawn according to actual scale. In addition, some elements and/or element symbols may be omitted from some drawings. It is expected that the elements and features in one embodiment can be advantageously incorporated into another embodiment without further elaboration.

The semiconductor structure according to the embodiment includes a plurality of stacks, a plurality of active columnar elements, and an insulating material. The stacks are separated from each other by a plurality of trenches. The active columnar elements are arranged in the trenches and separated from each other in each of the trenches. The active columnar elements respectively include two n-type heavily doped portions on two sides thereof. The n-type heavily doped portions respectively extend in a substantially vertical direction. The n-type heavily doped part respectively connects two corresponding stacks of the stacks. The insulating material is located in the remaining spaces between the active columnar elements in the trenches. The insulating material is a silicon glass that includes an element that can be used as an n-type dopant.

An example of this type of semiconductor structure is shown in Figure 1. For clarity, the semiconductor structure is shown as a 3D AND flash memory device (3D and flash memory device), and the insulating material in the region R is removed. However, it can be appreciated that the embodiments of the present disclosure are not limited thereto.

Please refer to FIG. 1, an exemplary semiconductor structure 100 includes a plurality of stacks 102. The stack 102 may respectively include a plurality of conductive strips 104 and a plurality of insulating strips 106 stacked alternately. The number of conductive strips 104 and the number of insulating strips 106 are not particularly limited. Although not shown in FIG. 1, the stack 102 may further include one or more other layers. The stack 102 is separated from each other by a plurality of trenches 108.

The semiconductor structure 100 further includes a plurality of active columnar elements 110. The active columnar element 110 is disposed in the trench 108 and separated from each other in each of the trenches 108. The active columnar element 110 includes two n-type heavily doped portions 112 on both sides thereof. The two n-type heavily doped portions 112 respectively extend in a substantially vertical direction. Here, the vertical direction means a direction perpendicular to a main surface of the semiconductor structure (for example, the upper surface of the substrate (not shown in FIG. 1) on which the stack 102 is formed). In the drawings, the vertical direction is the Z direction, and as shown in Figures 2A to 15A, the upper surface of the substrate extends in the X-Y plane. The term "substantially vertical direction" allows a slight deviation from the precise vertical direction which is acceptable in semiconductor devices. Such deviations may be the result of process limitations, for example. The two n-type heavily doped portions 112 are respectively connected to two corresponding stacks 102 in the stack 102. More specifically, on the X-Y plane, the n-type heavily doped portion 112 may extend in a direction perpendicular to the extending direction of the stack 102.

As an AND flash memory device, in the semiconductor structure 100, the active columnar device 110 may further include two memory layers 114, two channel layers 116, and an insulating layer 118, respectively. The two memory layers 114 are respectively disposed on the sidewalls of the two corresponding stacks 102. The two channel layers 116 are arranged between the two memory layers 114. The two channel layers 116 are respectively arranged on the sidewalls of the memory layer 114. The insulating layer 118 is disposed between the two channel layers 116. The two channel layers 116 and the insulating layer 118 are located between the two n-type heavily doped portions 112. Although not shown in FIG. 1, the active columnar element 110 may further include one or more other elements. For example, the active columnar element 110 may further include a contact plug disposed on the insulating layer 118, respectively. The contact plug undergoes p-type implantation. The active columnar element 110 may further include a p-type doped region disposed under the insulating layer 118, respectively.

Correspondingly, the n-type heavily doped portion 112 may include two n-type heavily doped portions 120 and an insulating portion 122 respectively. The two n-type heavily doped parts 120 are respectively arranged near the two corresponding stacks 102. The insulating part 122 is disposed between the two n-type heavily doped parts 120. More specifically, the positions of the two n-type heavily doped portions 120 correspond to the positions of the two channel layers 116, and the position of the insulating portion 122 corresponds to the position of the insulating layer 118. According to some embodiments, the contact plug (not shown in Figure 1) has a first doping concentration, the two n-type heavily doped parts 120 have a second doping concentration, and the second doping concentration is higher than The first doping concentration.

As an AND flash memory device, in the semiconductor structure 100, a plurality of memory cells can be defined at the intersection of the conductive strip 104 and the channel layer 116. According to some embodiments, the conductive strip 104 may be a word line, and for each of the active column elements 110, one of the two n-type heavily doped portions 112 is electrically connected to the bit Line, the other is electrically connected to the source line. In the semiconductor structure 100, the active columnar elements 110 are arranged in an alternating manner. Correspondingly, bit line pairs, such as bit lines BL11 and BL12 and BL21 and BL22, and source line pairs, such as source lines SL11 and SL12 and SL21 and SL22 are provided. However, it can be appreciated that other types of configurations can be applied to the active columnar element 110 and the corresponding bit line and source line.

The semiconductor structure 100 further includes an insulating material 124. The insulating material 124 is located in the remaining spaces between the active columnar elements 110 in the trenches 108. The insulating material 124 is a silicon glass that includes an element that can be used as an n-type dopant. For example, the silicon glass may be phosphorous silicon glass (PSG) or arsenic silicon glass (ASG).

The forming method of the semiconductor structure according to the embodiment includes the following steps. First, provide an initial structure. The initial structure includes a plurality of stacks separated from each other by a plurality of trenches. A plurality of semi-finished active column elements are formed in the groove. The semi-finished active columnar element is separated from each other in each of the grooves. An insulating material is filled into the remaining spaces between the semi-finished active column elements in the trenches. The insulating material is a silicon glass that includes an element that can be used as an n-type dopant. Afterwards, by performing a thermal process for driving the element that can be used as n-type dopants into the semi-finished product of the active columnar device, a plurality of n-type heavily doped portions are formed between the semi-finished product of the active columnar device and the insulating material. .

The different stages of the semiconductor structure in this type of method are shown in Figures 2A~2B to 15A~15B, where the figures indicated by "A" and the figures indicated by "B" are shown respectively The perspective view and the corresponding cross-sectional view, the cross-sectional view is along the line CC" in the corresponding drawing indicated by "A". For clarity, only a stack and two adjacent grooves are shown. The semiconductor structure is shown as a 3D AND flash memory device. However, it can be appreciated that the embodiments of the disclosure are not limited thereto.

Please refer to Figures 2A~2B to provide an initial structure 200. The initial structure 200 includes a substrate 202. The initial structure 200 further includes a plurality of stacks 204, which can be formed on the substrate 202. The stack 204 may include a plurality of conductive strips 206 and a plurality of insulating strips 208, respectively, which are alternately stacked on each other. The conductive strip 206 may be formed of doped polysilicon or any other suitable material. The insulating strip 208 may be formed of silicon oxide. In some embodiments, the stack 204 further includes a stress compensation layer 210 located above the conductive strip 206 and the insulating strip 208. The stress compensation layer 210 compensates for the tensile stress and prevents the stack 204 with a high aspect ratio from collapsing or bending. The stress compensation layer 210 may be formed of silicon nitride. The stack 204 is separated from each other by a plurality of trenches 212.

Referring to FIGS. 3A to 3B, an initial memory layer 214 is formed on the initial structure 200 in a conformal manner. The initial memory layer 214 can be a BE-SONOS (energy gap engineering silicon-oxide-nitride-oxide-silicon) layer, ONONO (oxide-nitride-oxide-nitride-oxide) layer, or any other Suitable layer.

Referring to FIGS. 4A to 4B, an initial channel layer 216 is formed on the initial memory layer 214 in a conformal manner. The initial channel layer 216 may be formed of polysilicon. The initial channel layer 216 includes a plurality of gate control regions 218 corresponding to the conductive strips 206, as shown in FIG. 4B.

Please refer to FIGS. 5A to 5B. Optionally, p-type dopants may be used to implant the initial channel layer 216 at the bottom of the trenches 212. Thus, a plurality of p-type doped regions 220 are formed. This step ensures that the bottom part of the channel is p-type doped, which can reduce the leakage path. The p-type doped region 220 may be further cut at a subsequent stage (for example, the stage described with reference to FIGS. 12A to 12B), and form the active columnar element 110 disposed under the insulating layer 118 with reference to FIG. 1. p-type doped region.

Referring to FIGS. 6A to 6B, a plurality of insulating layers 222 are respectively formed in the remaining space of the trench in a corresponding manner. The insulating layer 222 may be formed of oxide. Then, a planarization process can be performed, as shown in FIGS. 7A to 7B. The planarization process is terminated at the portion of the initial memory layer 214 on the stack 204. The planarization process can be a chemical mechanical planarization (CMP) process, an etching back process, or any other suitable planarization process.

Please refer to FIGS. 8A to 8B to remove the top part of the insulating layer 222. Next, referring to FIGS. 9A-9B, an intrinsic material 224, such as polysilicon, is filled into the space created by the step of removing the top portion of the insulating layer 222. As shown in FIGS. 9A-9B, the intrinsic material 224 can form a layer on the semiconductor structure. Therefore, a planarization process can be performed, as shown in FIGS. 10A to 10B. The planarization process also ends at the portion of the initial memory layer 214 on the stack 204. Please refer to Figures 11A to 11B for an implantation process using p-type dopants. In particular, the p-type dopant is used to implant the intrinsic material 224 (polysilicon). The p-type dopant may be, but is not limited to, boron (B). According to some embodiments, the doping concentration of the polysilicon implanted with p-type dopants may fall on the order of 10 ¹⁵ cm ⁻³ . Thus, a plurality of contact plugs 226 of the semi-finished products of the active columnar elements are formed. The contact plug 226 provides a sufficient thickness of the silicon part for the landing of the contact. The implantation process using p-type dopants can provide p-type doped contact plugs 226, especially p-type heavily doped contact plugs 226, which can reduce plug resistance and avoid punch through. )occur.

Next, referring to FIGS. 12A to 12B, cut at least the part of the initial channel layer 216 and the insulating layer 222 in each of the trenches. In this way, a plurality of semi-finished products 228 of active columnar elements are formed in the trench 212. In each of the trenches 212, the semi-finished product 228 of the active columnar element is separated from each other. The semi-finished active column element 228 may be but not limited to be arranged in an alternating manner. The opening formed by the cutting step may extend into the substrate 202, as shown in FIG. 12B. Alternatively, the openings may terminate in the initial memory layer 214 without extending to the substrate 202.

Referring to FIGS. 13A to 13B, an insulating material 230 is filled in the remaining spaces between the semi-finished active column elements 228 in the trenches 212 (that is, the openings formed in the previous stage). The insulating material is a silicon glass that includes an element that can be used as an n-type dopant. For example, the silica glass can be phosphosilicate glass (PSG) or arsenic silica glass (ASG). In other words, the elements that can be used as n-type dopants in silicon glass are phosphorus (P) or arsenic (As). In some embodiments, PSG is preferred because the phosphorus in PSG has a higher thermal diffusion rate than arsenic in ASG. According to some embodiments, the doping concentration of the polysilicon implanted with p-type dopants in the stage described with reference to FIGS. 8A to 8B is lower than that in the subsequent thermal process when the insulating material 230 is driven to the active pillar This type of semi-finished product 228 can be applied as a doping concentration of the n-type dopant element, so that the cut initial channel layer 216 and the contact plug 226 near the insulating material 230 are formed after the thermal process The n-type heavily doped portion 232 (shown in Figures 14A to 14B). For example, when the doping concentration of polysilicon implanted with p-type dopants falls on the order of 10 ¹⁵ cm ^-3 , the driving from the insulating material to the semi-finished product of the active columnar element can be applied as n-type doping. The doping concentration of impurities can be equal to or higher than 5´10 ²⁰ cm ^-3 . Correspondingly, in the insulating material 230, the doping concentration of the element applicable as an n-type dopant is equal to or higher than 5´10 ²⁰ cm ^-3 .

Please refer to Figs. 14A to 14B, by performing a thermal process in which elements that can be used as n-type dopants are driven into the semi-finished product 228 of the active columnar device, a plurality is formed between the semi-finished product 228 of the active columnar device and the insulating material 230 N-type heavily doped portions 232. In this way, the active columnar element described with reference to FIG. 1 can be formed. The element that can be applied as n-type dopant can be driven into the undoped or doped polysilicon part of the semi-finished product 228 of the active columnar element by a thermal process, because it tends to stay more than in silicon glass. In polysilicon. According to some embodiments, thermal process may be performed at 950 ^o C 30 min. It can be appreciated that higher temperatures and/or longer heating times can be used. As mentioned above, the doping concentration of polysilicon implanted with p-type dopants is lower than the doping concentration of elements that can be used as n-type dopants, which are driven from the insulating material to the semi-finished active columnar device. Next, the cut initial channel layer 216 and the part of the contact plug 226 close to the insulating material 230 form an n-type heavily doped portion 232 after the thermal process, as shown in FIGS. 14A-14B.

Referring to FIGS. 15A-15B, a plurality of contacts 234 can be formed on the n-type heavily doped portions 232 respectively. The two n-type heavily doped portions 232 of each active columnar element can be used as the source region and the drain region, respectively, and the contact 234 thereon can be used to provide an electrical connection to the source to be arranged above the structure Line and bit line (as shown in Figure 1). It can be understood that after the stage shown in FIGS. 15A to 15B, some further processes can be performed, such as the process of forming bit lines and source lines.

According to the present disclosure, the dopants used in the implantation process of the n-type heavily doped portion extending in a substantially vertical direction are implanted from a lateral source (that is, including an applicable n-type Dopant elements of silicon glass) provided. Thus, a uniform doping concentration can be obtained in the vertical direction. The silicon glass can be used to replace the insulating material traditionally used in semiconductor structures to isolate vertically extending components. Therefore, the above-mentioned manufacturing process can be easily performed in a self-aligned and controllable manner without much additional cost. In addition, these processes are compatible with general processes of semiconductor devices.

The exemplary 3D AND flash memory device and the exemplary forming method thereof can be used in various applications, especially those applications in which a doped portion with a uniform doping concentration in the vertical direction is strongly required. One example is the field of AI memory applications. Furthermore, although the above embodiments are exemplarily directed to 3D memory devices, it can be appreciated that the concept of the present disclosure can be applied to other semiconductor structures that require a uniform n-type heavily doped portion extending in a substantially vertical direction .

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100: semiconductor structure 102: Stack 104: Conductive strip 106: insulation strip 108: groove 110: Active columnar element 112: n-type heavily doped part 114: memory layer 116: Channel layer 118: Insulation layer 120: n-type heavily doped site 122: Insulation part 124: insulating material 200: initial structure 202: substrate 204: Stack 206: conductive strip 208: Insulation tape 210: Stress compensation layer 212: groove 214: Initial Memory Layer 216: initial channel layer 218: Gate Control Area 220: p-type doped region 222: Insulation layer 224: Intrinsic Materials 226: Contact plug 228: Semi-finished products of active columnar components 230: insulating material 232: n-type heavily doped part 234: Contact BL11, BL12, BL21, BL22: bit lines SL11, SL12, SL21, SL22: source line R: area

Figure 1 shows an exemplary semiconductor structure according to an embodiment. FIGS. 2A to 2B to 15A to 15B show various stages of the semiconductor structure in the process of an exemplary method for forming a semiconductor structure according to an embodiment.

100: semiconductor structure

102: Stack

104: Conductive strip

106: insulation strip

108: groove

110: Active columnar element

112: n-type heavily doped part

114: memory layer

116: Channel layer

118: Insulation layer

120: n-type heavily doped site

122: Insulation part

124: insulating material

BL11, BL12, BL21, BL22: bit lines

SL11, SL12, SL21, SL22: source line

R: area

Claims (10)

A semiconductor structure including: Multiple stacks, separated from each other by multiple grooves; A plurality of active columnar elements are arranged in the grooves and separated from each other in each of the grooves, wherein the active columnar elements are respectively located on two sides of each of the active columnar elements The side includes two n-type heavily doped portions, the n-type heavily doped portions respectively extend in a substantially vertical direction, and the n-type heavily doped portions are respectively connected to two corresponding stacks in the stacks ;as well as An insulating material is located in the remaining spaces between the active columnar elements in the trenches, wherein the insulating material is a silicon glass, and the silicon glass includes an element that can be applied as an n-type dopant. As the semiconductor structure described in item 1 of the scope of patent application, The stacks respectively include a plurality of conductive strips and a plurality of insulating strips stacked alternately; The active columnar elements further include: Two memory layers are respectively arranged on the two corresponding stacked sidewalls; Two channel layers are arranged between the two memory layers, wherein the two channel layers are respectively arranged on the sidewalls of the two memory layers; and An insulating layer arranged between the two channel layers; Wherein the two channel layers and the insulating layer are located between the two n-type heavily doped portions; and A plurality of memory cell systems are defined at the intersections of the conductive strips and the channel layers. In the semiconductor structure described in item 2 of the scope of patent application, the active columnar elements further include: A contact plug is arranged on the insulating layer; and A p-type doped region is arranged under the insulating layer. In the semiconductor structure described in item 3 of the scope of patent application, the n-type heavily doped portions respectively include: Two n-type heavily doped parts are respectively arranged near the two corresponding stacks; and An insulating part is arranged between the two n-type heavily doped parts. The semiconductor structure according to claim 4, wherein the contact plug undergoes p-type implantation and has a first doping concentration, and the two n-type heavily doped parts have a second doping concentration, And the second doping concentration is higher than the first doping concentration. In the semiconductor structure described in item 1 of the scope of patent application, the silicon glass is phosphosilicate glass (PSG) or arsenic silica glass (ASG). A method for forming a semiconductor structure includes: Providing an initial structure, the initial structure including a plurality of stacks separated from each other by a plurality of trenches; Forming a plurality of semi-finished products of active columnar elements in the grooves, wherein the semi-finished products of active columnar elements are separated from each other in each of the grooves; An insulating material is filled in the remaining spaces between the semi-finished active columnar devices in the trenches, wherein the insulating material is a silicon glass including an element that can be used as an n-type dopant ;as well as By performing a thermal process for driving the element that can be applied as n-type dopants into the semi-finished products of active columnar devices, a plurality of n-type weights are formed between the semi-finished products of active columnar devices and the insulating material. Doped part. According to the method for forming a semiconductor structure as described in item 7 of the scope of patent application, the step of forming the semi-finished products of the active columnar elements includes: Forming an initial memory layer in a conformal manner on the initial structure; Forming an initial channel layer on the initial memory layer in a conformal manner; Using p-type dopants to implant the initial channel layer at the bottom of the trenches; Forming a plurality of insulating layers in the remaining spaces of the trenches in a corresponding manner; Performing a planarization process, the planarization process is terminated at the portion of the initial memory layer on the stacks; Removing a top part of the insulating layers, and forming a plurality of contact plugs of the semi-finished products of the active columnar elements; and Cutting at least a portion of the initial channel layer and the insulating layers located in each of the trenches. According to the method for forming a semiconductor structure described in item 8 of the scope of the patent application, a doping concentration of the polysilicon implanted with p-type dopants falls on the order of 10 ¹⁵ cm ^-3 , and the insulating material is driven to the A doping concentration of the element that can be used as n-type dopant in some semi-finished active column elements is equal to or higher than 5´10 ²⁰ cm ^-3 , so that the initial channel layer and the contacts after cutting The portion of the plug close to the insulating material forms the n-type heavily doped portions after the thermal process. According to the method for forming a semiconductor structure described in item 8 of the scope of patent application, the step of forming the contact plugs includes: Filling polysilicon into the space created by the step of removing the top portion of the insulating layers; and An implantation process is performed using p-type dopants.

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