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TWI623069B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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Publication number
TWI623069B
TWI623069B TW105130120A TW105130120A TWI623069B TW I623069 B TWI623069 B TW I623069B TW 105130120 A TW105130120 A TW 105130120A TW 105130120 A TW105130120 A TW 105130120A TW I623069 B TWI623069 B TW I623069B
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Taiwan
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substrate
thickness
chip package
item
manufacturing
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TW105130120A
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TW201712818A (zh
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關欣
劉滄宇
李柏漢
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精材科技股份有限公司
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Abstract

本發明揭露一種晶片封裝體，包括一第一基底。第一基底內包括一感測區或元件區。第一基底接合於一第二基底上，且電性連接至第二基底。第二基底的厚度與第一基底的厚度的比值為2至8。本發明亦揭露一種晶片封裝體的製造方法。根據本發明的實施例，晶片封裝體的尺寸能夠進一步縮小。

Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝技術，特別為有關於一種薄化的晶片封裝體及其製造方法。
晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
製作晶片封裝體的過程包括將晶片接合於電路板上。然而，在接合的過程中晶片被取起及施壓，因此晶片需要具有足夠的厚度，以避免晶片遭受物理性破壞(例如，晶片出現破裂)，如此一來晶片封裝體的尺寸難以進一步縮小。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體，包括一第一基底。第一基底內包括一感測區或元件區。第一基底接合於一第二基底上，且電性連接至第二基底。第二基底的厚度與第一基底的厚度的比值為2至8。
本發明實施例係提供一種晶片封裝體的製造方法，包括提供一第一基底。第一基底內包括一感測區或元件 區。將第一基底接合於第二基底上。第一基底電性連接至第二基底。第二基底的厚度與第一基底的厚度的比值為2至8。
100‧‧‧半導體基底
100a‧‧‧第一表面
100b‧‧‧第二表面
110‧‧‧晶片區
120‧‧‧感測區或元件區
130‧‧‧絕緣層
140‧‧‧導電墊
150‧‧‧光學部件
160‧‧‧第一基底
170‧‧‧支撐基底
180‧‧‧黏著層
185‧‧‧子結構
190‧‧‧第二基底
200‧‧‧接觸墊
210‧‧‧導電結構
210a‧‧‧末端
D1、D2、D3‧‧‧距離
T1‧‧‧初始厚度
T1’、T2、T3‧‧‧厚度
第1A至1F圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System，MEMS)、生物辨識元件(biometric device)、微流體系統(micro fluidic systems)、或利用熱、光線、 電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package，WSP)製程對影像感測元件、發光二極體(light-emitting diodes，LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、指紋辨識器(fingerprint recognition device)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體或系統級封裝(System in Package，SIP)之晶片封裝體。
以下配合第1A至1F圖說明本發明一實施例之晶片封裝體的製造方法，其中第1A至1F圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
請參照第1A圖，提供一半導體基底100，其具有一第一表面100a及與其相對的一第二表面100b，且包括複數晶片區110。為簡化圖式，此處僅繪示出一完整的晶片區及與其相鄰的晶片區的一部分。在某些實施例中，半導體基底100可為 一矽基底或其他半導體基底。在某些其他實施例中，半導體基底100為一矽晶圓，以利於進行晶圓級封裝製程。
在某些實施例中，每一晶片區110的半導體基底100內具有一感測區或元件區120。感測區或元件區120可鄰近於第一表面100a，且感測區或元件區120內包括一感測元件。在某些實施例中，感測區或元件區120內包括感光元件或其他適合的光電元件。在某些其他實施例中，感測區或元件區120內可包括感測生物特徵的元件(例如，一指紋辨識元件)、感測環境特徵的元件(例如，一溫度感測元件、一溼度感測元件、一壓力感測元件、一電容感測元件)或其他適合的感測元件。
半導體基底100的第一表面100a上具有一絕緣層130。一般而言，絕緣層130可由層間介電層、金屬間介電層及覆蓋之鈍化層組成。為簡化圖式，此處僅繪示出單層絕緣層130。在某些實施例中，絕緣層130可包括無機材料，例如氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合或其他適合的絕緣材料。
在某些實施例中，每一晶片區110的絕緣層130內具有一個或一個以上的導電墊140。在某些實施例中，導電墊140可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明。在某些實施例中，每一晶片區110的絕緣層130內包括一個或一個以上的開口，露出對應的導電墊140。在某些實施例中，感測區或元件區120內的感測元件可透過半導體基底100內的內連線結構(未繪示)而與導電墊140電性連接。
在某些實施例中，可依序進行半導體裝置的前段(front end)製程(例如，在半導體基底100內製作感測區或元件區120及後段(back end)製程(例如，在半導體基底100上製作絕緣層130、內連線結構及導電墊140)來製作前述結構。換句話說，以下晶片封裝體的製造方法係用於對完成後段製程的基底進行後續的封裝製程。
在某些實施例中，每一晶片區110內還具有一光學部件150設置於半導體基底100的第一表面100a上，且對應於感測區或元件區120。在某些實施例中，光學部件150可為微透鏡陣列、濾光層、其組合或其他適合的光學部件。
在某些實施例中，半導體基底100、絕緣層130及光學部件150共同構成一第一基底160，如第1A圖所示。在某些其他實施例中，第一基底160可僅由半導體基底100及絕緣層130所構成。在某些其他實施例中，除了半導體基底100及絕緣層130，第一基底160可能包括其他適合的部件。在某些實施例中，第一基底160的初始厚度T1為大約735μm或大約750μm。在某些其他實施例中，第一基底160可具有其他適合的厚度。
請參照第1B圖，將一支撐基底170貼附於第一基底160的前側上。舉例來說，導電墊140及光學部件150鄰近於第一基底160的前側，且導電墊140及光學部件150位於半導體基底100與支撐基底170之間。
在某些實施例中，支撐基底170的厚度T2為大約400μm或大於400μm。在某些實施例中，支撐基底170的平面尺寸大致上相同於半導體基底100的平面尺寸。在某些實施例 中，支撐基底170由玻璃、半導體材料(例如，矽)或其他適合的支撐基底材料所構成。在某些實施例中，支撐基底170的材料相同於半導體基底100的材料。在某些其他實施例中，支撐基底170的材料不同於半導體基底100的材料。
在某些實施例中，支撐基底170透過一黏著層180貼附於第一基底160上。在某些實施例中，黏著層180為雙面膠材或其他適合的黏著材料。再者，黏著層180包括可移除性材料，舉例來說，黏著層180由可透過加熱而消除黏性的材料所構成。
請參照第1C圖，以位於第一基底160前側的支撐基底170作為承載基板，對第一基底160的背側進行薄化製程，以減少第一基底160的初始厚度T1。
具體而言，對貼附有支撐基底170之半導體基底100的第二表面100b進行薄化製程，進而減少半導體基底100的厚度。在某些實施例中，支撐基底170為第一基底160提供支撐的功能，且支撐基底170具有足夠的厚度T2，因此有利於盡可能減少第一基底160的厚度。在某些實施例中，薄化製程包括蝕刻製程、銑削(milling)製程、磨削(grinding)製程、研磨(polishing)製程或其他適合的製程。
在某些實施例中，第一基底160經薄化而減少了大約80%的初始厚度T1至大約95%的初始厚度T1。第一基底160的初始厚度T1經薄化後變成厚度T1’，且支撐基底170的厚度T2大於第一基底160的厚度T1’。
在某些實施例中，厚度T1’小於200μm。在某些實 施例中，厚度T1’介於大約50μm至大約150μm之間。在某些實施例中，厚度T1’介於大約50μm至大約100μm之間。在某些其他實施例中，厚度T1’小於50μm。在某些實施例中，初始厚度T1與厚度T1’的比值介於大約5至大約15的範圍內。在某些實施例中，厚度T2與厚度T1’的比值大於2。在某些實施例中，厚度T2與厚度T1’的比值介於大約2.6至大約8的範圍內。
接著，沿著晶片區110之間的切割道SC切割第一基底160及支撐基底170，以形成複數獨立的子結構(substructure)185，如第1D圖所示。子結構185為附有載板的晶片(chip)/晶粒(die)。子結構185亦可稱為感測晶片/晶粒。
在某些實施例中，支撐基底170由易於切割的材料(例如，矽)所構成。在某些實施例中，支撐基底170的材料相同於半導體基底100的材料，以有助於切割製程的進行。
請參照第1D圖，每個子結構185包括薄化的第一基底160及貼附於前側的支撐基底170。在某些實施例中，子結構185的厚度介於大約450μm至大約550μm的範圍內。在某些實施例中，子結構185的厚度可能介於大約400μm至大約450μm的範圍內。在某些其他實施例中，子結構185的厚度大於大約550μm。
請參照第1E圖，將子結構185接合(mount)於一第二基底190上，使得第二基底190位於第一基底160的背側，且其中第一基底160位於支撐基底170與第二基底190之間。在某些實施例中，透過一黏著層(未繪示)將半導體基底100的第二表面100b貼附於第二基底190，使得半導體基底100位於支撐基底 170與第二基底190之間。
在某些實施例中，第二基底190為電路板或其他適合的元件。第二基底190可能為印刷電路板(printed circuit board，PCB)。再者，第二基底190內具有接觸墊(contact pad)200鄰近於上表面。在某些實施例中，第二基底190的厚度T3介於大約300μm至大約400μm的範圍內。在某些其他實施例中，第二基底190可具有其他適合的厚度。
在接合的過程中，透過點膠製程在子結構185上形成黏著層，並將子結構185取起及放置於第二基底190上，接著對子結構185施加向下的力量，以將子結構185與第二基底190之間的黏著層均勻地壓散。由於子結構185內包括足夠厚的支撐基底170，因此在上述接合的過程中可防止第一基底160遭受物理性破壞。特別是第一基底160的厚度極小的情況下，能夠有效避免第一基底160出現破裂、彎曲或翹曲的問題。換句話說，由於子結構185內包括具有足夠厚度的支撐基底170，因此可以盡可能降低第一基底160的厚度而不會對第一基底160造成損壞，如此一來能夠進一步縮小晶片封裝體的尺寸。
此外，支撐基底170亦可防止第一基底160被汙染。舉例來說，支撐基底170覆蓋導電墊140及光學部件150，因此支撐基底170能夠保護導電墊140及光學部件150在各個製程期間不被灰塵或顆粒汙染，以顯著提升晶片封裝體的可靠度及品質。
在某些實施例中，支撐基底170的厚度T2與第一基底160的厚度T1’的比值應大致上相同或大於大約2。在某些情 況下，如果厚度T2與厚度T1’的比值小於大約2，可能增加第一基底160出現破裂、彎曲或翹曲問題的機率。然而，本發明並不限定於此，在某些其他情況下，厚度T2與厚度T1’的比值有可能小於2。
在某些實施例中，支撐基底170的厚度T2與第一基底160的厚度T1’的比值應介於大約2.6至大約8的範圍內。在某些情況下，如果厚度T2與厚度T1’的比值大於大約8，可能會增加沿著切割道SC切割第一基底160及支撐基底170的製程難度。然而，本發明並不限定於此，在某些其他情況下，厚度T2與厚度T1’的比值有可能大於8。
請參照第1F圖，將支撐基底170及黏著層180自第二基底190上的子結構185去除，進而露出光學部件150及導電墊140。在某些實施例中，經由加熱來消除黏著層180的黏性，進而將支撐基底170分離(debond)及移除。例如，可利用紫外光(ultraviolet，UV)來進行加熱。在去除支撐基底170及黏著層180之後，子結構185的厚度變成介於大約50μm至大約150μm之間或甚至小於50μm。
接著，在第二基底190上形成複數導電結構210。在某些實施例中，導電結構210為焊線或其他適合的導電結構。可透過打線接合(wire bonding)製程，將導電結構210自接觸墊200延伸至導電墊140，以將半導體基底100與第二基底190電性連接。
在某些實施例中，晶片封裝體具有極薄的厚度，特別是具有薄化的第一基底160，使得導電結構210的整體高度 也隨之降低。薄化的第一基底160的厚度T1’至少小於200μm，例如厚度T1’介於大約50μm至大約150μm之間，厚度T1’也可能小於50μm。因此，第二基底190的厚度T3與第一基底160的厚度T1’的比值介於大約2至大約8的範圍內。
在某些實施例中，厚度T3與厚度T1’的比值應大致上相同或大於大約2。在某些情況下，如果厚度T3與厚度T1’的比值小於大約2，可能大幅增加第一基底160出現破裂、彎曲或翹曲問題的機率。
在某些實施例中，在接合過程中利用支撐基底170承載極薄的第一基底160，藉此能夠使得厚度T3與厚度T1’的比值大致上相同或小於大約8。在某些情況下，如果沒有利用支撐基底170承載第一基底160，厚度T3與厚度T1’的比值將會大於8，因而難以降低晶片封裝體的尺寸。然而，厚度T3與厚度T1’的比值並不限定於此。
在某些實施例中，第二基底190與導電墊140的距離D1大於第二基底190與感測區或元件區120的距離D2，且距離D1小於第二基底190與導電結構210位於導電墊140的末端210a之間的距離D3，如第1F圖所示。
在某些實施例中，距離D1小於200μm，例如距離D1介於大約50μm至大約150μm的範圍內，距離D1也可能小於50μm。
在某些實施例中，距離D2遠小於200μm，例如距離D2介於大約25μm至大約75μm的範圍內，距離D2也可能小於25μm。
在某些實施例中，距離D3至少小於200μm，例如距離D3介於大約50μm至大約150μm的範圍內，距離D3也可能小於50μm。
可以理解的是，雖然第1A至1F圖的實施例描述的是具有光學感測裝置之晶片封裝體的製造方法，然而本發明晶片封裝體的製造方法亦可適用於其他類型的晶片封裝體，而不限定於此。
一般而言，在薄化基底時，僅以厚度極小的膠帶在薄化的過程中暫時性地保護基底，且為了避免後續在進行接合時基底出現破裂，基底的厚度不能變得太薄，因此導致晶片封裝體的尺寸受到限制。
根據本發明的上述實施例，利用暫時性支撐基底提供結構強度，有利於協助晶圓基底的薄化及切割，也進一步協助晶片基底與電路板的接合，因此可在不破壞晶片基底的情況下大幅減少晶片基底的厚度，如此一來能夠更進一步地降低晶片封裝體的尺寸。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。

Claims (20)

  1. 一種晶片封裝體，包括：一第一基底，其中該第一基底內包括一感測區或元件區；以及一第二基底，其中該第一基底接合於該第二基底上且電性連接至該第二基底，且該第一基底之遠離該第二基底的一表面完全暴露出來，且其中該第二基底的一厚度與該第一基底的一厚度的比值為2至8。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該第一基底的該厚度為50μm至150μm。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該第二基底的該厚度為300μm至400μm。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該第二基底為一電路板。
  5. 如申請專利範圍第1項所述之晶片封裝體，更包括一導電結構，其中該導電結構位於該第一基底上，且將該第一基底電性連接至該第二基底。
  6. 如申請專利範圍第5項所述之晶片封裝體，其中該第二基底與位於該第一基底上的該導電結構之間的一距離為50μm至150μm。
  7. 如申請專利範圍第1項所述之晶片封裝體，其中該第一基底具有一前側及一背側，該第二基底位於該第一基底的該背側，且其中該第一基底內更包括一導電墊，該導電墊鄰近於該前側。
  8. 如申請專利範圍第7項所述之晶片封裝體，其中該第二基底與該導電墊之間的一距離為50μm至150μm。
  9. 一種晶片封裝體的製造方法，包括：提供一第一基底，其中該第一基底內包括一感測區或元件區；以及將該第一基底接合於一第二基底上，其中該第一基底電性連接至該第二基底，且該第一基底之遠離該第二基底的一表面完全暴露出來，且其中該第二基底的一厚度與該第一基底的一厚度的比值為2至8。
  10. 如申請專利範圍第9項所述之晶片封裝體的製造方法，其中該第一基底的該厚度為50μm至150μm。
  11. 如申請專利範圍第9項所述之晶片封裝體的製造方法，其中該第二基底的該厚度為300μm至400μm。
  12. 如申請專利範圍第9項所述之晶片封裝體的製造方法，其中該第一基底具有一前側及一背側，該第二基底位於該第一基底的該背側，且其中該第一基底內更包括一導電墊，該導電墊鄰近於該前側。
  13. 如申請專利範圍第9項所述之晶片封裝體的製造方法，其中提供該第一基底的步驟包括將一支撐基底貼附於該第一基底上，且該支撐基底的一厚度大於該第一基底的該厚度。
  14. 如申請專利範圍第13項所述之晶片封裝體的製造方法，其中該支撐基底的該厚度與該第一基底的該厚度的比值大於2。
  15. 如申請專利範圍第13項所述之晶片封裝體的製造方法，其中該支撐基底由玻璃或半導體材料所構成。
  16. 如申請專利範圍第13項所述之晶片封裝體的製造方法，其中提供該第一基底的步驟更包括對貼附有該支撐基底的該第一基底進行薄化製程，以得到該第一基底的該厚度。
  17. 如申請專利範圍第16項所述之晶片封裝體的製造方法，其中在進行薄化製程之前該第一基底具有一初始厚度，該初始厚度與該第一基底的該厚度之比值為5至15。
  18. 如申請專利範圍第13項所述之晶片封裝體的製造方法，其中提供該第一基底的步驟更包括對該第一基底及該支撐基底進行切割製程。
  19. 如申請專利範圍第13項所述之晶片封裝體的製造方法，其中將該第一基底接合於該第二基底上的步驟包括將貼附有該支撐基底的該第一基底接合於該第二基底上，且其中該第一基底位於該支撐基底與該第二基底之間。
  20. 如申請專利範圍第19項所述之晶片封裝體的製造方法，更包括在將貼附有該支撐基底的該第一基底接合於該第二基底上之後去除該支撐基底。
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