TWI599281B - Package carrier and method for manufacturing same - Google Patents

Description

Package carrier board and manufacturing method thereof

The invention relates to a package carrier and a manufacturing method thereof.

In the existing package carrier technology, a package carrier in which a resistor and a capacitor are embedded has been developed. A package carrier having an embedded capacitor resistor can be obtained by mounting a passive component such as a resistor or capacitor on the surface of the package carrier or in the inner layer of the package carrier. The package carrier with the embedded capacitor resistor component only needs to assemble a small number of capacitor resistor components, and is advantageous for reducing the size of the package carrier.

However, in such a package carrier having embedded capacitors and resistor elements, through-hole conduction is usually adopted. Since the operating capacitance and resistance of the chip generate heat, the via design is not easy to conduct heat to the motherboard, which may affect the package loading. The function of the board and shorten the service life of the package carrier. Moreover, the use of through holes limits the wiring density of the package carrier, which is disadvantageous for further reducing the size of the components.

In view of this, the present invention provides a package carrier board having a good heat dissipation effect and a small size, and a method of fabricating the package carrier board.

A method for manufacturing a package carrier board, comprising the following steps: Providing a capacitor substrate having a first copper foil layer and a second copper foil layer on opposite sides of the capacitor substrate; etching the first copper foil layer and the second copper foil layer to form the first capacitor circuit layer and the second capacitor circuit layer a capacitor unit; a first insulating layer, a resistor substrate and a third copper foil layer are sequentially formed on the first capacitor circuit layer, and a second insulating layer and a fourth copper foil layer are formed under the second capacitor circuit layer to obtain a capacitor embedded therein a substrate; forming a blind via on the substrate, and plating the blind via to form a conductive pillar, wherein the third copper foil layer and the fourth copper foil layer respectively pass through the conductive pillar and the first capacitor circuit layer and the second capacitor circuit layer Conducting; etching the third copper foil layer, the fourth copper foil layer, and the resistor substrate to form the first conductive wiring layer and the second wiring circuit layer and the resistance circuit layer.

The present invention also provides a package carrier plate fabricated by the above method, comprising a capacitor unit, a first insulating layer and a second insulating layer formed on opposite sides of the capacitor unit, and a resistive circuit layer formed on the first insulating layer, forming The first conductive circuit layer on the surface of the resistive circuit layer and the second conductive circuit layer formed under the second insulating layer, the first conductive circuit layer and the second conductive circuit layer are electrically connected to the capacitor unit by the conductive pillars.

Compared with the prior art, the present invention utilizes an upper and a lower copper foil layer of an etched capacitor material to form a capacitor unit having a capacitor circuit layer. The capacitor unit is press-bonded to the insulating layer, the resistor substrate and the copper foil layer as a substrate, and is developed and etched to form a resistive wiring layer and an outer layer circuit layer. A blind via is formed by laser drilling and a conductive pillar is formed by plating a metal to the via hole to electrically conduct the capacitor circuit layer and the outer circuit layer, thereby obtaining a package carrier having an embedded capacitor and a resistor. By using the conductive pillars to respectively conduct the single-sided capacitor circuit layer and the outer layer circuit, the heat dissipation of the package carrier component can be improved, and the wiring density can be reduced and the component size can be reduced without increasing the thickness of the package carrier and increasing the number of package carrier layers. . In addition, it is also possible to avoid the abnormality of the plugging quality caused by the high aspect ratio of the through hole plating filling hole.

10‧‧‧Package carrier

100‧‧‧Capacitive substrate

100a‧‧‧Capacitor unit

110‧‧‧ dielectric layer

120‧‧‧First copper foil layer

122‧‧‧Second copper foil layer

1202‧‧‧First capacitor circuit layer

1222‧‧‧Second capacitor circuit layer

130‧‧‧First dry film

132‧‧‧Second dry film

140‧‧‧First insulation

142‧‧‧Second insulation

150‧‧‧Resistive substrate

152‧‧‧resistive circuit layer

160‧‧‧ third copper foil layer

162‧‧‧fourth copper foil layer

170‧‧‧ Third dry film

172‧‧‧fourth dry film

174‧‧‧ seventh dry film

176‧‧‧ eighth dry film

180‧‧‧First conductive pattern

181‧‧‧First conductive circuit layer

182‧‧‧Second conductive circuit layer

183‧‧‧ Third conductive circuit layer

190‧‧‧ fifth dry film

192‧‧‧ sixth dry film

194‧‧‧ ninth dry film

196‧‧‧ Tenth dry film

200‧‧‧Substrate

201‧‧‧First blind hole

202‧‧‧Second blind hole

203‧‧‧ third blind hole

204‧‧‧4th blind hole

201a‧‧‧First Conductive Column

202a‧‧‧second conductive column

203a‧‧‧The third conductive column

204a‧‧‧fourth conductive column

210‧‧‧First solder mask

212‧‧‧Second solder mask

220‧‧‧First surface treatment layer

222‧‧‧Second surface treatment layer

1 is a schematic cross-sectional view of a capacitor substrate according to a first embodiment of the present invention.

2 is a schematic cross-sectional view showing the formation of a first dry film and a second dry film on the capacitor substrate of FIG. 1.

3 is a schematic cross-sectional view showing the capacitor substrate formed by etching the capacitor substrate of FIG. 1.

4 is a schematic cross-sectional view showing the formation of a substrate on the basis of the capacitor unit of FIG. 3.

Figure 5 is a schematic cross-sectional view showing the formation of a blind via on the substrate of Figure 4.

Figure 6 is a schematic cross-sectional view showing the plating of the blind holes in Figure 5 and forming the third dry film and the fourth dry film.

FIG. 7 is a schematic cross-sectional view showing the formation of the first conductive line pattern, the second conductive wiring layer, and the resistive wiring layer in FIG.

Figure 8 is a schematic cross-sectional view showing the formation of a fifth dry film and a sixth dry film in Figure 7.

Figure 9 is a schematic cross-sectional view showing the formation of the first conductive wiring layer and the third conductive wiring layer in Figure 8.

10 is a schematic cross-sectional view showing the formation of a first solder resist layer, a second solder resist layer, a first surface treatment layer, and a second surface treatment layer in FIG.

Figure 11 is a cross-sectional view showing the seventh dry film and the eighth dry film formed by plating a blind hole in Figure 5.

12 is a schematic cross-sectional view showing the formation of the first conductive wiring layer, the second conductive wiring layer, and the third conductive wiring layer in FIG.

Figure 13 is a schematic cross-sectional view showing the formation of the ninth dry film and the tenth dry film in Figure 12 .

FIG. 14 is a schematic cross-sectional view showing the formation of a resistive wiring layer on the etched resistor substrate of FIG.

A first embodiment of the present invention provides a method of fabricating a package carrier 10, which includes the following steps:

For the first process, referring to FIG. 1 , a capacitor substrate 100 is provided. The capacitor substrate 100 includes a dielectric layer 110 and first copper foil layers 120 and second copper respectively formed on opposite sides of the dielectric layer 110 . Foil layer 122.

In the second process, referring to FIG. 2 and FIG. 3, the capacitor substrate 100 is etched to form a capacitor unit 100a.

As shown in FIG. 2, the capacitor unit 100a is specifically formed by first covering the first dry film 130 and the second dry film 132 on the first copper foil layer 120 and the second copper foil layer 122, respectively, by exposure, The first dry film 130 and the second dry film 132 are patterned by development. Next, as shown in FIG. 3, the first copper foil layer 120 and the second copper foil layer 122 are respectively etched to form a first capacitor line layer 1202 and a second capacitor line layer 1222. Finally, the first dry film 130 and the second dry film 132 are removed to obtain a capacitor unit 100a.

In the third process, referring to FIG. 4, the first insulating layer 140 and the second insulating layer 142 are respectively formed on the upper and lower sides of the capacitor unit 100a, and the resistive substrate 150 is formed on the surface of the first insulating layer 140. Thereafter, a third copper foil layer 160 and a fourth copper foil layer 162 are formed on the surface of the resistor substrate 150 and the surface of the second insulating layer 142, respectively, thereby obtaining the substrate 200 in which the capacitor unit 100a is embedded.

In the fourth process, referring to FIG. 5, a plurality of blind holes are formed on the substrate 200 to expose the first capacitor circuit layer 1202 and the second capacitor circuit layer 1222.

Specifically, a pair of first blind holes 201 and second blind holes 202 are formed from the third copper foil layer 160 and the fourth copper foil layer 162 toward the first capacitor circuit layer 1202 by laser drilling, respectively. A pair of third blind holes 203 and fourth blind holes 204 are formed from the third copper foil layer 160 and the fourth copper foil layer 162 toward the second capacitor line layer 1222. The first blind via 201 and the second blind via 202 are used to expose the first capacitive circuit layer 1202, and the third blind via 203 and the fourth blind via 204 are used to expose the second capacitive wiring layer 1222. Specifically, the first blind via 201 sequentially penetrates the third copper foil layer 160 , the resistive substrate 150 , and the first insulating layer 140 from above the substrate 200 to expose a portion of the first capacitor line layer 1202 . The second blind hole 202 is disposed opposite to the first blind hole 201, and sequentially penetrates the fourth copper foil layer 162, the second insulating layer 142, the second capacitor circuit layer 1222, and the dielectric layer 110 from below the substrate 200 to expose a portion. The first capacitive circuit layer 1202. Similarly, the third blind via 203 sequentially penetrates the third copper foil layer 160 and the resistive substrate 150 from above the substrate 200. The first insulating layer 140, the first capacitor line layer 1202, and the dielectric layer 110 expose a portion of the second capacitor line layer 1222. The fourth blind via 204 corresponds to the third blind via 203, and sequentially penetrates the fourth copper foil layer 162 and the second insulating layer 142 from below the substrate 200 to expose a portion of the second capacitive wiring layer 1222.

In this embodiment, as shown in FIG. 5, the depth of the first blind hole 201 is smaller than the depth of the second blind hole 202, and the depth of the third blind hole 203 is greater than the depth of the fourth blind hole 204.

In the fifth process, referring to FIG. 6 and FIG. 7, the first blind via 201, the second blind via 202, the third blind via 203, and the fourth blind via 204 are filled with copper, thereby forming a first conductive pillar 201a, a second conductive pillar 202a, a third conductive pillar 203a, and a fourth conductive pillar 204a; and etching the third copper foil layer 160 and the fourth copper foil layer 162, thereby forming the first conductive pattern 180 and the second conductive wiring layer 182, The resistor substrate 150 is etched to form a resistive wiring layer 152.

Specifically, first, referring to FIG. 6, the first blind via 201, the second blind via 202, the third blind via 203, and the fourth blind via 204 are filled with copper to form a first layer by electroplating. The conductive pillar 201a, the second conductive pillar 202a, the third conductive pillar 203a, and the fourth conductive pillar 204a enable the first conductive pillar 201a to conduct the first capacitor circuit layer 1202 and the third copper foil layer 160, and the second conductive pillar 202a is turned on. The first capacitor circuit layer 1202 and the fourth copper foil layer 162 enable the third conductive pillar 203a to conduct the second capacitor circuit layer 1222 and the third copper foil layer 160, so that the fourth conductive pillar 204a turns on the second capacitor circuit layer 1222 and the first Four copper foil layers 162. Next, a third dry film 170 and a fourth dry film 172 are formed on the surfaces of the third copper foil layer 160 and the fourth copper foil layer 162, respectively, and the third dry film 170 and the fourth dry film 172 are exposed by exposure and development. Patterned. Thereafter, as shown in FIG. 7, the third copper foil layer 160 and the fourth copper foil layer 162 are etched to obtain a first conductive pattern 180 and a second conductive wiring layer 182. At the same time, the resistor substrate 150 is etched to obtain the resistance wiring layer 152, and finally the third dry film 170 and the fourth dry film 172 are removed.

In the sixth process, referring to FIGS. 8-9, the first conductive pattern 180 is etched to form a first conductive wiring layer 181 and at least a third conductive wiring layer 183.

The method for forming the first conductive circuit layer 181 and the third conductive circuit layer 183 specifically includes the following steps: First, forming a fifth dry film 190 and a sixth dry film on the surfaces of the first conductive pattern 180 and the second conductive circuit layer 182, respectively. 192. The fifth dry film 190 and the sixth dry film 192 are subjected to exposure and development. Patterned. Thereafter, as shown in FIG. 9, the first conductive pattern 180 is etched to form a first conductive wiring layer 181 and a third conductive wiring layer 183. Finally, the fifth dry film 190 and the sixth dry film 192 are removed.

At this time, the first capacitor circuit layer 1202 is electrically connected to the first conductive circuit layer 181 and the second conductive circuit layer 182 by the first conductive pillar 201a and the second conductive pillar 202a, respectively, and the second capacitor circuit layer 1222 is electrically conductive by the third conductive layer. The pillar 203a and the fourth conductive pillar 204a are electrically connected to the first conductive wiring layer 181 and the second conductive wiring layer 182, respectively.

In the seventh process, referring to FIG. 10, a first solder resist layer 210 is formed on the first conductive wiring layer 181 and the third conductive wiring layer 183, and a second solder resist layer 212 is formed on the surface of the second conductive wiring layer 182. At least one pair of solder resist openings are formed on each of the solder resist layer 210 and the second solder resist layer 212. A portion of the first conductive wiring layer 181 and the third conductive wiring layer 183 are exposed from the solder resist opening of the first solder resist layer 210; a portion of the second conductive wiring layer 182 is formed from the solder resist opening of the second solder resist layer 212. Exposed. Thereafter, a first surface treatment layer 220 is formed on the exposed portions of the first conductive wiring layer 181 and the third conductive wiring layer 183, and a second surface treatment layer 222 is formed on the second conductive wiring layer 182. The first surface treatment layer is formed. 220 and second surface treatment layer 222 are used to solder external wafers (not shown). The first surface treatment layer 220 and the second surface treatment layer 222 may be an organic welder or a metal protective layer.

Through the above steps, the package carrier 10 of the present invention is formed.

The method of fabricating the package carrier 10 of the second embodiment of the present invention is substantially the same as the method of fabricating the package carrier 10 of the first embodiment, and is different from the following steps.

Referring to FIG. 11 and FIG. 12, the first blind via 201, the second blind via 202, the third blind via 203, and the fourth blind via 204 are filled with copper to form a first conductive pillar 201a. The second conductive pillar 202a, the third conductive pillar 203a, and the fourth conductive pillar 204a etch the substrate third copper foil layer 160 and the fourth copper foil layer 162, thereby forming the first conductive wiring layer 181, the second conductive wiring layer 182, and The third conductive circuit layer 183.

Referring to FIG. 11, first, the first blind via 201, the second blind via 202, the third blind via 203, and the fourth blind via 204 are filled with copper to form a first conductive pillar 201a and a second by electroplating. The conductive pillar 202a, the third conductive pillar 203a, and the fourth conductive pillar 204a turn on the first conductive pillar 201a. a capacitor circuit layer 1202 and a third copper foil layer 160, so that the second conductive pillar 202a turns on the first capacitor circuit layer 1202 and the fourth copper foil layer 162, so that the third conductive pillar 203a turns on the second capacitor circuit layer 1222 and the third The copper foil layer 160 causes the fourth conductive pillar 204a to conduct the second capacitor wiring layer 1222 and the fourth copper foil layer 162. Next, the seventh dry film 174 and the eighth dry film 176 are respectively covered on the surfaces of the third copper foil layer 160 and the fourth copper foil layer 162, and the seventh dry film 174 and the eighth dry film 176 are patterned by exposure and development. Chemical. Thereafter, referring to FIG. 12, the third copper foil layer 160 and the fourth copper foil layer 162 are etched to obtain a first conductive wiring layer 181, a second conductive wiring layer 182, and a third conductive wiring layer 183. Finally, the seventh dry film 174 and the eighth dry film 176 are removed. The first capacitor circuit layer 1202 is electrically connected to the first conductive circuit layer 181 and the second conductive circuit layer 182 by the first conductive pillar 201a and the second conductive pillar 202a, respectively, and the second capacitor circuit layer 1222 is connected by the third conductive pillar. 203a and fourth conductive pillars 204a are electrically connected to the first conductive wiring layer 181 and the second conductive wiring layer 182, respectively.

In the sixth process, referring to FIGS. 13 and 14, the resistor substrate 150 is etched to form the resistive wiring layer 152.

Referring to FIG. 13, the ninth dry film 194 is covered on the surface of the resistor substrate 150, the first conductive circuit layer 181, and the third conductive circuit layer 183, and the tenth dry film 196 is covered on the surface of the second conductive circuit layer 182 by exposure. The ninth dry film 194 and the tenth dry film 196 are patterned by development. Thereafter, referring to FIG. 14, the resistor substrate 150 is etched to obtain the resistance wiring layer 152. Finally, the ninth dry film 194 and the tenth dry film 196 are removed.

Referring to FIG. 10, the present invention further provides a package carrier 10 comprising a dielectric layer 110 and a first capacitor circuit layer 1202 and a second capacitor circuit layer formed on the upper and lower sides of the dielectric layer 110. The capacitor unit 100a composed of 1222, the first insulating layer 140 and the second insulating layer 142 attached to the upper and lower sides of the capacitor unit 100a, and the resistive wiring layer 152 formed on the surface of the first insulating layer 140 are formed on the surface of the resistive circuit layer 152. a first conductive circuit layer 181, a second conductive circuit layer 182 formed on a surface of the second insulating layer 142, and first solder resist layers 210 and a first surface formed on the surfaces of the first conductive circuit layer 181 and the second conductive circuit layer 182, respectively The second solder resist layer 212 is respectively opened on the first solder resist layer 210 and the second anti-solder layer At least one pair of solder resist openings on the solder layer 212 and the first surface treatment layer 220 and the second surface treatment layer 222 formed on the solder resist opening.

The package carrier 10 provided by the present invention further includes a first conductive pillar 201a, a second conductive pillar 202a, a third conductive pillar 203a, and a fourth conductive pillar 204a. The first capacitor circuit layer 1202 is electrically connected to the first conductive circuit layer 181 and the second conductive circuit layer 182 by the first conductive pillar 201a and the second conductive pillar 202a, respectively. The second capacitor circuit layer 1222 is supported by the third conductive pillar 203a. The fourth conductive pillars 204a are electrically connected to the first conductive wiring layer 181 and the second conductive wiring layer 182, respectively.

Specifically, the first conductive pillar 201a is located above the capacitor unit 100a, which is sequentially connected to the first conductive circuit layer 181, penetrates the resistance circuit layer 152 and the first insulating layer 140, and is connected to the first capacitor circuit layer 1202. The second conductive pillars 202a are located under the capacitor unit 100a, which are sequentially connected to the second conductive circuit layer 182, penetrate the second insulating layer 142, the second capacitor circuit layer 1222, and the dielectric layer 110, and are connected to the first capacitor circuit layer 1202. . The third conductive pillar 203a is located above the capacitor unit 100a, and sequentially connects the first conductive circuit layer 181, penetrates the resistance circuit layer 152 and the first insulating layer 140, the first capacitor circuit layer 1202, and the dielectric layer 110, and is connected to the second Capacitor circuit layer 1222. The fourth conductive pillar 204a is located below the capacitor unit 100a, which in turn connects the second conductive wiring layer 182, penetrates the second insulating layer 142, and is connected to the second capacitor circuit layer 1222.

The package carrier 10 of the present invention further includes at least one third conductive circuit layer 183 for connection to other electronic components. In the embodiment, the third conductive circuit layer 183 is in communication with the first conductive circuit layer 181 via the resistance circuit layer 152.

Compared with the prior art, the present invention utilizes an upper and a lower copper foil layer of an etched capacitor material to form a capacitor unit having a capacitor circuit layer. The capacitor unit is press-bonded to the insulating layer, the resistor substrate and the copper foil layer as a substrate, and is developed and etched to form a resistive wiring layer and an outer layer circuit layer. A blind via is formed by laser drilling and a conductive pillar is formed by plating a metal to the via hole to electrically conduct the capacitor circuit layer and the outer circuit layer, thereby obtaining a package carrier having an embedded capacitor and a resistor. By using the conductive pillars to respectively conduct the single-sided capacitor circuit layer and the outer layer circuit, the heat dissipation of the package carrier component can be improved, and the number of the package carrier layers is not increased without thickening the package carrier board. In this case, the wiring density is reduced and the component size is reduced. In addition, it is also possible to avoid the abnormality of the plugging quality caused by the high aspect ratio of the through hole plating filling hole.

10‧‧‧Package carrier

100a‧‧‧Capacitor unit

1202‧‧‧First capacitor circuit layer

1222‧‧‧Second capacitor circuit layer

140‧‧‧First insulation

142‧‧‧Second insulation

152‧‧‧resistive circuit layer

181‧‧‧First conductive circuit layer

182‧‧‧Second conductive circuit layer

183‧‧‧ Third conductive circuit layer

201a‧‧‧First Conductive Column

202a‧‧‧second conductive column

203a‧‧‧The third conductive column

204a‧‧‧fourth conductive column

210‧‧‧First solder mask

212‧‧‧Second solder mask

220‧‧‧First surface treatment layer

222‧‧‧Second surface treatment layer

Claims (10)

A method for fabricating a package carrier, comprising the steps of: providing a capacitor substrate, the capacitor substrate comprising a dielectric layer and a first copper foil layer and a second copper foil layer on opposite sides of the dielectric layer; Etching the first copper foil layer and the second copper foil layer to form a first capacitor circuit layer and a second capacitor circuit layer to obtain a capacitor unit; forming a first insulating layer and a resistor sequentially above the first capacitor circuit layer a substrate and a third copper foil layer, a second insulating layer and a fourth copper foil layer are formed under the second capacitor circuit layer to obtain a substrate in which the capacitor unit is embedded; a blind hole is formed on the substrate, and Electroplating the blind via hole to form a conductive pillar, wherein the third copper foil layer and the fourth copper foil layer are respectively electrically connected to the first capacitor circuit layer and the second capacitor circuit layer by the conductive pillar; The third copper foil layer, the fourth copper foil layer and the resistor substrate are etched to form a first conductive wiring layer and a second wiring circuit layer and a resistance wiring layer. The method for manufacturing a package carrier according to claim 1, wherein the blind hole comprises a first blind hole, a second blind hole, a third blind hole, and a fourth blind hole, wherein the first blind hole is Above the substrate, the third copper foil layer, the resistor substrate and the first insulating layer are sequentially penetrated to expose the first capacitor circuit layer; the second blind holes are sequentially penetrated from the bottom of the substrate a fourth copper foil layer, the second insulating layer, the second capacitor circuit layer and the dielectric layer to expose the first capacitor circuit layer; the third blind vias are sequentially from above the substrate Through the third copper foil layer, the resistor substrate and the first insulating layer, the first capacitor circuit layer and the dielectric layer to expose the second capacitor circuit layer; the fourth blind The holes penetrate the fourth copper foil layer and the second insulating layer in sequence from below the substrate to expose the second capacitor circuit layer. The method for fabricating a package carrier according to the second aspect of the invention, wherein the first blind hole, the second blind hole, the third blind hole, and the fourth blind hole are electroplated Filling copper to form a first conductive pillar, a second conductive pillar, a third conductive pillar, and a fourth conductive pillar, respectively, to make the first The conductive pillars conduct the first capacitor circuit layer and the third copper foil layer, so that the second conductive pillar conducts the first capacitor circuit layer and the fourth copper foil layer, so that the third conductive pillar The second capacitor circuit layer and the third copper foil layer are turned on, such that the fourth conductive pillar conducts the second capacitor circuit layer and the fourth copper foil layer are electrically connected. The method for fabricating a package carrier according to claim 1, wherein the etching the third copper foil layer further comprises forming at least one third conductive circuit layer, wherein the third conductive circuit layer is formed by the resistance circuit The layer is in communication with the first conductive circuit layer. The method of fabricating a package carrier according to claim 4, wherein the third copper foil layer and the resistor substrate are etched to form a first conductive trace pattern and the resistive wiring layer, and the first A conductive line pattern forms the first conductive wiring layer and the third conductive wiring layer. The method for fabricating a package carrier according to claim 4, wherein the third copper foil layer is first etched to form the first conductive wiring layer and the third conductive wiring layer, and the resistor substrate is etched second. Forming the resistive wiring layer. The method for fabricating a package carrier according to claim 1, further comprising forming a first solder resist layer on the first conductive circuit layer and forming a second solder resist on the second conductive circuit layer. And forming at least one pair of solder resist openings in the first solder resist layer and the second solder resist layer to expose the first conductive trace layer and the second conductive trace layer to the solder resist layer Opening. A package carrier comprising a capacitor unit composed of a dielectric layer and a first capacitor circuit layer and a second capacitor circuit layer formed on upper and lower surfaces of the dielectric layer, and formed on the opposite surfaces of the capacitor unit An insulating layer and a second insulating layer, a resistive circuit layer formed over the first insulating layer, a first conductive circuit layer formed on a surface of the resistive wiring layer, and a second formed under the second insulating layer a conductive circuit layer, wherein the first conductive circuit layer and the second conductive circuit layer are electrically connected to the capacitor unit by a conductive pillar, the conductive pillar includes a first conductive pillar, a second conductive pillar, and a third conductive a pillar and a fourth conductive pillar; the first conductive pillar is located above the capacitor unit, penetrates the resistor circuit layer and the first insulating layer, and is connected to the first capacitor circuit layer and the first conductive circuit layer; The second conductive pillar is located below the capacitor unit, and is connected to the second conductive circuit layer, through the first a second insulating layer, the second capacitor circuit layer and a dielectric layer are connected to the first capacitor circuit layer; the first capacitor circuit layer is respectively connected to the first conductive pillar and the second conductive pillar The first conductive line and the second conductive line are turned on; the third conductive pillar is located above the capacitor unit, and sequentially connects the first conductive circuit layer, penetrates the resistance circuit layer, and the first insulation The layer, the first capacitor circuit layer and the dielectric layer are connected to the second capacitor circuit layer; the fourth conductive pillar is located below the capacitor unit, and sequentially connected to the second conductive circuit layer, The second insulating layer is connected to the second capacitor circuit layer, and the second capacitor circuit layer is respectively connected to the first conductive line and the third conductive pillar and the fourth conductive pillar The second conductive line is turned on. The package carrier of claim 8, wherein the package carrier further comprises at least one third conductive circuit layer, the third conductive circuit layer by the resistance circuit layer and the first The conductive circuit layers are in communication. The package carrier of claim 9, wherein the package carrier further includes a first solder resist layer, a second solder resist layer, a first surface treatment layer, and a second surface treatment layer, a solder resist layer is formed on the surface of the first conductive circuit layer and the third conductive circuit layer, and the second solder resist layer is formed on a surface of the second conductive circuit layer, the first solder resist layer and the The second solder resist layer respectively includes at least one first solder mask opening and at least one second solder mask opening, and the first conductive trace layer and the third conductive trace layer are exposed to the first solder resist layer Opening; the second conductive circuit layer is exposed to the second solder resist layer opening, the first surface treatment layer is formed on the first conductive circuit layer and the first exposed by the first solder resist opening On the three conductive circuit layers, the second surface treatment layer is formed on the second conductive circuit layer exposed by the opening of the second solder resist layer.