CN114286540B - Method for manufacturing circuit board and circuit board - Google Patents
Method for manufacturing circuit board and circuit board Download PDFInfo
- Publication number
- CN114286540B CN114286540B CN202011041557.1A CN202011041557A CN114286540B CN 114286540 B CN114286540 B CN 114286540B CN 202011041557 A CN202011041557 A CN 202011041557A CN 114286540 B CN114286540 B CN 114286540B
- Authority
- CN
- China
- Prior art keywords
- layer
- circuit
- substrate
- slot
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 379
- 239000000758 substrate Substances 0.000 claims abstract description 81
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 53
- 239000011889 copper foil Substances 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 40
- 239000012790 adhesive layer Substances 0.000 claims abstract description 37
- 239000003292 glue Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims description 28
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 20
- 239000004642 Polyimide Substances 0.000 claims description 15
- 229920001721 polyimide Polymers 0.000 claims description 15
- 239000003822 epoxy resin Substances 0.000 claims description 10
- 229920000647 polyepoxide Polymers 0.000 claims description 10
- 239000004593 Epoxy Substances 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- 238000009713 electroplating Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical compound C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- CBCKQZAAMUWICA-UHFFFAOYSA-N 1,4-phenylenediamine Chemical compound NC1=CC=C(N)C=C1 CBCKQZAAMUWICA-UHFFFAOYSA-N 0.000 description 1
- GTDPSWPPOUPBNX-UHFFFAOYSA-N ac1mqpva Chemical compound CC12C(=O)OC(=O)C1(C)C1(C)C2(C)C(=O)OC1=O GTDPSWPPOUPBNX-UHFFFAOYSA-N 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 235000010290 biphenyl Nutrition 0.000 description 1
- 239000004305 biphenyl Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A manufacturing approach of circuit board and circuit board, this method includes providing a circuit board, the circuit board includes the base material layer, two inner circuit layers, two glue layers and two outer copper foil layers; forming a slot on the circuit substrate by using laser, wherein the slot at least does not penetrate through an outer copper foil layer, and the slot comprises a first opening formed in the adhesive layer; forming an electroplated layer on the inner wall of the slot, wherein the electroplated layer enables the inner circuit layer to be electrically connected with the outer copper foil layer; etching the outer copper foil layer to form an outer circuit layer, wherein the electroplated layer is communicated with the inner circuit layer and the outer circuit layer to form a wire, the maximum width of the wire is equal to the width of the first opening, and the total thickness of the wire is at least equal to the distance between the two outer circuit layers; and fixing the electronic element on the surface of the outer circuit layer which is not penetrated by the slot and is away from the slot, so as to obtain the circuit board.
Description
Technical Field
The application relates to a manufacturing method of a circuit board and the circuit board.
Background
In the printed circuit board, based on the requirements of carrying current, heat dissipation, impedance matching and the like, the circuit layer in the circuit board is required to have larger thickness and width, so that the internal resistance of the circuit layer is reduced. However, because of the light and thin electronic products and the high density, there is no more space for increasing the width of the circuit layer, so the thickness of the circuit layer is often increased in the prior art.
In the conventional process, electroplating is usually adopted on the copper foil layer, and then the electroplating layer and the copper foil layer are etched in an exposure and development mode to obtain a circuit layer, wherein the arrangement of the electroplating layer can increase the total thickness of the circuit layer. However, due to the limitation of the exposure and development process, the thickness of the electroplated layer is limited, and the width of the electroplated layer in the obtained circuit layer may be smaller than the width of the copper foil layer, so that the internal resistance of the circuit layer can be reduced to a limited extent; the thickened circuit layer may have partial bubbles or insufficient filling due to the line distance and the thickness of the electroplated layer in the subsequent filling process, so that the reliability of the product is affected, and the like.
Disclosure of Invention
In view of the above, it is necessary to provide a method for manufacturing a circuit board in which an embedded plating layer is formed in an internal space of the circuit board to reduce the resistance of a wire.
In addition, the application also provides a circuit board manufactured by adopting the manufacturing method of the circuit board.
The application provides a manufacturing method of a circuit board, which comprises the following steps:
the circuit substrate comprises a base material layer, wherein the base material layer comprises two opposite surfaces, and an inner circuit layer, an adhesive layer and an outer copper foil layer are sequentially laminated on each surface.
And forming at least one slot in the circuit substrate by using laser, wherein the slot at least penetrates through the outer copper foil layer, the adhesive layer and the inner circuit layer which are positioned at one side of the substrate layer, the slot at least does not penetrate through the other outer copper foil layer, the slot comprises a first opening formed in the adhesive layer, a second opening formed in the substrate layer and a third opening formed in the inner circuit layer and the outer copper foil layer, and the size of the first opening is larger than that of the second opening and the size of the first opening is larger than that of the third opening along the extending direction of the circuit substrate.
And forming an electroplated layer on the inner wall of the slot, wherein the electroplated layer enables the inner circuit layer to be electrically connected with the outer copper foil layer.
Etching the outer copper foil layer to form an outer circuit layer, wherein the electroplated layer is communicated with the inner circuit layer and the outer circuit layer to jointly form a wire, the maximum width of the wire is equal to the width of the first opening along the extending direction of the circuit substrate, and the total thickness of the wire is not less than the distance between the surfaces of the two outer circuit layers far away from one side of the substrate layer.
And providing an electronic element, and mounting the electronic element on the outer circuit layer of the wire, so as to obtain the circuit board.
In an embodiment of the present application, the thermal decomposition temperature of the substrate layer is greater than the thermal decomposition temperature of the glue layer.
In the embodiment of the application, the adhesive layer is made of epoxy resin, and the substrate layer is made of polyimide.
In an embodiment of the present application, after the "forming the plating layer on the inner wall of the slot" further includes:
and forming a conductive column in the groove provided with the electroplated layer, wherein the wire also comprises the conductive column.
In the embodiment of the application, an insulating layer is further arranged between the adhesive layer and the outer layer circuit layer, and the grooves penetrate through the substrate layer, the two inner layer circuit layers, the two adhesive layers, the two insulating layers and the outer layer copper foil layer.
The application also provides a circuit board, which comprises a circuit substrate, and at least one slot and an electronic element which are arranged on the circuit substrate.
The circuit substrate comprises a substrate layer, the substrate layer comprises two opposite surfaces, an inner circuit layer, an adhesive layer and an outer circuit layer are sequentially arranged on each surface in a lamination mode, the inner circuit layer is electrically connected with the outer circuit layer, and the inner circuit layer is electrically connected with the outer circuit layer.
The grooving at least penetrates through the outer copper foil layer, the adhesive layer and the inner layer circuit layer which are arranged on one side of the substrate layer, the grooving at least does not penetrate through the other outer layer circuit layer, the grooving comprises a first opening formed in the adhesive layer, a second opening formed in the substrate layer and a third opening formed in the inner layer circuit layer and the outer layer circuit layer, the size of the first opening is larger than that of the second opening along the extending direction of the circuit substrate, the size of the first opening is also larger than that of the third opening, an electroplated layer is arranged on the grooved inner wall and is communicated with the inner layer circuit layer and the outer layer circuit layer to form a wire, the maximum width of the wire is equal to the width of the first opening along the extending direction of the circuit substrate, and the total thickness of the wire is not smaller than the distance between the surfaces of the two outer layer circuit layers far away from one side of the substrate layer.
The electronic component is mounted on the outer circuit layer of the wire.
In an embodiment of the present application, the thermal decomposition temperature of the substrate layer is greater than the thermal decomposition temperature of the glue layer.
In an embodiment of the present application, the material of the adhesive layer is epoxy resin, and the material of the base material layer is polyimide.
In the embodiment of the application, the slot provided with the electroplated layer is also provided with a conductive column, and the wire also comprises the conductive column.
In the embodiment of the application, an insulating layer is further arranged between the adhesive layer and the outer circuit layer.
In the embodiment of the application, an insulating layer is further arranged between the adhesive layer and the outer circuit layer.
The manufacturing method of the circuit board provided by the application has the following advantages: the inner layer circuit layer and the outer layer circuit layer form a through network structure through the grooves, then an electroplated layer is formed on the inner surface of each groove to conduct the inner layer circuit layer and the outer layer circuit layer, so that the embedded wire is obtained. The width of the inner layer or the outer layer circuit layer is not required to be increased independently, so that wiring space can be saved, and the technical development requirement of the high-density circuit board is met. The embedded design has no fault phenomenon, and the problems of partial bubbles or insufficient glue filling and the like in the subsequent process of filling the covering layer can be avoided due to factors such as line spacing, copper thickness and the like.
Drawings
Fig. 1 is a schematic view of a copper-clad plate according to an embodiment of the present application.
Fig. 2 is a schematic view of the copper clad laminate shown in fig. 1 after the first blind hole is formed.
Fig. 3 is a schematic view of a first blind hole in the copper-clad plate shown in fig. 2, provided with a first electrical connection portion
Fig. 4 is a schematic view of forming an inner circuit layer on the copper-clad plate shown in fig. 3.
Fig. 5 is a schematic diagram of a circuit substrate according to an embodiment of the application.
Fig. 6 is a schematic view of the circuit substrate shown in fig. 5 with a slot and a second blind hole.
Fig. 7 is a schematic view of a circuit substrate shown in fig. 6 with a plating layer formed in the grooves.
Fig. 8 is a schematic view of a circuit substrate shown in fig. 7 with conductive pillars formed in the slots.
Fig. 9 is a schematic view of forming an outer circuit layer on the circuit substrate shown in fig. 8.
Fig. 10 is a schematic view of a cover layer formed on the outer circuit layer shown in fig. 9.
Fig. 11 is a schematic diagram of a circuit board according to an embodiment of the application.
Description of the main reference signs
Circuit board 100
Circuit board 200
Copper-clad plate 10
Substrate layer 11
Inner copper foil layer 12
First blind hole 13
First electrical connection 14
Inner wiring layer 15
Adhesive layer 20
Insulating layer 30
Outer copper foil layer 40
Second blind hole 41
Second electrical connection portion 42
Outer layer of wiring layer 43
Slotting 50
First opening 51
Second opening 52
Third opening 53
Electroplated layer 60
Conductive post 70
Cover layer 80
Window 81
Electronic component 90
Wire 300
Width d1, d2, X
Total thickness Y
The application will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
The embodiment of the application provides a manufacturing method of a circuit board, which comprises the following steps:
in step S1, referring to fig. 1, a copper-clad plate 10 is provided, wherein the copper-clad plate 10 includes a substrate layer 11 and inner copper foil layers 12 disposed on two opposite surfaces of the substrate layer 11.
In the present embodiment, the material of the substrate layer 11 includes, but is not limited to, polyimide.
In step S2, referring to fig. 2 and 3, a first blind hole 13 is formed in the copper-clad plate 10, and a first electrical connection portion 14 is formed in the first blind hole 13, so that the two inner copper foil layers 12 are electrically connected through the first electrical connection portion 14.
In this embodiment, the first blind hole 13 may be formed on the copper-clad plate 10 by a laser drilling method.
In this embodiment, the first blind hole 13 does not penetrate through one inner copper foil layer 12, and the first electrical connection portion 14 is formed by copper plating in the first blind hole 13, so as to electrically connect the two inner copper foil layers 12. It can be appreciated that the first blind hole 13 may also penetrate through the whole copper-clad plate.
In step S3, referring to fig. 4, the inner copper foil layer 12 is etched to form an inner circuit layer 15, and the substrate layer 11 is exposed on the surface of the first inner circuit layer 15.
In this embodiment, the inner wiring layer 15 is manufactured by a subtractive process. Specifically, the inner circuit layer 15 can be obtained by a process such as film removal by exposure to a photoresist, development, etching, or the like.
In step S4, referring to fig. 5, a glue layer 20 is formed on the surface of each inner circuit layer 15, and the glue layer 20 encapsulates the inner circuit layers 15.
It is to be understood that the adhesive layer 20 may be formed on the surface of the substrate layer 11 exposed from the first inner circuit layer 15, that is, the adhesive layer 20 may be filled in the gaps of the inner circuit layer 15.
In this embodiment, the material of the adhesive layer 20 includes, but is not limited to, epoxy resin.
In step S5, referring to fig. 5, an outer copper foil layer 40 is formed on the surface of the adhesive layer 20 to form a circuit substrate 200.
In this embodiment, the outer copper foil layer 40 is formed on the surface of each adhesive layer 20. It will be appreciated that when the glue layer 20 is provided on only one side surface of the substrate layer 11, a single sided build-up may be selected.
In this embodiment, an insulating layer 30 is further disposed between the adhesive layer 20 and the outer copper foil layer 40, and the insulating layer 30 may be made of the same material as the base material layer 11, and may be polyimide.
In step S6, referring to fig. 6, at least one slot 50 is formed in the circuit substrate 200 by using a laser, and the slot 50 at least penetrates through the base material layer 11 and the inner circuit layer 15, the adhesive layer 20 and the outer copper foil layer 40 disposed on the same side of the base material layer 11.
The slot 50 includes a first opening 51 formed in the adhesive layer 20, a second opening 52 formed in the base material layer 11, and a third opening 53 formed in the inner circuit layer 15 and the outer copper foil layer 40, wherein a width of the first opening 51 is greater than a width of the second opening 52 along an extending direction of the circuit substrate 200, and a width of the first opening 51 is greater than a width of the third opening 53.
In this embodiment, the width of the second opening 52 is larger than the width of the third opening 53.
When the slot 50 is formed by the laser, a large amount of heat is generated during the slot forming process, and this heat is absorbed by the glue layer 20, the base material layer 11 and the insulating layer 30 surrounding the slot 50, so that the materials of the glue layer 20, the base material layer 11 and the insulating layer 30 are degraded, and after degradation, the glue layer 20, the base material layer 11 and the insulating layer 30 surrounding the slot 50 shrink inwards along the extending direction of the circuit substrate 200. The width of the slot 50 is increased throughout. Further, by selecting the materials of the adhesive layer 20, the base material layer 11 and the insulating layer 30, and controlling the energy of the laser beam, etc., the degradation degree of different layers can be different, so that the width of each portion of the slot 50 is different.
In this embodiment, the material of the adhesive layer 20 is epoxy resin, and the material of the base material layer 11 and the insulating layer 30 is Polyimide (PI).
After laser irradiation, the polymer material absorbs laser heat and then is vaporized or decomposed, and the vaporization or decomposition amount of the material is related to the property of the material. In the present embodiment, the shrinkage of the epoxy resin and polyimide is actually due to thermal decomposition of the material, and the degree of thermal decomposition is related to the thermal decomposition temperature of the material itself: the temperature at which the macromolecule begins to crack under heat is called the thermal decomposition temperature (Thermal decomposition). For wholly aromatic Polyimide (PI), the thermal decomposition temperature is 400-500 ℃ generally, the thermal decomposition temperature of polyimide synthesized by biphenyl dianhydride and p-phenylenediamine reaches 600 ℃, and the thermal decomposition temperature of epoxy resin is above 300 ℃. As can be seen from the thermal decomposition temperature specifications of the two materials, the epoxy resin shrink-in width d1 is greater than the polyimide shrink-in widths d2, d2: d1 =1:1.5, that is to say that the amount of shrinkage of the epoxy resin is 1.5 times greater than that of the polyimide when both materials receive the same laser heat.
The substrate layer 11 is used for carrying the inner circuit layer 15, the insulating layer 30 is used for carrying the outer copper foil layer 40, and if the shrinkage is too large, the circuit layer on the surface of the substrate layer is affected, so that the shrinkage of the substrate layer 11 is relatively small in the application. The width of the glue layer 20 is not limited by the circuit layer, so that when the material of the glue layer 20 is selected, the material with a lower thermal decomposition temperature can be selected, thereby increasing the shrinkage of the glue layer 20.
In this embodiment, the slot 50 penetrates through the substrate layer 11, the two inner circuit layers 15, the two adhesive layers 20 and the outer copper foil layer 40. At the bottom of the slot 50 is another outer copper foil layer 40.
In this embodiment, the slot 50 further penetrates through the two insulating layers 30, and a fourth opening 54 is formed in the slot 50 corresponding to the insulating layer 30, and the insulating layer 30 and the base material layer 11 are made of the same material, so that the dimensions of the fourth opening 54 formed in the slot 50 corresponding to the insulating layer 30 are identical to those of the second opening 52.
In this embodiment, the manufacturing method further includes forming a second blind hole 41 in the insulating layer 30 and the outer copper foil layer 40, where the second blind hole 41 corresponds to the first electrical connection portion 14.
In step S7, referring to fig. 7, a plating layer 60 is formed on the inner wall of the slot 50 to electrically connect the inner circuit layer 15 and the outer copper foil layer 40.
In this embodiment, the plating layer 60 is a copper plating layer. Specifically, the plating layer 60 is formed on the inner surfaces of the first, second, and third openings 51, 52, 53 and the surface of the outer copper foil layer 40 not penetrated by the slit 50 near the slit 50, thereby forming a stepped copper plating layer.
In this embodiment, the manufacturing method further includes forming a second electrical connection portion 42 in the second blind hole 41, so that the outer copper foil layer 40 and the inner circuit layer 15 are electrically connected through the second electrical connection portion 42.
In this embodiment, the plating layer 60 does not fill the slot 50, and it is understood that the plating layer 60 only coats the inner sidewall of the slot 50, and the surface of the plating layer 60 away from the inner sidewall of the slot 50 encloses a slot having a size slightly smaller than the original slot 50.
In another embodiment, the electroplated layer 60 fills the slots 50.
In step S8, referring to fig. 8, a conductive pillar 70 is formed in the trench 50 formed with the plating layer 60.
In the present embodiment, the conductive post 70 is formed by filling the groove 50 formed with the plating layer 60 with a conductive metal paste (e.g., copper paste or tin paste) and then curing the paste.
When the plating layer 60 is formed, the grooves 50 are not filled with the plating layer 60, but in the present embodiment, the grooves 50 are further filled with a conductive copper paste, and the grooves 50 formed with the plating layer 60 are filled with the copper paste, so that the filling effect is good, and defects such as voids and bubbles are not formed in the grooves 50.
In step S9, referring to fig. 9, the outer copper foil layer 40 is etched to form an outer circuit layer 43, the plating layer 60 connects the inner circuit layer 15 and the outer circuit layer 43 to form a conductive line 300 together, the outermost width X of the conductive line 300 is equal to the width of the first opening 51 along the extending direction of the circuit substrate 200, and the total thickness Y of the conductive line 300 is not less than the distance between the surfaces of the two outer circuit layers 43 away from the substrate layer 11.
The plating layer 60 forms a stepped structure built in the circuit substrate 200 by grooving the inside of the circuit substrate 200 and shrinking the glue layer 20, the base material layer 11 and the insulating layer 30, thereby effectively reducing the resistance of the conductive wire 300. By filling copper paste in the grooves 50 where the plating layer 60 is formed to form the conductive posts 70, the resistance of the wire 300 is further reduced.
The glue layer 20 is shrunk to form the first opening 51, and the width of the outermost side of the electroplated layer 60 formed in the slot 50 is equal to the width of the first opening 51, so that the width (maximum width) X of the outermost side of the wire 300 is equal to the width of the first opening 51, and the width of the first opening 51 can be controlled by selecting the material of the glue layer 20 and the energy of the laser, so that the maximum width X of the wire 300 can be controlled according to the actual requirement. Furthermore, the conductive posts 70 may be configured to integrate the structures within the slot 50, and may further reduce the resistance of the conductive line 300. The reduction of the resistance is beneficial to signal transmission and impedance matching, and in addition, the electronic element can be quickly cooled.
In the present embodiment, in order to increase the cross-sectional area of the conductive wire 300, the plating layer 60 may be formed on the surface of the outer layer wire layer 43 around the opening of the slot 50. Meanwhile, the surface of the conductive post 70 may be further increased by exceeding the opening of the slot 50, so that the total thickness Y of the conductive wire 300 may be further increased to the surface of the conductive post 70 away from the substrate layer 11, so that the total thickness Y of the conductive wire is equal to the distance between the surfaces of the outer circuit layer 43, which are not penetrated by the slot 50, away from the substrate layer 11, and the resistance of the conductive wire 300 is significantly reduced.
In this embodiment, along the extending direction of the circuit substrate 200, the minimum cross-sectional area of the conductive line 300=2×the cross-sectional area of the first opening 51+the cross-sectional area of the second opening 52+3×the cross-sectional area of the third opening 53+2×the cross-sectional area of the fourth opening 54+2×the cross-sectional area of the inner line layer 15 corresponding to the conductive line 300+2×the cross-sectional area of the outer line layer 43 corresponding to the conductive line 300, so that the inner line layer 15 and the outer line layer 43 form a penetrating network structure by opening the groove 50 and forming the plating layer 60 on the inner surface of the groove 50, and then the conductive post 70 is filled in the groove 50, thereby increasing the cross-sectional area of the conductive line 300 and effectively reducing the resistance of the conductive line 300.
In this embodiment, the outer circuit layer 43 is manufactured by a subtractive process. Specifically, the outer circuit layer 43 can be obtained by a process such as film removal by film-pressing exposure, development, etching, and the like.
In step S10, referring to fig. 10, a cover layer 80 is formed on the surface of the outer circuit layer 43, a window 81 is formed on the cover layer 80 on one side of the outer circuit layer 43 not penetrated by the slot 50, the window 81 is disposed corresponding to the slot 50, and the outer circuit layer 43 not penetrated by the slot 50 is exposed from the window 81 to form a bonding pad 431.
In step S11, referring to fig. 11, an electronic component 90 is provided, and the electronic component 90 is mounted on the bonding pad 431, thereby obtaining the circuit board 100.
In this embodiment, the electronic component 90 is soldered to the pad 431.
The plating layer 60 connects the outer circuit layer 43 and the inner circuit layer 15 corresponding to the slots 50, so as to jointly form the wires 300, in this embodiment, the slots 50 are two, the slots 50 are corresponding to two wires 300, the outer circuit layers 43 of the two wires 300 are connected to the electronic component 90, and the two wires 300 may be power lines or signal lines.
Referring to fig. 11, a circuit board 100 manufactured by the above-mentioned circuit board manufacturing method is provided in an embodiment of the application, where the circuit board 100 includes a circuit substrate 200, and a slot 50 and an electronic component 90 disposed on the circuit substrate 200.
The circuit substrate 200 includes a substrate layer 11, the substrate layer 11 includes two surfaces disposed opposite to each other, each surface is provided with an inner circuit layer 15, an adhesive layer 20, and an outer circuit layer 43, the two inner circuit layers 15 are electrically connected, and the inner circuit layers 15 and the outer circuit layers 43 on the same side are electrically connected.
Referring to fig. 9, the slot 50 does not penetrate through at least one of the outer circuit layers 43, the slot 50 includes a first opening 51 formed in the adhesive layer 20, a second opening 52 formed in the substrate layer 11, and a third opening 53 formed in the inner circuit layer 15 and the outer circuit layer 43, and the size of the first opening 51 is larger than the size of the second opening 52 along the extending direction of the circuit substrate 200, and the size of the first opening 51 is also larger than the size of the third opening 53. The inner wall of the slot 50 is provided with a plating layer 60, the plating layer 60 communicates the inner circuit layer 15 and the outer circuit layer 43 to form a conductive wire 300, the maximum width X of the conductive wire 300 is equal to the width of the first opening 51 along the extending direction of the circuit substrate 200, and the total thickness Y of the conductive wire 300 is at least equal to the distance between the surfaces of the two outer circuit layers 43 away from the substrate layer 11.
The electronic component 90 is fixed to and electrically connected to a surface of the outer circuit layer 43, which is not penetrated by the slot 50, at a side away from the slot 50.
In the present embodiment, the thermal decomposition temperature of the base material layer 11 and the insulating layer 30 is higher than the thermal decomposition temperature of the adhesive layer 20.
In this embodiment, the adhesive layer 20 is epoxy resin, and the base material layer 11 is polyimide.
In this embodiment, the conductive posts 70 are further disposed in the grooves 50 formed with the plating layer 60, and the conductive posts 70 can further increase the cross-sectional area of the conductive wire 300, thereby further reducing the resistance of the conductive wire 300. The conductive posts 70 are formed by curing a conductive metal paste, such as copper paste or tin paste.
In this embodiment, the circuit board 100 further includes a cover layer 80, the cover layer 80 is disposed on the surface of the outer circuit layer 43, the cover layer 80 is provided with a window 81 corresponding to the electronic component 90, the outer circuit layer 43 not penetrated by the slot 50 is exposed in the window 81, and the outer circuit layer 43 is exposed by the window 81 to form a bonding pad 431. The electronic component 90 is mounted on the bonding pad 431.
In this embodiment, an insulating layer 30 is further disposed between the adhesive layer 20 and the outer circuit layer 43. The fourth opening 54 is formed in the trench 50 corresponding to the insulating layer 30, and the insulating layer 30 and the base material layer 11 are made of the same material, so that the fourth opening 54 formed in the trench 50 corresponding to the insulating layer 30 is identical to the second opening 52 in size.
In this embodiment, the two slots 50 correspond to two wires 300, the outer circuit layers 43 of the two wires 300 are connected to the electronic component 90, and the two wires 300 may be power lines, signal lines, or the like.
According to the application, the grooves 50 are formed, and the electroplated layers 60 are formed in the grooves 50, so that the inner circuit layer 15 and the outer circuit layer 43 form a through network structure, and the embedded wire 300 is formed in the circuit board 100, and the adhesive layer 20 surrounding the grooves 50 is contracted inwards, so that the sectional area of the wire 300 is increased, and the resistance of the wire 300 is effectively reduced. Meanwhile, the wiring design of the inner circuit layer 15 and the outer circuit layer 43 is not affected, and the outer circuit layer 43 is not in fault, so that the thickened part is not in the process of filling the cover layer 80 in the follow-up process, and the problems of partial bubbles or insufficient filling glue and the like caused by factors such as line spacing, copper thickness and the like are avoided.
In addition, various other corresponding changes and modifications will be apparent to those skilled in the art from the technical idea of the present application, and all such changes and modifications are intended to be included in the scope of the present application.
Claims (10)
1. A method of manufacturing a circuit board, comprising the steps of:
providing a circuit substrate, wherein the circuit substrate comprises a base material layer, the base material layer comprises two opposite surfaces, and an inner circuit layer, an adhesive layer and an outer copper foil layer are sequentially laminated on each surface;
forming at least one slot in the circuit substrate by using laser, wherein the slot at least penetrates through the outer copper foil layer, the adhesive layer and the inner circuit layer which are positioned at one side of the substrate layer, the slot at least does not penetrate through the other outer copper foil layer, the slot comprises a first opening formed in the adhesive layer, a second opening formed in the substrate layer and a third opening formed in the inner circuit layer and the outer copper foil layer, and the size of the first opening is larger than that of the second opening along the extending direction of the circuit substrate, and the size of the first opening is also larger than that of the third opening;
forming an electroplated layer on the inner wall of the slot, wherein the electroplated layer enables the inner layer circuit layer to be electrically connected with the outer layer copper foil layer;
etching the outer copper foil layer to form an outer circuit layer, wherein the electroplated layer is communicated with the inner circuit layer and the outer circuit layer to form a wire together, the maximum width of the wire is equal to the width of the first opening along the extending direction of the circuit substrate, and the total thickness of the wire is not less than the distance between the surfaces of the two outer circuit layers away from one side of the substrate layer; and
providing an electronic element, and mounting the electronic element on the outer circuit layer of the wire, thereby obtaining the circuit board.
2. The method of manufacturing of claim 1, wherein the thermal decomposition temperature of the substrate layer is greater than the thermal decomposition temperature of the glue layer.
3. The method of claim 2, wherein the glue layer is epoxy and the substrate layer is polyimide.
4. The method of manufacturing according to claim 1, wherein after the forming of the plating layer on the inner wall of the groove, further comprising:
and forming a conductive column in the groove provided with the electroplated layer, wherein the wire also comprises the conductive column.
5. The method of claim 1, wherein an insulating layer is further disposed between the glue layer and the outer layer of circuitry, and the slot extends through the substrate layer, the two inner layer of circuitry, the two glue layers, the two insulating layers, and the outer layer of copper foil.
6. The circuit board is characterized by comprising a circuit substrate, and at least one slot and an electronic element which are arranged on the circuit substrate;
the circuit substrate comprises a substrate layer, wherein the substrate layer comprises two opposite surfaces, an inner circuit layer, an adhesive layer and an outer circuit layer are sequentially laminated on each surface, the two inner circuit layers are electrically connected, and the inner circuit layer is electrically connected with the outer circuit layer;
the slot at least penetrates through the outer layer circuit layer, the adhesive layer and the inner layer circuit layer which are positioned at one side of the substrate layer, the slot at least does not penetrate through the other outer layer circuit layer, the slot comprises a first opening formed in the adhesive layer, a second opening formed in the substrate layer and a third opening formed in the inner layer circuit layer and the outer layer circuit layer, the size of the first opening is larger than that of the second opening along the extending direction of the circuit substrate, the size of the first opening is also larger than that of the third opening, the inner wall of the slot is provided with an electroplated layer, the electroplated layer is communicated with the inner layer circuit layer and the outer layer circuit layer to form a wire, the maximum width of the wire is equal to the width of the first opening along the extending direction of the circuit substrate, and the total thickness of the wire is not smaller than the distance between the surfaces of the two outer layer circuit layers far away from one side of the substrate layer;
the electronic component is mounted on the outer circuit layer of the wire.
7. The circuit board of claim 6, wherein the thermal decomposition temperatures of the substrate layers are each greater than the thermal decomposition temperature of the glue layer.
8. The circuit board of claim 7, wherein the glue layer is made of epoxy resin and the substrate layer is made of polyimide.
9. The circuit board of claim 6, wherein said slot provided with said plating layer further has a conductive post disposed therein, said wire further comprising said conductive post.
10. The circuit board of claim 7, wherein an insulating layer is further disposed between the glue layer and the outer circuit layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011041557.1A CN114286540B (en) | 2020-09-28 | 2020-09-28 | Method for manufacturing circuit board and circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011041557.1A CN114286540B (en) | 2020-09-28 | 2020-09-28 | Method for manufacturing circuit board and circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114286540A CN114286540A (en) | 2022-04-05 |
| CN114286540B true CN114286540B (en) | 2023-08-18 |
Family
ID=80868147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011041557.1A Active CN114286540B (en) | 2020-09-28 | 2020-09-28 | Method for manufacturing circuit board and circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114286540B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102740582A (en) * | 2011-04-06 | 2012-10-17 | 日本梅克特隆株式会社 | Multilayer printed wiring board and producing method thereof |
| CN106658964A (en) * | 2015-10-28 | 2017-05-10 | 碁鼎科技秦皇岛有限公司 | Circuit board and production method thereof |
| CN106658959A (en) * | 2015-10-28 | 2017-05-10 | 富葵精密组件(深圳)有限公司 | Flexible circuit board and manufacturing method thereof |
-
2020
- 2020-09-28 CN CN202011041557.1A patent/CN114286540B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102740582A (en) * | 2011-04-06 | 2012-10-17 | 日本梅克特隆株式会社 | Multilayer printed wiring board and producing method thereof |
| CN106658964A (en) * | 2015-10-28 | 2017-05-10 | 碁鼎科技秦皇岛有限公司 | Circuit board and production method thereof |
| CN106658959A (en) * | 2015-10-28 | 2017-05-10 | 富葵精密组件(深圳)有限公司 | Flexible circuit board and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114286540A (en) | 2022-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8354596B2 (en) | Multilayer wiring board and method for manufacturing the same | |
| KR100412155B1 (en) | Electronic Component Device and Method of Manufacturing the Same | |
| US11699671B2 (en) | Packaged circuit structure including circuit strcutre with antenna | |
| US5223676A (en) | Composite circuit board having means to suppress heat diffusion and manufacturing method of the same | |
| KR20100125805A (en) | Heat radiation board and its manufacturing method | |
| CN111148353A (en) | Preparation method of circuit board with copper-based heat sink | |
| JP2001352166A (en) | Method for manufacturing wiring board | |
| KR20090094983A (en) | A metal core package and a multilayer printed circuit board including the metal core package and a fabricating method of the same | |
| JP2017135357A (en) | Printed wiring board and manufacturing method thereof | |
| CN114286540B (en) | Method for manufacturing circuit board and circuit board | |
| US9924590B2 (en) | Printed board and electronic apparatus | |
| JP2011049255A (en) | Wiring board with capacitive element, and method of manufacturing the same | |
| JP2001274555A (en) | Printed wiring board, blank board for printed wiring, semiconductor device, manufacturing method for printed wiring board and manufacturing method for semiconductor device | |
| US20220232697A1 (en) | Circuit board with at least one embedded electronic component and method for manufacturing the same | |
| KR100725481B1 (en) | Electronic element embedded printed circuit board and its manufacturing method | |
| JPH10261854A (en) | Printed wiring board and manufacturing method thereof | |
| JP2006344887A (en) | Printed-wiring board and manufacturing method therefor | |
| US20240244762A1 (en) | Wiring substrate and method for manufacturing the same | |
| JP3610769B2 (en) | Multi-layer electronic component mounting board | |
| CN217691158U (en) | Package substrate, integrated module, and electronic device | |
| CN113365443B (en) | Circuit board with embedded heat dissipation part and manufacturing method thereof | |
| JP4019717B2 (en) | Component built-in multilayer wiring module substrate and manufacturing method thereof | |
| KR101077336B1 (en) | Fabricating Method of Printed Circuit Board | |
| CN117295227A (en) | Circuit board, preparation method thereof and circuit board connection structure | |
| JPH0964542A (en) | Multilayered printed wiring board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |