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TWI596721B - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
TWI596721B
TWI596721B TW102127512A TW102127512A TWI596721B TW I596721 B TWI596721 B TW I596721B TW 102127512 A TW102127512 A TW 102127512A TW 102127512 A TW102127512 A TW 102127512A TW I596721 B TWI596721 B TW I596721B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
wafer
semiconductor
bonding material
electrodes
Prior art date
Application number
TW102127512A
Other languages
English (en)
Other versions
TW201411792A (zh
Inventor
Jumpei Konno
Takafumi Nishita
Kenji Sakata
Nobuhiro Kinoshita
Michiaki Sugiyama
Tsuyoshi Kida
Yoshihiro Ono
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of TW201411792A publication Critical patent/TW201411792A/zh
Application granted granted Critical
Publication of TWI596721B publication Critical patent/TWI596721B/zh

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Description

半導體裝置之製造方法
本發明係關於一種半導體裝置及其製造技術，例如，關於一種適用於積層平面尺寸不同之複數個半導體晶片之半導體裝置之有效技術。
於日本專利特開2005-191053號公報(專利文獻1)中揭示有藉由倒裝晶片連接方式而於封裝基板上搭載半導體晶片之半導體裝置之製造方法。專利文獻1中揭示有於封裝基板上，經由NCP(Non-Conductive Paste，非導電膏)配置半導體晶片後，推壓晶片背面，將半導體晶片連接於封裝基板之情況。
又，於日本專利特開2010-251408號公報(專利文獻2)、或日本專利特開2011-187574號公報(專利文獻3)中揭示有一種於經積層之複數個半導體晶片之各者形成貫通電極，且經由該貫通電極將複數個半導體晶片電性連接之半導體裝置。
又，於日本專利特開2000-299431號公報(專利文獻4)、或日本專利特開2002-26236號公報(專利文獻5)中揭示有以下之內容。當將第1半導體晶片(第1半導體元件)，經由各向異性導電接著劑(底部填充材)搭載於電路基板(基板)時，使各向異性導電接著劑之一部分伸出至第1半導體晶片之外部。而且，於伸出之樹脂即支撐部及第1半導體晶片之上，經由接著劑(黏晶用接著劑)搭載第2半導體晶片(第2半導體元件)。
[先前技術文獻] [專利文獻]
[專利文獻1]日本專利特開2005-191053號公報
[專利文獻2]日本專利特開2010-251408號公報
[專利文獻3]日本專利特開2011-187574號公報
[專利文獻4]日本專利特開2000-299431號公報
[專利文獻5]日本專利特開2002-26236號公報
本案發明者研究了使配線基板上積層有平面尺寸(外形尺寸)不同之複數個半導體晶片之半導體裝置之性能提昇之技術。作為其中一環節，研究了為使半導體晶片間之傳送速度提昇，而於複數個半導體晶片中配置於下段側之半導體晶片形成貫通電極，且經由該貫通電極，將複數個半導體晶片相互且電性地連接之技術。其結果，本案發明者發現於下段側之半導體晶片之平面尺寸小於上段側之半導體晶片之平面尺寸之情形時，半導體裝置之可靠性之方面產生了問題。
其他之課題與新穎性特徵可根據本說明書之記述及隨附圖式而清晰瞭解。
一實施形態之半導體裝置之製造方法係包含於配線基板上配置第1接著材後，於上述配線基板上搭載第1半導體晶片之步驟。又，半導體裝置之製造方法係包含於上述半導體晶片之第1背面上及自上述第1半導體晶片露出之上述第1接著材之露出面上，配置第2接著材後，於上述第1半導體晶片之上述第1背面上搭載第2半導體晶片之步驟。又，半導體裝置之製造方法係包含以樹脂密封上述第1半導體晶片及上述第2半導體晶片之步驟。
此處，上述第1半導體晶片係包含第1正面、形成於上述第1正面之複數個第1正面電極、與上述第1正面為相反側之第1背面、形成於第1背面之複數個第1背面電極、及以自上述第1正面及上述第1背面中之一者朝向另一者貫通之方式分別形成之複數個貫通電極。又，上述第2半導體晶片之平面尺寸大於上述第1半導體晶片之平面尺寸。又，於上述第2半導體晶片與上述配線基板之間隙由上述第1及第2接著材填塞之狀態下，進行上述樹脂之密封。
根據上述一實施形態，可使半導體裝置之可靠性提昇。
1、50、51、52、53‧‧‧半導體裝置
2、20‧‧‧配線基板
2a‧‧‧上表面(面、主面、晶片搭載面)
2b‧‧‧下表面(面、主面、安裝面)
2c‧‧‧側面
2d、2d1、2d2‧‧‧配線
2e‧‧‧絕緣層(核心層)
2f‧‧‧接合引線
2g‧‧‧焊墊
2h、2k‧‧‧絕緣膜(阻焊膜)
2hw、2kw‧‧‧開口部
2p1、2p2‧‧‧晶片搭載區域
3‧‧‧半導體晶片
3a‧‧‧正面(主面、上表面)
3ap、3ap1、3ap2‧‧‧正面電極(電極、焊墊)
3b‧‧‧背面(主面、下表面)
3bp‧‧‧背面電極(電極、焊墊)
3c‧‧‧側面
3d‧‧‧配線層(晶片配線層)
3tsh‧‧‧孔(孔、開口部)
3tsv‧‧‧貫通電極
4‧‧‧密封體(樹脂體)
4a‧‧‧上表面(面、正面)
4b‧‧‧下表面(面、背面)
4c‧‧‧側面
4g‧‧‧澆口部樹脂
4p‧‧‧樹脂
4v‧‧‧排氣孔部樹脂
5‧‧‧焊球
6‧‧‧密封體
6a‧‧‧底部填充樹脂
7‧‧‧突起電極(導電性構件、凸塊電極)
8‧‧‧接合材
8a、8b‧‧‧焊料層
20‧‧‧配線基板
20a‧‧‧器件區域
20b‧‧‧框部(外框)
20c‧‧‧切晶線(切晶區域)
25‧‧‧掩膜
26‧‧‧支撐基材
27‧‧‧保護層
28‧‧‧研磨治具
30‧‧‧保持治具
30a‧‧‧保持面
31‧‧‧加熱治具
32‧‧‧樹脂膜
33、36‧‧‧噴嘴
34‧‧‧基材(組裝基材)
34a‧‧‧組裝面
35‧‧‧接著層
40‧‧‧成形模具
41‧‧‧上模具
41a‧‧‧下表面(模具面)
41g‧‧‧澆口部
41v‧‧‧排氣孔部
41z‧‧‧模腔(凹部、凹陷部)
42‧‧‧下模具
42a‧‧‧上表面(模具面)
45‧‧‧切晶刀片(旋轉刀)
46‧‧‧膠帶材(切晶膠帶)
FL‧‧‧填料粒子
G1、G2、G3‧‧‧間隔
LC‧‧‧邏輯晶片
MC1、MC2、MC3、MC4‧‧‧記憶體晶片
MCS‧‧‧積層體
MR‧‧‧記憶體區域(記憶電路元件排列區域)
MRc‧‧‧記憶體區域MR之周緣部
NCL、NCL1、NCL2、NCL3、NCL4、NCL5‧‧‧接著材(絕緣性接著材)
NCL1a‧‧‧接著材NCL1之上表面
NCL1b‧‧‧接著材NCL1之下表面
NCL1c‧‧‧接著材NCL1之周緣部
R1‧‧‧填料粒子FL之半徑
T1‧‧‧邏輯晶片LC之厚度
T2‧‧‧記憶體晶片MC之厚度
TA‧‧‧積層體MCS之厚度
VD‧‧‧氣泡
WH‧‧‧晶圓
WHb‧‧‧晶圓WH之背面(主面、下表面)
WHs‧‧‧晶圓WH之正面(主面、上表面)
圖1係作為一實施形態之半導體裝置之立體圖。
圖2係圖1所示之半導體裝置之仰視圖。
圖3係表示將圖1所示之密封體去除之狀態下配線基板上之半導體裝置之內部結構之透視平面圖。
圖4係沿圖1之A-A線之剖面圖。
圖5係圖4所示之A部之放大剖面圖。
圖6係表示圖4所示之記憶體晶片之正面側之平面圖。
圖7係表示圖6所示之記憶體晶片之背面側之一例之平面圖。
圖8係表示圖4所示之邏輯晶片之正面側之平面圖。
圖9係表示圖8所示邏輯晶片之背面側之一例之平面圖。
圖10係圖4之B部之放大剖面圖。
圖11係表示使用圖1~圖10所說明之半導體裝置之製造步驟之概要之說明圖。
圖12係表示圖11所示之基板準備步驟中進行準備之配線基板之整體結構之平面圖。
圖13係相當於圖12所示之1個器件區域之放大平面圖。
圖14係沿圖13之A-A線之放大剖面圖。
圖15係表示圖13之相反側之面之放大平面圖。
圖16係表示於圖13所示之晶片搭載區域配置有接著材之狀態之放大平面圖。
圖17係沿圖16之A-A線之放大剖面圖。
圖18係示意性表示圖7所示之具備貫通電極之半導體晶片之製造步驟之概要之說明圖。
圖19係示意性表示繼圖18之後之半導體晶片之製造步驟之概要之說明圖。
圖20係表示於圖16所示之配線基板之晶片搭載區域上搭載有邏輯晶片LC之狀態之放大平面圖。
圖21係沿圖20之A-A線之放大剖面圖。
圖22係表示圖11所示之第1晶片搭載步驟之詳細流程之說明圖，且係示意性表示於晶片搭載區域上載置有半導體晶片之狀態之說明圖。
圖23係表示圖11所示之第1晶片搭載步驟之詳細流程之說明圖，且係表示將圖22所示之搬送治具拆卸，且將加熱治具抵住半導體晶片之背面側之狀態之說明圖。
圖24係表示圖11所示之第1晶片搭載步驟之詳細流程之說明圖，且係表示將半導體晶片加熱而與配線基板電性連接之狀態之說明圖。
圖25係表示於圖20所示之半導體晶片之背面及其周圍配置有接著材之狀態之放大平面圖。
圖26係沿圖25之A-A線之放大剖面圖。
圖27係示意性表示圖4所示之記憶體晶片之積層體之組裝步驟之概要之說明圖。
圖28係示意性表示繼圖27之後之記憶體晶片之積層體之組裝步 驟之概要之說明圖。
圖29係表示於圖25所示之邏輯晶片之背面上搭載有記憶體晶片之積層體之狀態之放大平面圖。
圖30係沿圖29之A-A線之放大剖面圖。
圖31係表示圖11所示之第2晶片搭載步驟之詳細流程之說明圖，且係示意性表示於邏輯晶片上載置有記憶體晶片之積層體之狀態之說明圖。
圖32係表示圖11所示之第2晶片搭載步驟之詳細流程之說明圖，且係表示將圖31所示之搬送治具拆卸，且將加熱治具抵住積層體之背面側之狀態之說明圖。
圖33係表示圖11所示之第2晶片搭載步驟之詳細流程之說明圖，且係表示將圖31所示之保持治具去除時，積層體傾斜之狀態之說明圖。
圖34係表示圖11所示之第2晶片搭載步驟之詳細流程之說明圖，且係表示將積層體加熱而與邏輯晶片電性連接之狀態之說明圖。
圖35係表示於圖30所示之配線基板上形成密封體，將經積層之複數個半導體晶片密封之狀態之放大剖面圖。
圖36係表示圖35所示之密封體之整體結構之平面圖。
圖37係表示於將密封體成形之成形模具內配置有圖30所示之配線基板之狀態之主要部分剖面圖。
圖38係表示對圖37所示之成形模具內供給樹脂之狀態之主要部分剖面圖。
圖39係表示圖37所示之成形模具內由樹脂充滿之狀態之主要部分剖面圖。
圖40係表示將圖39所示之配線基板自成形模具中取出之狀態之主要部分剖面圖。
圖41係表示於圖35所示之配線基板之複數個焊墊上接合有焊球之狀態之放大剖面圖。
圖42係表示將圖41所示之多數個配線基板單片化之狀態之剖面圖。
圖43係表示相對於圖4所示之半導體裝置之變化例之概要之主要部分剖面圖。
圖44係表示相對於圖4所示之半導體裝置之另一變化例之概要之主要部分剖面圖。
圖45係表示相對於圖44所示之半導體裝置之變化例之概要之主要部分剖面圖。
圖46係圖45之A部之放大剖面圖。
圖47係表示相對於圖4所示之半導體裝置之另一變化例之概要之主要部分剖面圖。
圖48係圖47之A部之放大剖面圖。
圖49係表示相對於圖4所示之半導體裝置之另一變化例之主要部分剖面圖。
圖50係表示在與圖31~圖34不同之研究例中，積層體傾斜之狀態之說明圖。
圖51係表示對於圖39之研究例之主要部分剖面圖。
(本申請中之揭示形式、基本性術語、用法之說明)
於本申請中，實施態樣之揭示係視需要，方便起見地分為複數個章節等予以揭示，但只要未特別註明並非如此，則該等並非相互獨立單獨者，無論揭示之前後，均為單一之例之各部分、一者為另一者之一部分詳細情況、或者一部分或者全部之變化例等。又，作為原則，相同之部分省略重複之說明。又，實施態樣中之各構成要素除了 特別註明並非如此之情形、以及邏輯上其數量受到限定之情形及根據上下文明確並非如此之情形，則並非必須組成。
同樣地，在實施態樣等之揭示中，關於材料、組成等，即便稱為「包含A之X」等，除了特別註明並非如此之情形及根據上下文明確並非如此情形，並非排除包含A以外之要素者。例如，就成分而言，為「包含A作為主要成分之X」等意思。例如，即便稱為「矽構件」等，勿庸置疑，亦非限定為單純之矽，該「矽構件」為亦包含含有SiGe(矽、鍺)合金或其他以矽為主要成分之多元合金、及其他添加物等之構件者。又，即便鍍金、Cu層、鍍鎳等，除了特別註明並非如此之情形，不僅為單純成分者，亦分別為包含以金、Cu、鎳等為主要成分之構件者。
進而，亦於言及特定之數值、數量時，除了特別註明並非如此之情形、邏輯上該數量受到限定之情形及根據上下文明確並非如此之情形，既可為超過該特定數值之數值，亦可為未達該特定數值之數值。
又，於實施形態之各圖中，同一或者相同之部分以同一或者類似之符號或者參照編號表示，且原則上不重複進行說明。
又，於隨附圖式中，相反地變得繁瑣之情形時、或者與空隙之區別較為明確之情形時，即便剖面，亦存在省略影線等之情形。與此相關地，根據說明等而較為清晰之情形時等，即便平面上閉合之孔，亦存在省略背景之輪廓線之情形。進而，即便並非剖面，為註明並非空隙，或者為註明區域之邊界，而亦存在標註影線或點陣圖案之情形。
(實施形態)
本實施形態係列舉於形成有運算處理電路之半導體晶片上積層形成有記憶體電路之複數個半導體晶片之實施態樣，作為積層有複數 個半導體晶片之半導體裝置之例進行說明。圖1係本實施形態之半導體裝置之立體圖，圖2係圖1所示之半導體裝置之仰視圖。又，圖3係表示圖1所示之將密封體去除之狀態下配線基板上之半導體裝置之內部結構之透視平面圖。又，圖4係沿圖1之A-A線之剖面圖。再者，圖1~圖4中，為便於觀察，而減少端子數進行表示，但端子(接合引線2f、焊墊2g、焊球5)之數量並不限定於圖1~圖4所示之態樣。又，圖3中，為便於觀察邏輯晶片LC與記憶體晶片MC4之俯視下之位置關係或平面尺寸之差異，而以點線表示邏輯晶片LC之輪廓。
<半導體裝置>
首先，利用圖1~圖4，說明本實施形態之半導體裝置1之概要構成。本實施形態之半導體裝置1係包含配線基板2、搭載於配線基板2上之複數個半導體晶片3(參照圖4)及將複數個半導體晶片3密封之密封體(樹脂體)4。
如圖4所示，配線基板2係包含搭載有複數個半導體晶片3之上表面(面、主面、晶片搭載面)2a、與上表面2a為相反側之下表面(面、主面、安裝面)2b、及配置於上表面2a與下表面2b之間之側面2c，且如圖2及圖3所示，於俯視下呈四邊形之外形形狀。於圖2及圖3所示之例中，配線基板2之平面尺寸(俯視下之尺寸、上表面2a及下表面2b之尺寸、外形尺寸)係呈例如一邊之長度為14mm左右之正方形。又，配線基板2之厚度(高度)、即圖4所示之上表面2a至下表面2b為止之距離為例如0.3mm~0.5mm左右。
配線基板2係用以將搭載於上表面2a側之半導體晶片3與未圖示之安裝基板電性連接之插入式基板，且具有將上表面2a側與下表面2b側電性連接之複數個配線層(圖4所示之例為4層)。於各配線層，形成有將複數個配線2d及複數個配線2d間、及相鄰之配線層間絕緣之絕緣層(核心層)2e。又，於配線2d，包含形成於絕緣層2e之上表面或者下表 面之配線2d1、及以在厚度方向上貫通絕緣層2e之方式形成之層間導電路徑即通孔配線2d2。
又，於配線基板2之上表面2a，形成有與半導體晶片3電性連接之端子即複數個接合引線(端子、晶片搭載面側端子、電極)2f。另一方面，於配線基板2之下表面2b，形成有用以與未圖示之安裝基板電性連接之端子、即接合有作為半導體裝置1之外部連接端子之複數個焊球5的複數個焊墊2g。複數個接合引線2f與複數個焊墊2g係經由複數個配線2d而分別電性連接。再者，連接於接合引線2f或焊墊2g之配線2d係與接合引線2f或焊墊2g一體地形成，因此，圖4中將接合引線2f及焊墊2g作為配線2d之一部分表示。
又，配線基板2之上表面2a及下表面2b係由絕緣膜(阻焊膜)2h、2k覆蓋。配線基板2之形成於上表面2a之配線2d係由絕緣膜2h覆蓋。於絕緣膜2h形成有開口部，於該開口部，複數個接合引線2f之至少一部分(與半導體晶片3之接合部、焊接區域)自絕緣膜2h露出。又，配線基板2之形成於下表面2b之配線2d係由絕緣膜2k覆蓋。於絕緣膜2k形成有開口部，於該開口部，複數個焊墊2g之至少一部分(與焊球5之接合部)自絕緣膜2k露出。
又，如圖4所示，與配線基板2之下表面2b之複數個焊墊2g接合之複數個焊球(外部端子、電極、外部電極)5係如圖2所示配置成行列狀(陣列狀、矩陣狀)。又，圖2中雖省略圖示，但接合有複數個焊球5之複數個焊墊2g(參照圖4)亦配置成行列狀(矩陣狀)。將以此方式於配線基板2之安裝面側行列狀地配置複數個外部端子(焊球5、焊墊2g)之半導體裝置稱為面陣列型之半導體裝置。面陣列型之半導體裝置可將配線基板2之安裝面(下表面2b)側有效運用作外部端子之配置空間，因此，於即便外部端子數增大，亦可抑制半導體裝置之安裝面積之增大之方面較佳。即，伴隨高功能化、高積體化，可節省空間地安裝外 部端子數增大之半導體裝置。
又，半導體裝置1係包括搭載於配線基板2上之複數個半導體晶片3。複數個半導體晶片3係積層於配線基板2之上表面2a上。又，複數個半導體晶片3分別具有正面(主面、上表面)3a、與正面3a為相反側之背面(主面、下表面)3b、及位於正面3a與背面3b之間之側面3c，且如圖3所示，於俯視下呈四邊形之外形形狀。藉由以此方式將複數個半導體晶片積層，而即便使半導體裝置1高功能化之情形時，亦可減少安裝面積。
圖3及圖4所示之例中，搭載於最下段(最接近配線基板2之位置)之半導體晶片3係形成有運算處理電路之邏輯晶片(半導體晶片)LC。另一方面，搭載於邏輯晶片之上段之半導體晶片3係形成有記憶在與邏輯晶片LC之間進行通訊之資料之主記憶電路(記憶電路)的記憶體晶片(半導體晶片)MC1、MC2、MC3、MC4。再者，於邏輯晶片LC，不僅形成有上述運算處理電路，還形成有控制記憶體晶片MC1、MC2、MC3、MC4之主記憶電路之動作的控制電路。又，於邏輯晶片LC，形成有例如快取記憶體等容量小於上述主記憶電路之記憶電路。又，於邏輯晶片LC，形成有在與未圖示之外部機器之間進行信號之輸入輸出之外部介面電路。又，於邏輯晶片LC，形成有在與內部機器(例如記憶體晶片MC1、MC2、MC3、MC4)之間進行信號之輸入輸出之內部介面電路。
將如邏輯晶片LC般使某一裝置或系統之動作所需之電路密集地形成於一個半導體晶片3而成者稱為SoC(System on a Chip(系統單晶片))。又，將如半導體裝置1般使某一裝置或系統之動作所需之電路密集地形成於一個半導體裝置1而成者稱為SIP(System In Package(系統級封裝))。
此處，相應於進行動作之裝置或系統，所需之主記憶電路之容 量進行變化。因此，於圖4所示之例中，搭載與SoC之邏輯晶片LC不同之具備主記憶電路之記憶體晶片MC1、MC2、MC3、MC4，將邏輯晶片LC與記憶體晶片MC1、MC2、MC3、MC4電性連接。藉此，可使邏輯晶片LC及記憶體晶片MC1、MC2、MC3、MC4之通用性提昇。再者，圖4係表示於一個邏輯晶片LC上積層有四個記憶體晶片MC1、MC2、MC3、MC4之例，但半導體晶片3之積層數存在各種變化例。雖省略圖示，但例如作為最小限度之構成，可適用於在一個邏輯晶片LC上搭載一個記憶體晶片MC1之變化例。又，將邏輯晶片LC與記憶體晶片MC1、MC2、MC3、MC4電性連接之方法下文進行詳細說明。
如上所述，根據使邏輯晶片LC及記憶體晶片MC1、MC2、MC3、MC4之通用性提昇之觀點，較佳為，邏輯晶片LC及記憶體晶片MC1、MC2、MC3、MC4之平面尺寸(俯視下之尺寸、正面3a及背面3b之尺寸、外形尺寸)於可達成各半導體晶片3之功能之範圍內最小化。邏輯晶片LC可藉由使電路元件之積體度提昇而減小平面尺寸。另一方面，由於相應於平面尺寸，主記憶電路之容量或傳送速度(例如受到資料匯流排寬度影響之資料傳送量)產生變化，因此，平面尺寸之小型化中存在限度。
因此，於圖4所示之例中，記憶體晶片MC4之平面尺寸大於邏輯晶片LC之平面尺寸。例如，相對於記憶體晶片MC4之平面尺寸係一邊之長度為8mm~10mm左右之四邊形，邏輯晶片LC之平面尺寸係一邊之長度為5mm~6mm左右之四邊形。又，雖省略圖示，但圖4所示之記憶體晶片MC1、MC2、MC3之平面尺寸與記憶體晶片MC4之平面尺寸相同。
又，如上所述，於邏輯晶片LC，形成有在與未圖示之外部機器之間進行信號之輸入輸出之外部介面電路，故而，根據縮短與外部機 器之傳送距離之觀點，複數個半導體晶片3之積層順序較佳為將邏輯晶片LC搭載於最下段、即最接近於配線基板2之位置。即，如半導體裝置1般，成為於平面尺寸較小之半導體晶片3(邏輯晶片LC)上，積層平面尺寸較大之半導體晶片3(記憶體晶片MC1、MC2、MC3、MC4)之構成。因此，如圖4所示，於最下段之半導體晶片3(邏輯晶片LC)之周緣部之外側之區域，在上段側之半導體晶片3(記憶體晶片MC1)與配線基板2之上表面2a之間產生間隙。
本實施形態係以填充該間隙之方式，於上段側之半導體晶片3(記憶體晶片MC1)與配線基板2之上表面2a之間配置接著材(絕緣性接著材)NCL。換言之，上段側之半導體晶片3(記憶體晶片MC1)與配線基板2之上表面2a之間之間隙被接著材NCL填塞。該接著材NCL係包含將邏輯晶片LC接著固定配線基板2上之接著材(絕緣性接著材)NCL1、及將記憶體晶片MC1接著固定於邏輯晶片LC上之接著材(絕緣性接著材)NCL2。
本實施形態中，如圖4所示，接著材NCL1之周緣部、尤其側面(與邏輯晶片LC之側面排列之面)被接著材NCL2覆蓋。而且，接著材NCL2如圖4所示，以覆蓋記憶體晶片(至少記憶體晶片MC1)之側面之方式，形成有圓角。進而，該接著材NCL2之圓角之一部分相較記憶體晶片之周緣部(側面)形成於外側(與邏輯晶片LC分離之方向)。又，接著材NCL1、NCL2分別包含絕緣性(非導電性)之材料(例如樹脂材料)。因此，可將相互地相鄰之接合部(邏輯晶片LC與配線基板2之接合部、邏輯晶片LC與記憶體晶片MC1之接合部)間電性絕緣。關於利用接著材NCL將記憶體晶片MC1與配線基板2之上表面2a之間之間隙填塞之詳細方法、及其效果，在說明隨後描述之半導體裝置之製造方法時詳細地進行說明。
又，圖4所示之例係於複數個記憶體晶片MC1、MC2、MC3、 MC4之間，配置與密封體4不同之密封體(晶片積層體用密封體、晶片積層體用樹脂體)6，且將記憶體晶片MC1、MC2、MC3、MC4之積層體MCS利用密封體6進行密封。密封體6係以密接於複數個記憶體晶片MC1、MC2、MC3、MC4之正面3a及背面3b之方式填充，且利用各半導體晶片3間之接合部及密封體6將記憶體晶片MC1、MC2、MC3、MC4之積層體MCS一體化。又，密封體6係包含絕緣性(非導電性)之材料(例如樹脂材料)，且可藉由於記憶體晶片MC1、MC2、MC3、MC4之各接合部配置密封體6，而將設置於各接合部之複數個電極間電性絕緣。但，如圖4所示，記憶體晶片MC1、MC2、MC3、MC4之積層體MCS中之搭載於最下段(最接近於邏輯晶片LC之位置)之記憶體晶片MC1之正面4a自密封體6露出。又，如圖3及圖4所示，記憶體晶片MC1、MC2、MC3、MC4之積層體MCS中之配置於最上段之記憶體晶片MC4之背面4b自密封體6露出。
又，半導體裝置1具備將複數個半導體晶片3密封之密封體4。密封體4具有上表面(面、正面)4a、位於上表面4a之相反側之下表面(面、背面)4b(參照圖4)、及位於上表面4a與下表面4b之間之側面4c，且俯視下呈四邊形之外形形狀。圖1所示之例中，密封體4之平面尺寸(自上表面4a側俯視時之尺寸、上表面4a之外形尺寸)係與配線基板2之平面尺寸相同，且密封體4之側面4c係與配線基板2之側面2c相連。又，圖1所示之例中，密封體4之平面尺寸(俯視下之尺寸)呈例如一邊之長度為14mm左右之正方形。
密封體4係保護複數個半導體晶片3之樹脂體，且可藉由密接於複數個半導體晶片3間及半導體晶片3與配線基板2，形成密封體4，而抑制較薄之半導體晶片3之損傷。又，密封體4係考慮到使作為保護構件之功能提昇之觀點而包含例如以下之材料。對於密封體4，由於要求易於密接於半導體晶片3及配線基板2，且密封後要求一定程度之硬 度，故較佳為含有例如環氧系樹脂等熱固性樹脂。又，為使硬化後之密封體4之功能提昇，較佳為，將例如矽石(二氧化矽；SiO2)粒子等填料粒子混合於樹脂材料中。例如，就抑制密封體4形成後之熱變形造成之半導體晶片3之損傷之觀點而言，較佳為，調整填料粒子之混合比例，使半導體晶片3與密封體4之線膨脹係數接近。
<半導體晶片之詳細情況>
其次，對圖3及圖4所示之邏輯晶片LC及記憶體晶片MC1、MC2、MC3、MC4之詳細情況及各半導體晶片3之電性連接方法進行說明。圖5係圖4所示之A部之放大剖面圖。又，圖6係表示圖4所示之記憶體晶片之正面側之平面圖，圖7係表示圖6所示之記憶體晶片之背面側之一例之平面圖。又，圖8係表示圖4所示之邏輯晶片之正面側之平面圖，圖9係表示圖8所示之邏輯晶片之背面側之一例之平面圖。又，圖10係圖4之B部之放大剖面圖。再者，圖5~圖9中為便於觀察，而減少電極數進行表示，但電極(正面電極3ap、背面電極3bp、貫通電極3tsv)之數並不限定於圖5~圖9所示之態樣。又，圖7中，表示記憶體晶片MC1、MC2、MC3之背面圖，但未形成背面電極3bp之記憶體晶片MC4(參照圖4)之背面之結構係示於圖3中，故省略圖示。
本案發明者研究了使SIP型之半導體裝置之性能提昇之技術，而作為其一個環節，對於使搭載於SIP之複數個半導體晶片間之信號傳送速度提昇至例如12Gbps(每秒12十億位元)以上之技術進行了研究。作為使搭載於SIP之複數個半導體晶片間之傳送速度提昇之方法，存在有增加內部介面之資料匯流排之寬度，從而使1次傳送之資料量增加之方法(以下，記作匯流排寬度擴大化)。又，作為其他方法，存在有使每一單位時間之傳送次數增加之方法(以下，記作高時脈化)。又，存在將上述匯流排寬度放大法與時脈數增加法組合地應用之方法。利用圖1~圖4所說明之半導體裝置1係藉由組合地應用匯流排寬度擴大 化與高時脈化，而使內部介面之傳送速度提昇至12Gbps以上之半導體裝置。
例如圖4所示之記憶體晶片MC1、MC2、MC3、MC4係分別具有512bit之資料匯流排之寬度的所謂寬I/O記憶體。詳細而言，記憶體晶片MC1、MC2、MC3、MC4係分別具備4個資料匯流排之寬度為128bit之通道，若將該4通道之匯流排寬度進行合計則達到512bit。又，各通道之每一單位時間之傳送次數係經高時脈化而例如分別達到3Gbps以上。
於以此方式，組合地應用高時脈化與匯流排寬度擴大化之情形時，必須使大量之資料線以高速動作，故考慮到減少雜訊之影響之觀點，必須縮短資料之傳送距離。因此，如圖4所示，將邏輯晶片LC與記憶體晶片MC1經由配置於邏輯晶片LC與記憶體晶片MC1之間之導電性構件而電性連接。又，複數個記憶體晶片MC1、MC2、MC3、MC4係分別經由配置於複數個記憶體晶片MC1、MC2、MC3、MC4之間之導電性構件而電性連接。換言之，半導體裝置1係於邏輯晶片LC與記憶體晶片MC1之間之傳送路徑，不含配線基板2或未圖示之線(接合線)。又，半導體裝置1係於複數個記憶體晶片MC1、MC2、MC3、MC4間之傳送路徑，不含配線基板2或未圖示之線(接合線)。
於本實施形態中，作為將複數個半導體晶片3彼此直接地連接之方法，應用如下技術：形成在厚度方向上貫通半導體晶片3之貫通電極，且將經由該貫通電極所積層之半導體晶片3彼此連接。詳細而言，邏輯晶片LC具有形成於正面3a之複數個正面電極(電極、焊墊)3ap、及形成於背面3b之複數個背面電極(電極、焊墊)3bp。又，邏輯晶片LC係具有以自正面3a及背面3b中之一者朝向另一者貫通之方式形成，且將複數個正面電極3ap與複數個背面電極3bp電性連接之複數個貫通電極3tsv。
半導體晶片3所具備之各電路係形成於半導體晶片3之正面3a側。詳細而言，半導體晶片3具備例如含矽(Si)之半導體基板(省略圖示)，且於半導體基板之主面(元件形成面)，形成有例如電晶體等複數個半導體元件(省略圖示)。於半導體基板之主面上(正面3a側)，積層有具備複數個配線與將複數個配線間絕緣之絕緣膜之配線層(省略圖示)。配線層之複數個配線係與複數個半導體元件分別電性連接，從而構成電路。形成於半導體晶片3之正面3a(參照圖3)之複數個正面電極3ap係經由設置於半導體基板與正面3a之間之配線層而與半導體元件電性連接，從而構成電路之一部分。
因此，如圖5所示，形成在厚度方向上貫通半導體晶片3之貫通電極3tsv，且經由貫通電極3tsv將正面電極3ap與背面電極3bp電性連接，藉此，可將形成於背面電極3bp與正面3a側之半導體晶片3之電路電性連接。即，如圖5所示，若將記憶體晶片MC1之正面電極3ap與邏輯晶片LC之背面電極3bp，經由突起電極(導電性構件、凸塊電極)7等導電性構件而電性連接，則記憶體晶片MC1之電路與邏輯晶片LC之電路經由貫通電極3tsv而電性連接。
本實施形態係搭載於記憶體晶片MC1與配線基板2之間之邏輯晶片LC具有複數個貫通電極3tsv。因此，可藉由經由貫通電極3tsv將記憶體晶片MC1與邏輯晶片LC電性連接，而自邏輯晶片LC與記憶體晶片MC1之間之傳送路徑，排除配線基板2或未圖示之線(接合線)。其結果，可減少邏輯晶片LC與記憶體晶片MC1之間之傳送路徑中之阻抗成分，從而減少因高時脈化造成之雜訊之影響。換言之，即便使邏輯晶片LC與記憶體晶片MC1之間之信號傳送速度提昇之情形時，亦可使傳送可靠性提昇。
又，圖5所示之例係於邏輯晶片LC上積層複數個記憶體晶片MC1、MC2、MC3、MC4，因此，較佳為，即便該複數個記憶體晶片 MC1、MC2、MC3、MC4間，亦使信號傳送速度提昇。因此，複數個記憶體晶片MC1、MC2、MC3、MC4中，上下地分別配置半導體晶片3。記憶體晶片MC1、MC2、MC3係與邏輯晶片LC同樣地具有複數個貫通電極3tsv。詳細而言，記憶體晶片MC1、MC2、MC3各自具有形成於正面3a之複數個正面電極(電極、焊墊)3ap、及形成於背面3b之複數個背面電極(電極、焊墊)3bp。又，記憶體晶片MC1、MC2、MC3各自具有以自正面3a及背面3b中之一者朝向另一者貫通之方式形成，且將複數個正面電極3ap與複數個背面電極3bp電性連接之複數個貫通電極3tsv。
因此，與上述邏輯晶片LC之情形同樣地，若記憶體晶片MC1、MC2、MC3、MC4中，將上段側之半導體晶片3之正面電極3ap與下段側之半導體晶片3之背面電極3bp，經由突起電極(導電性構件、凸塊電極)7等導電性構件而電性連接，則經積層之複數個半導體晶片3之電路經由貫通電極3tsv而電性連接。
因此，可自記憶體晶片MC1、MC2、MC3、MC4之間之傳送路徑，排除配線基板2或未圖示之線(接合線)。其結果，可減少經積層之複數個記憶體晶片MC1、MC2、MC3、MC4之間之傳送路徑中之阻抗成分，從而減少因高時脈化造成之雜訊之影響。換言之，即便使複數個記憶體晶片MC1、MC2、MC3、MC4之間之信號傳送速度提昇之情形時，亦可使傳送可靠性提昇。
再者，圖5所示之例係將搭載於最上段之記憶體晶片MC4與記憶體晶片MC3連接即可，因此，形成複數個正面電極3ap，但未形成複數個背面電極3bp及複數個貫通電極3tsv。如此般，可藉由採用搭載於最上段之記憶體晶片MC4不具備複數個背面電極3bp及複數個貫通電極3tsv之結構，而使記憶體晶片MC4之製造步驟簡化。其中，雖省略圖示，但作為變化例，記憶體晶片MC4亦可與記憶體晶片MC1、 MC2、MC3同樣地，設為具備複數個背面電極3bp及複數個貫通電極3tsv之結構。於該情形時，可藉由使經積層之複數個記憶體晶片MC1、MC2、MC3、MC4成為同一之結構，而使製造效率提昇。
又，配置於經積層之半導體晶片3之間且將上段側之半導體晶片3之正面電極3ap與下段側之半導體晶片3之3bp電性連接之突起電極7係於圖5所示之例中採用例如以下之材料。即，突起電極7係於形成為柱狀(例如圓柱形)之以銅(Cu)為主成分之構件之前端，積層鎳(Ni)膜、焊料(例如SnAg)膜而成之金屬構件，且藉由使前端之焊料膜接合於背面電極3bp而電性連接。但，構成突起電極7之材料可於滿足電氣特性方面之要求、或者接合強度方面之要求之範圍內適用各種變化例。例如，可將焊料材接合於正面電極3ap之露出面，使該焊料材成為突起電極7。
又，如圖5所示之邏輯晶片LC或記憶體晶片MC1、MC2、MC3般，具備貫通電極3tsv之半導體晶片3較佳為使厚度、即正面3a與背面3b之間隔距離變薄(變小)。若使半導體晶片3之厚度變薄，則貫通電極3tsv之傳送距離縮短，因此，就可減少阻抗成分而言較佳。又，於半導體基板之厚度方向形成開口部(包含貫通孔及不貫通之孔)之情形時，孔之深度越深，則加工精度越下降。換言之，若使半導體晶片3之厚度變薄，則可使用以形成貫通電極3tsv之開口部之加工精度提昇。因此，可使複數個貫通電極3tsv之直徑(相對半導體晶片3之厚度方向為正交方向之長度、寬度)一致，因此，變得易於控制複數個傳送路徑之阻抗成分。
圖5所示之例中，邏輯晶片LC之厚度T1係薄於配置於邏輯晶片LC上之複數個記憶體晶片MC1、MC2、MC3、MC4之積層體MCS(參照圖4)之厚度TA。又，邏輯晶片LC之厚度T1係薄於複數個記憶體晶片MC1、MC2、MC3、MC4中搭載於最上段且未形成貫通電極3tsv之 記憶體晶片MC4之厚度T2。例如，邏輯晶片LC之厚度T1為50μm。與此相對，記憶體晶片MC4之厚度為80μm~100μm左右。又，複數個記憶體晶片MC1、MC2、MC3、MC4之積層體MCS(參照圖4)之厚度TA為260μm左右。
如上所述，於將半導體晶片3薄型化之情形時，在使半導體晶片3露出之狀態下有半導體晶片3損傷之虞。根據本實施形態，如圖4所示，使密封體4密接於複數個半導體晶片3進行密封。因此，密封體4作為半導體晶片3之保護構件發揮功能，從而可抑制半導體晶片3之損傷。即，根據本實施形態，藉由以樹脂密封複數個半導體晶片3，可使半導體裝置1之可靠性(耐久性)提昇。
又，於將具備貫通電極3tsv之半導體晶片3積層之半導體裝置1之情形時，基於傳送距離縮短之觀點，較佳為亦使半導體晶片3與基板2之間隔狹窄化。例如，圖5所示之例中，邏輯晶片LC之正面3a與配線基板2之上表面2a之間隔G1為例如10μm~20μm左右。又，記憶體晶片MC1之正面3a與配線基板2之上表面2a之間隔G2為例如70μm~100μm左右。以此方式，在具備貫通電極3tsv之半導體晶片3積層之半導體裝置1中，較佳為藉由將半導體晶片3之厚度及間隔距離縮小，而實現傳送距離之縮短。
又，本實施形態適用於正面電極3ap及背面電極3bp之俯視下之佈局中，可將記憶體晶片MC1、MC2、MC3、MC4與邏輯晶片LC之間之傳送距離縮短之構成。
如圖6所示，記憶體晶片MC1、MC2、MC3、MC4所具備之複數個正面電極3ap係於正面3a密集地配置於中央部。如圖7所示，記憶體晶片MC1、MC2、MC3所具備之複數個正面電極3ap係於正面3a密集地配置於中央部。如圖5所示，記憶體晶片MC1、MC2、MC3、MC4之複數個正面電極3ap與記憶體晶片MC1、MC2、MC3之複數個背面 電極3bp係分別配置於厚度方向上重疊之位置。
又，如圖8所示，邏輯晶片LC所具備之複數個正面電極3ap中之一部分(複數個正面電極3ap1)係於正面3a密集地配置在中央部。又，邏輯晶片LC所具備之複數個正面電極3ap中之一部分(複數個正面電極3ap2)係沿正面3a之邊(側面3c)而配置於正面3a之周緣部。圖8所示之複數個正面電極3ap中、配置於正面3a之中央部之複數個正面電極3ap1係經由圖5所示之貫通電極3tcv而與背面電極3bp電性連接。即，複數個正面電極3ap1係內部介面用之電極。另一方面，圖8所示之複數個正面電極3ap中、配置於正面3a之周緣部之複數個正面電極3ap2係經由圖4所示之配線基板2而與未圖示之外部機器電性連接。詳細而言，如圖10所示，正面電極3ap2係經由突起電極7及焊料等接合材8而與接合引線2f電性接合。即，複數個正面電極3ap2係外部介面用之電極。
基於縮短複數個半導體晶片3之間之傳送距離之觀點，尤佳為，如圖5所示將內部介面用之正面電極3ap與背面電極3bp配置於厚度方向上重疊之位置，且經由突起電極7而連接之方式。
又，如上所述，邏輯晶片LC之平面尺寸小於記憶體晶片MC1、MC2、MC3、MC4之平面尺寸。又，圖3所示之半導體裝置1係以於俯視下邏輯晶片LC之背面3b之中央部(中央區域)與記憶體晶片MC4之中心部(中央區域)重疊之方式配置。即，於俯視下，記憶體晶片MC4之四個側面3c係相較邏輯晶片LC之四個側面3c配置於外側。換言之，複數個半導體晶片3係以記憶體晶片MC4之四個側面3c位於邏輯晶片LC之四個側面3c與配線基板2之四個側面2c之間之方式，積層地搭載於配線基板2上。又，圖4所示之記憶體晶片MC1、MC2、MC3係配置於俯視下與記憶體晶片MC4重疊之位置(相同之位置)。
因此，於俯視下，記憶體晶片MC1、MC2、MC3、MC4之周緣部 (正面3a及背面3b之周緣部)係配置於與邏輯晶片LC之外側之周邊區域重疊之位置。換言之，於記憶體晶片MC1、MC2、MC3、MC4之周緣部與配線基板2之間，不存在邏輯晶片LC(例如參照圖10)。
因此，為將圖5所示之各半導體晶片3之內部介面用之正面電極3ap與背面電極3bp配置於厚度方向上重疊之位置，較佳為，將至少內部介面用之正面電極3ap與背面電極3bp配置於與邏輯晶片LC在厚度方向上重疊之位置。又，於邏輯晶片LC之周緣部，如圖8所示，配置有外部介面用之複數個正面電極3ap2。因此，於邏輯晶片LC之正面3a，較佳為，將內部介面用之複數個正面電極3ap1密集地配置在正面3a之中央部。
又，如圖6所示，於記憶體晶片MC1、MC2、MC3、MC4之正面3a側(詳細而言為半導體基板之主面上)，形成有複數個記憶體區域(記憶電路元件排列區域)MR。圖6所示之例中，形成有與上述4通道對應之四個記憶體區域MR。於各記憶體區域MR陣列狀地配置有複數個記憶體單元(記憶電路元件)。此處，如圖6所示，若將複數個正面電極3ap密集地配置於正面3a之中央部，則可以包圍配置有正面電極群之區域之方式，配置相應於4通道之記憶體區域MR。其結果，可使各記憶體區域MR至正面電極3ap為止之距離均等化。即，可將複數個通道各自之傳送距離等長度化，故在可減少每一通道之傳送速度之誤差之方面較佳。
順帶而言，於將圖8所示之密集於邏輯晶片LC之正面3a之中央部之正面電極3ap1用作內部介面專用之電極之情形時，可使正面電極3ap1即便不與圖5所示之配線基板2電性連接亦發揮作用。然而，如圖5所示，於將正面電極3ap1之一部分與配線基板2之接合引線2f電性連接之情形時，於可將正面電極3ap1之一部分用作外部介面用之電極之方面較佳。
例如，於記憶體晶片MC1、MC2、MC3、MC4，形成有用以使未圖示之記憶體電路驅動之未圖示之驅動電路，但作為對該驅動電路供給電源電位(第1基準電位)或基準電位(與第1基準電位不同之第2基準電位，例如接地電位)之端子，可考慮利用正面電極3ap1之一部分。於藉由高時脈化而使信號傳送速度提昇之情形時，考慮到抑制瞬間性之電壓下降等造成之動作之不穩定化之觀點，較佳為，將電源之供給源與消耗電源之電路間之傳送距離縮短。因此，若對邏輯晶片LC之正面電極3ap1之一部分供給電源電位或基準電位，則於可將形成有消耗電源之電路之記憶體晶片MC1、MC2、MC3、MC4至驅動電路為止之距離縮短之方面較佳。
<半導體裝置之製造方法>
其次，對利用圖1~圖10說明之半導體裝置1之製造步驟進行說明。半導體裝置1係按照圖11所示之流程製造。圖11係表示利用圖1~圖10說明之半導體裝置之製造步驟之概要之說明圖。關於各步驟之詳細情況，利用圖12~圖42，進行以下說明。
<基板準備步驟>
首先，圖11所示之基板準備步驟係準備圖12~圖15所示之配線基板20。圖12係表示圖11所示之基板準備步驟中所準備之配線基板之整體結構之平面圖，圖13係相當於圖12所示之1個器件區域之放大平面圖。又，圖14係沿圖13之A-A線之放大剖面圖。又，圖15係表示圖13之相反側之面之放大平面圖。再者，圖12~圖15中，為便於觀察，而將端子數減少進行表示，但端子(接合引線2f、焊墊2g)之數並不限定於圖12~圖15所示之態樣。
如圖12所示，本步驟中所準備之配線基板20係於框部(外框)20b之內側具有複數個器件區域20a。詳細而言，複數個(圖12為27個)器件區域20a係行列狀配置。複數個器件區域20a係分別相當於圖1~圖4 所示之配線基板2。配線基板20係包含複數個器件區域20a、及於各器件區域20a之間包含切晶線(切晶區域)20c之所謂多數個基板。可藉由以此方式，利用具備複數個器件區域20a之多數個基板，而使製造效率提昇。
又，如圖13及圖14所示，於各器件區域20a，分別形成有利用圖4說明之配線基板2之構成構件。配線基板20係包含上表面2a、上表面2a之相反側之下表面2b、及將上表面2a側與下表面2b側電性連接之複數個配線層(圖4所示之例為4層)。於各配線層，形成有使複數個配線2d及複數個配線2d間、以及相鄰之配線層間絕緣之絕緣層(核心層)2e。又，於配線2d，包含形成於絕緣層2e之上表面或者下表面之配線2d1、及以於厚度方向上貫通絕緣層2e之方式形成之層間導電路徑即通孔配線2d2。
又，如圖13所示，配線基板20之上表面2a係包含於圖11所示之第1晶片搭載步驟中，搭載圖8所示之邏輯晶片LC之預定區域即晶片搭載區域(晶片搭載部)2p1。晶片搭載區域2p1係於上表面2a，存在於器件區域20a之中央部。再者，圖13中為表示晶片搭載區域2p1之位置，而以2點鏈線表示晶片搭載區域之輪廓，但晶片搭載區域2p1係如上所述搭載邏輯晶片LC之預定區域，故無需存在實際上可視認之邊界線。
又，配線基板20之上表面2a係形成有複數個接合引線(端子、晶片搭載面側端子、電極)2f。接合引線2f係於圖11所示之第1晶片搭載步驟中，與形成於圖8所示之邏輯晶片LC之正面3a之複數個正面電極3ap電性連接之端子。本實施形態係以使邏輯晶片LC之正面3a側與配線基板20之上表面2a對向之所謂倒裝焊接安裝方式搭載邏輯晶片LC，故而，使複數個接合引線2f之接合部形成於晶片搭載區域2p1之內側。
又，配線基板20之上表面2a係被絕緣膜(阻焊膜)2h所覆蓋。於絕緣膜2h形成有開口部2hw，且於該開口部2hw，複數個接合引線2f之至少一部分(與半導體晶片之接合部、焊接區域)自絕緣膜2h露出。
另一方面，如圖15所示，於配線基板20之下表面2b形成有複數個焊墊2g。配線基板20之下表面2b係被絕緣膜(阻焊膜)2k所覆蓋。於絕緣膜2k形成有開口部2kw，且於該開口部2kw，複數個焊墊2g之至少一部分(與焊球5之接合部)自絕緣膜2k露出。
又，如圖14所示，複數個接合引線2f與複數個焊墊2g係經由複數個配線2d而分別電性連接。該等複數個配線2d、複數個接合引線2f及複數個焊墊2g等之導體圖案係例如由以銅(Cu)為主成分之金屬材料形成。又，複數個配線2d、複數個接合引線2f及複數個焊墊2g係利用例如電解電鍍法而形成。又，如圖14所示，具有4層以上(圖14為4層)之配線層之配線基板20可藉由例如增層法而形成。
<第1接著材配置步驟>
其次，圖11所示之第1接著材配置步驟係如圖16及圖17所示，於配線基板20之上表面2a之晶片搭載區域2p1上配置接著材NCL1。圖16係表示在圖13所示之晶片搭載區域配置有接著材之狀態之放大平面圖，圖17係沿圖16之A-A線之放大剖面圖。再者，圖16為表示晶片搭載區域2p1及晶片搭載區域2p2之位置，而分別以2點鏈線表示晶片搭載區域2p1、2p2之輪廓，但晶片搭載區域2p1、2p2係分別搭載邏輯晶片LC及積層體MCS之預定區域，無需存在實際上可視認之邊界線。再者，以下，於圖示晶片搭載區域2p1、2p2之情形時，同樣地無需存在實際上可視認之邊界線。
一般而言，於利用倒裝焊接安裝方式(倒裝晶片連接方式)將半導體晶片搭載於配線基板上之情形時，將半導體晶片與配線基板電性連接後，實施以樹脂將連接部分密封之方式(後注入方式)。於該情形 時，自配置於半導體晶片與配線基板之間隙之附近之噴嘴供給樹脂，利用毛細管現象將樹脂填入至間隙。
另一方面，本實施形態係於隨後描述之第1晶片搭載步驟中，將邏輯晶片LC(參照圖8)搭載於配線基板20上之前，以將接著材NCL1配置於晶片搭載區域2p1，且自接著材NCL1上壓抵邏輯晶片LC，使之與配線基板20電性連接之方式(先塗佈方式)，搭載邏輯晶片LC。
於上述後注入方式之情形時，由於利用毛細管現象，將樹脂填入至間隙，因此，對一個器件區域20a之處理時間(將樹脂注入之時間)變長。另一方面，於上述先塗佈方式之情形時，在邏輯晶片LC之前端(例如，形成於圖5或圖10所示之突起電極7之前端之焊料材)與接合引線2f之接合部接觸之時間點，已於配線基板20與邏輯晶片LC之間填入有接著材NCL1。因此，於與上述後注入方式相比，可將對一個器件區域20a之處理時間縮短，使製造效率提昇之方面較佳。
又，先塗佈方式中所使用之接著材NCL1係如上所述，包含絕緣性(非導電性)之材料(例如樹脂材料)。
又，接著材NCL1係包含藉由施加能量而硬度(hardness)變硬(變高)之樹脂材料，本實施形態係包含例如熱固性樹脂。又，硬化前之接著材NCL1係相較圖5及圖10所示之突起電極7柔軟，且藉由壓抵邏輯晶片LC而變形。
又，硬化前之接著材NCL1係因操作方法之差異而大致分為以下之2個種類。一個具有包含稱為NCP(Non-Conductive Paste)之膏狀之樹脂(絕緣材膏)，且自未圖示之噴嘴對晶片搭載區域2p1進行塗佈之方式。另1個具有包含稱為NCF(Non-Conductive Film(非導電膜))之預先成形為膜狀之樹脂(絕緣材膜)，且以膜狀態直接搬送至晶片搭載區域2p1進行貼合之方法。於使用絕緣材膏(NCP)之情形時，如同絕緣材膜(NCF)般無需進行貼合之步驟，因此，相較使用絕緣材膜之情形， 可使對半導體晶片等賦予之應力變小。另一方面，於使用絕緣材膜(NCF)之情形時，相較絕緣材膏(NCP)，保形性較高，因此，易於控制配置接著材NCL1之範圍或厚度。
詳細情況隨後描述，但接著材NCL1較佳為控制配置範圍或厚度，因而，較佳為使用預先形成為膜狀之絕緣材膜(NCF)。圖16及圖17所示之例係表示將作為絕緣材膜(NCF)之接著材NCL1配置於晶片搭載區域2p1上，且以與配線基板20之上表面2a密接之方式進行貼合之例。其中，雖省略圖示，但作為變化例，亦可使用絕緣材膏(NCP)。
接著材NCL1具有在圖11所示之第1晶片接著步驟中將邏輯晶片LC(參照圖4)與配線基板20接著固定之固定材功能。又，接著材NCL1具有藉由將邏輯晶片LC與配線基板2之接合部密封而進行保護之密封材功能。再者，上述密封功能中包含藉由使傳遞至邏輯晶片LC與配線基板2之接合部之應力分散緩和而保護接合部之應力緩和功能。
以滿足上述密封材功能之觀點而言，以包覆邏輯晶片LC與配線基板2之接合部之周圍之方式，配置接著材NCL1即可，因此，僅於與晶片搭載區域2p1重疊之區域配置接著材NCL1即可。又，就使上述固定材功能提昇之觀點而言，較佳為，使接著材NC1之一部分密接於圖10所示之邏輯晶片LC之側面3c，但如圖16所示，無需相較晶片搭載區域2p1較大地伸展配置於外側。
然而，圖16及圖17所示之例係以覆蓋較晶片搭載區域2p1寬廣之範圍之方式配置接著材NCL1。圖16所示之晶片搭載區域2p2係圖11所示之第2晶片搭載步驟中搭載記憶體晶片MC1、MC2、MC3、MC4(參照圖4)之積層體MCS(參照圖4)之預定區域，且內含晶片搭載區域2p1，且平面尺寸大於晶片搭載區域2p1。圖16所示之例係將接著材NCL1之周緣部配置於晶片搭載區域2p1之周緣部與晶片搭載區域2p2之周緣部之間且接近於晶片搭載區域2p2之周緣部之位置。換言之， 接著材NCL1係以覆蓋晶片搭載區域2p2之周緣部附近為止之方式配置。詳細而言，圖16所示之例中，接著材NCL1成為與晶片搭載區域NCL1大致相同之平面尺寸。
如上所述，以覆蓋較晶片搭載區域2p1寬廣之範圍之方式配置接著材NCL1所得之效果將於隨後描述之第2晶片搭載步驟、及密封步驟中詳細地進行說明。
<第1晶片準備步驟>
又，圖11所示之第1晶片準備步驟係準備圖8及圖9所示之邏輯晶片LC。圖18係示意性表示圖7所示之具備貫通電極之半導體晶片之製造步驟之概要之說明圖。又，圖19係示意性表示繼圖18之後的半導體晶片之製造步驟之概要之說明圖。再者，圖18及圖19係以與貫通電極3tsv及貫通電極3tsv電性連接之背面電極3p之製造方法為中心進行說明，且對於貫通電極3tsv以外之各種電路之形成步驟，省略圖示及說明。又，圖18及圖19所示之半導體晶片之製造方法不僅可適用於圖4所示之邏輯晶片LC，亦可適用於記憶體晶片MC1、MC2、MC3之製造方法。
首先，作為晶圓準備步驟，準備圖18所示之晶圓(半導體基板)WH。晶圓WH係例如含矽(Si)之半導體基板，且於俯視下呈圓形。晶圓WH具有作為半導體元件形成面之正面(主面、上表面)WHs及正面WHs之相反側之背面(主面、下表面)WHb。又，晶圓WH之厚度係薄於圖4所示之邏輯晶片LC或記憶體晶片MC1、MC2、MC3之厚度，例如為數百μm。
繼而，作為孔形成步驟，形成用以形成圖5所示之貫通電極3tsv之孔(孔、開口部)3tsh。圖18所示之例係將掩膜25配置於晶圓WH之正面WHs上，實施蝕刻處理，藉此形成孔3tsh。再者，圖4所示之邏輯晶片LC或記憶體晶片MC1、MC2、MC3之半導體元件可例如於本步 驟之後且下一個之配線層形成步驟之前形成。
繼之，於孔3tsh內填入例如銅(Cu)等金屬材料，形成貫通電極3tsv。繼而，作為配線層形成步驟，於晶圓WH之正面WHs上形成配線層(晶片配線層)3d。本步驟係形成圖5或圖10所示之複數個正面電極3ap，將複數個貫通電極3tsv與複數個正面電極3ap分別電性連接。又，本步驟係將圖4所示之邏輯晶片LC或記憶體晶片MC1、MC2、MC3之半導體元件與圖5及圖10所示之複數個正面電極3ap，經由配線層3d而電性連接。藉此，將邏輯晶片LC或記憶體晶片MC1、MC2、MC3之半導體元件經由配線層3d而電性連接。
繼而，作為突起電極形成步驟，於正面電極3ap(參照圖5、圖10)上形成突起電極7。又，在突起電極7之前端形成焊料層8a。該焊料層8a係作為將圖5所示之半導體晶片3搭載於配線基板2或下層之半導體晶片3上時之接合材發揮作用。
繼而，作為圖19所示之背面研磨步驟，將晶圓WH之背面WHb(參照圖18)側進行研磨，使晶圓WH之厚度變薄。藉此，圖5所示之半導體晶片3之背面3b露出。換言之，貫通電極3tsv在厚度方向上貫通晶圓WH。又，複數個貫通電極3tsv係於晶圓WH之背面3b自晶圓WH露出。於圖19所示之例中，背面研磨步驟在由保護如下突起電極7之保護層27支撐晶圓WH之狀態下，使用研磨治具28進行研磨，上述突起電極7係保護玻璃板等支撐基材26及正面WHs側。
繼而，於背面電極形成步驟中，在背面3b形成複數個背面電極3bp，且與複數個貫通電極3tsv電性連接。
繼之，作為單片化步驟，將晶圓WH沿切晶線進行分割，取得複數個半導體晶片3。其後，視需要進行檢查，獲得圖4所示之半導體晶片3(邏輯晶片LC或記憶體晶片MC1、MC2、MC3)。
<第1晶片搭載步驟>
其次，在圖11所示之第1晶片搭載步驟中，如圖20或圖21所示，將邏輯晶片LC搭載於配線基板2上。圖20係表示在圖16所示之配線基板之晶片搭載區域上搭載有邏輯晶片LC之狀態之放大平面圖。又，圖21係沿圖20之A-A線之放大剖面圖。又，圖22~圖24係表示圖11所示之第1晶片搭載步驟之詳細流程之說明圖。圖22係示意性表示於晶片搭載區域上載置有半導體晶片之狀態之說明圖。圖23係表示將圖22所示之搬送治具拆卸，且將加熱治具抵住半導體晶片之背面側之狀態之說明圖。又，圖24係表示將半導體晶片加熱且與配線基板電性連接之狀態之說明圖。
本步驟係如圖21所示，以邏輯晶片LC之正面3a與配線基板2之上表面2a對向之方式，利用所謂倒裝焊接安裝方式(倒裝晶片連接方式)搭載邏輯晶片LC。又，藉由本步驟，而將邏輯晶片LC與配線基板2電性連接。詳細而言，形成於邏輯晶片LC之正面之複數個正面電極3ap與形成於配線基板2之上表面2a之複數個接合引線2f經由突起電極7及接合材8(參照圖5、圖10)而電性連接。以下，對於本步驟之詳細流程，利用圖22~圖24進行說明。
於本步驟中，首先，如圖22所示，在配線基板20之晶片搭載區域2p1上配置邏輯晶片LC(半導體晶片3)。將邏輯晶片LC於背面3b側由保持治具30保持之狀態下搬送至晶片搭載區域2p1上，且以正面3a與配線基板20之上表面2a對向之方式配置於接合材NCL1上。保持治具30具有吸附保持邏輯晶片LC之背面3b之保持面30a，且將邏輯晶片LC在由保持面30a保持之狀態下進行搬送。
又，於邏輯晶片LC之正面3a側形成有突起電極7，且於突起電極7之前端形成有焊料層8a。另一方面，於形成於配線基板20之上表面2a之接合引線2f之接合部，形成有作為用以與突起電極7電性連接之接合材的焊料層8b。又，若為進行加熱處理之前，則接著材NCL1為 硬化前之柔軟之狀態。因此，若使保持治具30接近配線基板20，則將突起電極7壓入至接著材NCL1之內部。
繼而，如圖23所示，將加熱治具31抵住邏輯晶片LC之背面3b側，朝向配線基板20壓抵邏輯晶片LC。如上所述，若為進行加熱處理之前，則接著材NCL1為硬化前之柔軟之狀態，因此，若藉由加熱治具31而將邏輯晶片LC壓入，則邏輯晶片LC將接近配線基板20。若邏輯晶片LC接近配線基板20，則形成於邏輯晶片LC之正面3a之複數個突起電極7之前端(詳細而言為焊料層8a)將接觸於接合引線2f之焊接區域(詳細而言為焊料層8b)。
又，接著材NCL1之厚度(上表面NCL1a與下表面NCL1b間之距離)係至少厚於突起電極7之高度(突出高度)、接合引線2f之厚度、及接合材(焊料層8a、8b)之厚度之合計。因此，若被加熱治具31壓入，則邏輯晶片LC之正面3a側之一部分被接著材NCL1填充。換言之，邏輯晶片LC之側面3c中之至少正面3a側之一部分被嵌入至接著材NCL1。考慮到保護邏輯晶片LC與配線基板20之接合部之觀點，將接著材NCL1填入至邏輯晶片LC與配線基板20之間即可，但可藉由將邏輯晶片LC之正面3a側之一部分由接著材NCL1填充，而在隨後描述之第2晶片搭載步驟中穩定地搭載半導體晶片。詳細情況於第2晶片搭載步驟中進行說明。
又，於邏輯晶片LC形成有背面電極3bp，故必須防止柔軟之接著材NCL1繞進背面3b側，將背面電極3bp覆蓋。因此，如圖23所示，較佳為，於加熱治具31與邏輯晶片LC之間，介置相較加熱治具31及邏輯晶片LC柔軟之構件(低彈性構件)、例如樹脂膜(膜)32，且利用樹脂膜32覆蓋邏輯晶片LC之背面3b。若經由樹脂膜32壓抵邏輯晶片LC，則樹脂膜32將密接於邏輯晶片LC之背面3b，故而，即便使接著材NCL1之厚度變厚，亦可抑制接著材NCL1繞進邏輯晶片LC之背面3b。 又，可藉由利用樹脂膜32覆蓋配置有接著材NCL1之區域整體，而使接著材NCL1之上表面NCL1a平坦化。再者，本實施形態之樹脂膜32係包含例如氟樹脂。
再者，若於使樹脂膜32介置之狀態下，壓抵加熱治具31，則樹脂膜32成為陷入至邏輯晶片LC之狀態。圖23係易於理解地表示樹脂膜32陷入至邏輯晶片LC之狀態，但若接著材NCL1之上表面NCL1a之高度達到邏輯晶片之背面3b之高度以下，則可抑制接著材NCL1繞入邏輯晶片LC之背面3b。
繼之，如圖23所示，於將邏輯晶片LC壓抵於加熱治具31之狀態下，利用加熱治具(熱源)31，將邏輯晶片LC及接著材NCL1加熱。邏輯晶片LC與配線基板20之接合部係藉由圖23所示之焊料層8a、8b分別熔融後一體化，而成為圖24所示之接合材(焊料材)8。即，藉由利用加熱治具(熱源)31，將邏輯晶片LC加熱，而經由接合材8將突起電極7與接合引線2f電性連接。
另一方面，藉由利用圖23所示之加熱治具(熱源)31將接著材NCL1加熱，而使接著材NCL1硬化。藉此，在邏輯晶片LC之一部分被填充之狀態下獲得已硬化之接著材NCL1。又，邏輯晶片LC之背面電極3bp因被樹脂膜32覆蓋，故自已硬化之接著材NCL1露出。再者，無需利用來自加熱治具(熱源)31之熱，使接著材NCL1完全地硬化，而可採用如下實施態樣：於使接著材NCL1所含之熱固性樹脂之一部分以可將邏輯晶片LC固定之程度硬化(預硬化)後，將配線基板20移至未圖示之加熱爐，使剩餘之熱固性樹脂硬化(正式硬化)。至接著材NCL1所含之熱固性樹脂成分整體硬化之正式硬化處理結束為止，需要時間，但可藉由利用加熱爐進行正式硬化處理，而使製造效率提昇。
<第2接著材配置步驟>
其次，圖11所示之第2接著材配置步驟係如圖25所示，於邏輯晶片LC(半導體晶片3)之背面3b上、及自邏輯晶片LC露出之接著材NCL1之上表面(正面)NCL1a上，配置接著材NCL2。圖25係表示於圖20所示之半導體晶片之背面及其周圍配置有接著材之狀態之放大平面圖，圖26係沿圖25之A-A線之放大剖面圖。
如上述圖5所示，本實施形態之半導體裝置1被積層之複數個半導體晶片3中之搭載於最下段(例如第1段)之邏輯晶片LC、及於自下段起計數搭載於第2段之記憶體晶片MC1均利用倒裝焊接安裝方式(倒裝晶片連接方式)進行搭載。因此，如上述第1接著材配置步驟中所說明，於可將對於一個器件區域20a(參照圖25、圖26)之處理時間縮短，使製造效率提昇之方面，較佳為適用上述之先塗佈方式。
又，先塗佈方式中使用之接著材NCL2係如上所述，包含絕緣性(非導電性)之材料(例如樹脂材料)。
又，接著材NCL2係包含藉由施加能量而硬度(hardness)變硬(變高)之樹脂材料，且本實施形態中包含例如熱固性樹脂。又，硬化前之接著材NCL2係相較圖5所示之突起電極7柔軟，且藉由壓抵邏輯晶片LC而變形。
又，硬化前之接著材NCL2因操作方法之差異，而大致分為稱為NCP之膏狀之樹脂(絕緣材膏)、及稱為NCF之預先成形為膜狀之樹脂(絕緣材膜)。作為本步驟中使用之接著材NCL2，可使用NCP及NCF之任一者。圖25及圖26所示之例係自噴嘴33(參照圖26)噴出NCP，於邏輯晶片LC之背面3b上及自邏輯晶片LC露出之接著材NCL1之上表面(露出面、正面)NCL1a上，配置接著材NCL2。
再者，關於自噴嘴33噴出膏狀之接著材NCL2之方面，與上述第1接著材配置步驟中說明之後注入方式共通。然而，本實施形態係於搭載圖4所示之記憶體晶片MC1之前，預先搭載接著材NCL2。因此，若 與利用毛細管現象注入樹脂之後注入方式進行比較，則可大幅度提昇接著材NCL2之塗佈速度。
絕緣材膏(NCP)係與絕緣材膜(NCF)相比，可藉由低負載而與塗佈對象物(本步驟為邏輯晶片LC)密接。又，接著材NCL2係如圖3所示無需朝向記憶體晶片MC4之側面3c之周圍較大地伸展。因此，與上述第1接著材配置步驟中說明之NCP1相比，易於控制厚度或配置範圍。因此，就本步驟時減少對已搭載之邏輯晶片LC之應力之觀點而言，較佳為絕緣材膏(NCP)。但，雖省略圖示，作為變化例，亦可將絕緣材膜(NCF)用作接著材NCL2。
接著材NCL2具有利用圖11所示之第2晶片接著步驟，將記憶體晶片MC1(參照圖4)與邏輯晶片LC(參照圖4)接著固定之固定材功能。又，接著材NCL2具有藉由密封而保護記憶體晶片MC1與邏輯晶片LC之接合部之密封材功能。再者，於上述密封功能中，包含藉由使傳遞至記憶體晶片MC1與邏輯晶片LC之接合部之應力分散緩和而保護接合部的應力緩和功能。
就滿足上述密封材功能之觀點而言，以包覆記憶體晶片MC1與邏輯晶片LC之接合部之周圍之方式配置接著材NCL2即可，因此，僅於邏輯晶片之背面3b上配置接著材NCL2即可。然而，本實施形態係如圖25所示，不僅於邏輯晶片之背面3b上，而且亦於接著材NCL1之上表面NCL1a上，配置接著材NCL2。藉由以此方式，亦於接著材NCL1之上表面NCL1a上配置接著材NCL2，而於利用圖11所示之第2晶片搭載步驟，搭載記憶體晶片MC1、MC2、MC3、MC4(參照圖4)之積層體MCS(參照圖4)時，積層體MCS變得不易傾斜。
又，圖25所示之晶片搭載區域2p2係利用圖11所示之第2晶片搭載步驟搭載記憶體晶片MC1、MC2、MC3、MC4(參照圖4)之積層體MCS(參照圖4)之預定區域。又，晶片搭載區域2p2係於圖25所示之例 中，沿著俯視下呈四邊形之晶片搭載區域2p2之對角線，帶狀地塗佈接著材NCL2。以此方式於接著材NCL2之塗佈區域塗佈呈相互交差之2條帶形狀之膏狀之接著材NCL2之方式(稱為交叉塗佈方式)係於隨後描述之第2晶片搭載步驟中，使接著材NCL2容易均等地伸展之方面較佳。但，於隨後描述之第2晶片搭載步驟中，若為可以不產生間隙之方式使接著材NCL2伸展之方法，則亦可採用與圖25不同之塗佈方法。
又，接著材NCL2之端部係配置於晶片搭載區域2p2之外側。換言之，於第2接著材配置步驟中，配置接著材NCL2之範圍大於晶片搭載區域2p2。可藉由以此方式，對相較晶片搭載區域2p2寬廣之範圍塗佈接著材NCL2，而於圖11所示之第2晶片搭載步驟中，如圖4所示，將記憶體晶片MC1之正面3a與配線基板2之上表面2a之間隙填塞。
<第2晶片準備步驟>
又，圖11所示之第2晶片準備步驟係準備圖4所示之記憶體晶片MC1、MC2、MC3、MC4。作為相對於本實施形態之變化例，可於邏輯晶片LC上依次積層記憶體晶片MC1、MC2、MC3、MC4。然而，本實施形態係對將記憶體晶片MC1、MC2、MC3、MC4預先積層，形成圖28所示之積層體(記憶體晶片積層體、半導體晶片積層體)MCS之實施態樣進行說明。如以下所說明，於形成記憶體晶片MC1、MC2、MC3、MC4之積層體MCS之情形時，例如，可在與除了圖11所示之第2晶片準備步驟以外之步驟不同之場所，與其他步驟獨立地進行。例如，積層體MCS亦可作為採購零件而準備。因此，於可將圖11所示之組裝步驟簡化，作為整體使製造效率提昇之方面較為有利。
圖27係示意性表示圖4所示之記憶體晶片之積層體之組裝步驟之概要之說明圖。又，圖28係示意性表示繼圖27之後之記憶體晶片之積層體之組裝步驟之概要之說明圖。再者，圖27及圖28所示之複數個記 憶體晶片MC1、MC2、MC3、MC4各自之製造方法可適用利用圖18及圖19說明之半導體晶片之製造方法而製造，故而省略說明。
首先，作為組裝基材準備步驟，準備用以組裝圖28所示之積層體MCS之基材(組裝基材)34。基材34具有積層複數個記憶體晶片MC1、MC2、MC3、MC4之組裝面34a，且於組裝面34a設置有接著層35。
其次，作為晶片積層步驟，將記憶體晶片MC1、MC2、MC3、MC4積層於基材34之組裝面34a上。圖27所示之例係以被積層之各半導體晶片之背面3b與基材34之組裝面34a對向之方式，將記憶體晶片MC4、MC3、MC2、MC1以此順序依次地積層。各半導體晶片之突起電極7與背面電極3bp係藉由例如接合材8而接合。又，在配置於最上段之記憶體晶片MC1之突起電極7之前端，形成有用以在圖11所示之第2晶片搭載步驟中將圖26所示之邏輯晶片LC之背面電極3bp與圖27所示之記憶體晶片MC1之突起電極7電性連接之接合材8(例如焊料層8a)。
其次，圖28所示之積層體密封步驟係對被積層之複數個半導體晶片之間，供給樹脂(底部填充樹脂)，形成密封體(晶片積層體用密封體、晶片積層體用樹脂體)6。該密封體6係藉由上述第1接著材配置步驟中說明之後注入方式而形成。即，於預先積層複數個半導體晶片3之後，自噴嘴36供給底部填充樹脂6a，填入至經積層之複數個半導體晶片3之間。底部填充樹脂6a係黏度低於圖11所示之密封步驟中使用之密封用之樹脂，從而可利用毛細管現象，填入至複數個半導體晶片3之間。其後，使填入至半導體晶片3之間之底部填充樹脂6a硬化，從而獲得密封體6。
以該後注入方式形成密封體6之方法係與所謂轉注成形方式(詳細情況隨後描述)相比，間隙之填入特性優異，因此，於經積層之半導 體晶片3之間之間隙狹窄之情形時適用較為有效。又，如圖28所示，於填入底部填充樹脂6a之間隙形成為複數段之情形時，可對複數個間隙，整批地填入底部填充樹脂6a。因此，作為整體可縮短處理時間。
其次，組裝基材去除步驟係將基材34及接著層35，自記憶體晶片MC4之背面3b剝離去除。作為將基材34與接著層35去除方法，可適用例如使接著層35中所含之樹脂成分(例如紫外線硬化樹脂)硬化之方法。藉由以上之步驟，而獲得將複數個記憶體晶片MC1、MC2、MC3、MC4積層，且各記憶體晶片MC1、MC2、MC3、MC4之連接部由密封體6密封之積層體MCS。該積層體MCS可視作具有形成有複數個正面電極3ap之正面3a(記憶體晶片MC1之正面3a)及位於正面3a之相反側之背面3b(記憶體晶片MC4之背面3b)之一個記憶體晶片。
<第2晶片搭載步驟>
其次，圖11所示之第2晶片搭載步驟係如圖29或圖30所示，於邏輯晶片LC上，搭載複數個記憶體晶片MC1、MC2、MC3、MC4之積層體MCS。圖29係表示於圖25所示之邏輯晶片之背面上搭載有記憶體晶片之積層體之狀態之放大平面圖。又，圖30係沿圖29之A-A線之放大剖面圖。
本步驟係如圖30所示，以積層體MCS之正面3a與邏輯晶片LC之背面3b(換言之，配線基板20之上表面2a)對向之方式，利用所謂倒裝焊接安裝方式(倒裝晶片連接方式)搭載積層體MCS。又，藉由本步驟，而將複數個記憶體晶片MC1、MC2、MC3、MC4與邏輯晶片LC電性連接。詳細而言，如圖5所示，將形成於記憶體晶片MC1(或積層體MCS)之正面3a之複數個正面電極3ap與形成於邏輯晶片LC之背面3b之複數個背面電極3bp經由突起電極7(及未圖示之接合材)而電性連接。再者，於圖5中，為便於觀察，而將形成於圖27所示之最上段之突起電極7之前端之接合材8省略圖示。以下，對本步驟之詳細流程， 利用圖31~圖33進行說明。
圖31~圖34係表示圖11所示之第2晶片搭載步驟之詳細流程之說明圖。圖31係示意性表示於邏輯晶片上載置有記憶體晶片之積層體之狀態之說明圖。圖32係表示將圖31所示之搬送治具拆卸，且將加熱治具抵住積層體之背面側之狀態之說明圖。又，圖33係表示將圖31所示之保持治具去除時，積層體傾斜之狀態之說明圖。又，圖34係表示將積層體加熱，而與邏輯晶片電性連接之狀態之說明圖。又，圖50係表示在與圖31~圖34不同之研究例中，積層體傾斜之狀態之說明圖。於圖31~圖34及圖50中，為便於觀察，而將積層體MCS視作一個半導體晶片3進行表示。
本步驟係首先如圖31所示，在搭載於配線基板20之邏輯晶片LC之背面3b上配置積層體MCS(半導體晶片3)。積層體MCS係於背面3b側由保持治具30保持之狀態下搬送至晶片搭載區域2p2上，且以積層體MCS之正面3a與邏輯晶片LC之背面3b對向之方式，配置於接合材NCL2上。保持治具30可使用與利用圖22進行說明之第1晶片搭載步驟相同者。即，保持治具30具有吸附保持積層體MCS之背面3b之保持面30a，且將積層體MCS於由保持面30a保持之狀態下進行搬送。
又，於積層體MCS之正面3a側形成有突起電極7，且於突起電極7之前端，如利用圖27所說明般，形成有焊料層8a(接合材8)。再者，圖31係例示性表示於背面電極3bp之露出面未配置接合材之實施態樣，但作為變化例，亦可將未圖示之接合材(例如焊料層)形成於背面電極3bp之露出面。
又，該階段中之接著材NCL2係進行加熱處理之前，故為柔軟之狀態。因此，將配置於邏輯晶片LC上之積層體MCS之突起電極7如圖31所示，填入(壓入)接著材NCL2內。
繼而，如圖32所示，使加熱治具31抵住積層體MCS之背面3b 側，朝向邏輯晶片LC及接著材NCL1，壓抵積層體MCS。由於與接著材NCL1同樣地，於進行加熱處理之前，接著材NCL2為硬化前之柔軟之狀態，因此，若藉由加熱治具31而將積層體MCS壓入，則積層體MCS接近邏輯晶片LC。若積層體MCS接近邏輯晶片LC，則形成於積層體MCS之正面3a之複數個突起電極7之前端(詳細而言為焊料層8a)與形成於邏輯晶片LC之背面3b之複數個背面電極3bp(或者背面電極3bp上之未圖示之接合材)接觸。又，塗佈於積層體MCS與邏輯晶片LC之間之接著材NCL2係沿著邏輯晶片LC之背面3b及接著材NCL1之上表面NCL1a擴散，積層體MCS與配線基板2之間隙被接著材NCL1及接著材NCL2填塞。
此處，根據本案發明者之研究，於平面尺寸較小之邏輯晶片LC上，搭載平面尺寸較大之積層體MCS(半導體晶片3)之情形時，發現存在以下之課題。即，發現當由圖31所示之搬送治具更換為圖32所示之加熱治具31時，存在平面尺寸較大之積層體MCS以突起電極7為基點而傾斜之情形。
例如，如圖50所示之變化例般，於接著材NCL1僅配置於邏輯晶片LC與配線基板20之間，且未擴散至晶片搭載區域2p2之周緣部之情形時，存在積層體MCS以突起電極7之位置為基點而傾斜之情形。如此般，半導體晶片3傾斜之程度於複數個突起電極7在正面3a密集地配置於中央部之情形時容易變大。其原因在於：若突起電極7密集地配置於正面3a之中央部，則與配置於正面3a之周緣部之情形相比，積層體MCS(半導體晶片3)之平衡容易變得不穩定。
又，若積層體MCS開始傾斜，則傾斜之程度容易增大，直到與其他構件接觸為止。例如，圖50所示之例中，成為積層體MCS之正面3a之周緣部與配線基板20之上表面2a接觸之狀態。如圖50所示，於積層體MCS傾斜之情形時，在該傾斜之狀態下，即便利用圖32所示之加 熱治具31將積層體MCS壓住，亦存在導致突起電極7與背面電極3bp之位置偏移之情形。
對此，本實施形態如圖33所示，以覆蓋相較晶片搭載區域2p1更寬廣之範圍之方式配置接著材NCL1。圖33所示之例中將接著材NCL1以覆蓋至晶片搭載區域2p2之周緣部附近之方式配置。又，接著材NCL1係於第2晶片搭載步驟之前已實施硬化處理施，因此比接著材NCL2更硬。因此，如圖33所示，於積層體MCS之正面3a之周緣部接觸於接著材NCL1之時間點，可使傾斜程度之增加停止。換言之，本實施形態係藉由以覆蓋至晶片搭載區域2p2之周緣部附近之方式配置接著材NCL1，因而即便積層體MCS傾斜之情形時，亦可減輕該傾斜之程度。
其結果，如圖32所示，若將加熱治具31(及樹脂膜32)壓抵於積層體MCS，則可修復積層體MCS之傾斜。此時，若傾斜之程度較小，可抑制突起電極7與背面電極3bp之位置偏移。藉由如此般，覆蓋搭載積層體MCS之預定區域即晶片搭載區域2p2之大部分，而抑制因積層體MCS傾斜造成突起電極7與背面電極3bp之位置偏移。
如上所述，基於抑制突起電極7與背面電極3bp之位置偏移之觀點，於積層體MCS(半導體晶片3)以突起電極7為基點傾斜時，較佳為，以接著材NCL1與積層體MCS最初接觸之程度之平面尺寸及厚度而形成接著材NCL1。詳細而言，較佳為，將接著材NCL1之周緣部配置於相較晶片搭載區域2p1之周緣部更接近於晶片搭載區域2p2之周緣部之位置。又，尤佳為，以覆蓋晶片搭載區域2p2整體之方式配置接著材NCL1。另一方面，若接著材NCL1之配置範圍(接著材NCL1之平面尺寸)大幅地大於晶片搭載區域2p1，則接著材NCL1之使用量增加。又，變得反而難以控制接著材NCL2變大之範圍。因此，尤佳為，接著材NCL1之配置範圍(接著材NCL1之平面尺寸)為與晶片搭載 區域2p2大致相同之大小。
又，較佳為，使接著材NCL1之厚度成為邏輯晶片LC之側面3c中之邏輯晶片LC之正面3a側之一半以上被接著材NCL1覆蓋之程度之厚度。換言之，較佳為，以於剖視下，接著材NCL1之上表面NCL1a相較邏輯晶片LC之側面3c之中央部(一半之高度)位於邏輯晶片LC之背面3b側之方式，形成接著材NCL1。但，若邏輯晶片LC之背面3b側被接著材NCL1覆蓋，則存在將背面電極3bp與突起電極7電性連接時成為阻障之情形。因此，較佳為，使接著材NCL1之上表面NCL1a之高度於邏輯晶片LC之背面3b以下之範圍內儘可能地變高。
根據如此之觀點，如上所述，較佳為，接著材NCL1中使用在易於控制範圍或厚度之方面較為有利之絕緣材膜(NCF)。
又，如圖32所示，於將加熱治具31壓抵於積層體MCS，使接著材NCL2伸展之情形時，較佳為，減少邏輯晶片LC所受之應力。可藉由擴大已硬化之接著材NCL1之配置範圍，而使邏輯晶片LC所受之負載分散至接著材NCL1側。因此，就減少第2晶片搭載步驟中之邏輯晶片LC之應力之觀點而言，較佳為，擴大已硬化之接著材NCL1之配置範圍。
再者，圖32所示之例係於積層體MCS未形成背面電極3bp，故可將圖32所示之加熱治具31與積層體MCS之間未介置樹脂膜32之實施態樣適用作變化例。然而，於圖11所示之第1晶片搭載步驟與第2晶片搭載步驟中，可藉由使用相同之搭載裝置(保持治具30、加熱治具31、及樹脂膜32)，而抑制製造裝置變得繁瑣。因此，較佳為，與第1晶片搭載步驟同樣地，經由樹脂膜32，使用加熱治具31壓抵積層體MCS。
又，如圖50所示，即便於接著材NCL1之配置範圍較小之情形時，亦可填充積層體MCS與配線基板20之間隙。即，如上所述，若為突起電極7與背面電極3bp之位置未偏移之情形，則可將圖50所示之實 施態樣適用作變化例。即便該情形時，若使接著材NCL2之塗佈量(配置量)增加，則於配置有接著材NCL1之區域之外側，亦可藉由接著材NCL2而將積層體MCS與配線基板20之間隙填塞。但，尤其於接著材NCL2使用絕緣材膏(NCP)之情形時，若塗佈量增加，則難以進行變大之範圍之控制。因此，就控制接著材NCL2之配置範圍，將積層體MCS與配線基板20之間隙確實地填塞之觀點而言，較佳為，如圖33所示，將接著材NCL1之周緣部配置於相較晶片搭載區域2p1之周緣部接近於晶片搭載區域2p2之周緣部之位置。
其次，如圖33所示，在積層體MCS壓抵於加熱治具31之狀態下，藉由加熱治具(熱源)31，而將邏輯晶片LC及接著材NCL2加熱。積層體MCS與邏輯晶片LC之接合部係因圖33所示之焊料層8a熔融，將背面電極3bp潤濕，而成為圖34所示之接合材(焊料材)8。即，利用加熱治具(熱源)31將積層體MCS加熱，藉此，將積層體MCS之突起電極7與邏輯晶片LC之背面電極3bp經由接合材8而電性連接。
另一方面，利用圖32所示之加熱治具(熱源)31將接著材NCL1加熱，藉此，接著材NCL1硬化(預硬化)。藉此，如圖34所示，積層體MCS與配線基板20之間隙被已硬化之接著材NCL1及接著材NCL2填塞。積層體MCS之側面3c之正面3a側之一部分係由接著材NCL2覆蓋。因此，可使積層體MCS與邏輯晶片LC之接著強度提昇。再者，無需利用來自圖32所示之加熱治具(熱源)31之熱使接著材NCL2完全硬化，而可採取於使接著材NCL2所含之熱固性樹脂之一部分硬化(預硬化)至可將邏輯晶片LC固定之程度後，將配線基板20移入至未圖示之加熱爐，使剩餘之熱固性樹脂硬化(正式硬化)之實施態樣。直至接著材NCL2所含之熱固性樹脂成分整體硬化之正式硬化處理結束為止，需要時間，但可藉由利用加熱爐進行正式硬化處理，而使製造效率提昇。
<密封步驟>
其次，圖11所示之密封步驟係如圖35所示，利用樹脂將配線基板20之上表面2a、邏輯晶片LC及複數個記憶體晶片MC1、MC2、MC3、MC4之積層體MCS密封，形成密封體4。圖35係表示在圖30所示之配線基板上形成密封體，將經積層之複數個半導體晶片密封之狀態之放大剖面圖。又，圖36係表示圖35所示之密封體之整體結構之平面圖。
本實施形態係如圖36所示，形成將複數個器件區域20a整批地密封之密封體4。如此之密封體4之形成方法係稱為整批密封(Block Molding，區塊封膠)方式，且將藉由該整批密封方式而製造之半導體封裝稱為MAP(Multi Array Package，多陣列封裝)型之半導體裝置。整批密封方式可使各器件區域20a之間隔變小，因此，1片配線基板20中之有效面積變大。即，可自1片配線基板20取得之製品個數增加。可藉由如此般，增大1片配線基板20中之有效面積，而使製造步驟效率化。
又，本實施形態係於將經加熱軟化之樹脂壓入至成形模具內進行成形後，利用使樹脂熱硬化之所謂轉注成形方式形成密封體4。由轉注成形方式形成之密封體4係例如將圖35所示之積層體MCS密封之密封體6般，與使液狀樹脂硬化者相比，耐久性較高，故作為保護構件較為適合。又，例如可藉由將矽石(二氧化矽；SiO2)粒子等填料粒子混合於熱固性樹脂中，而使密封體4之功能(例如，對於翹曲變形之耐受性)提昇。以下，對本步驟之詳細流程，利用圖37~圖40進行說明。
圖37~圖40係表示圖11所示之密封步驟之詳細流程之說明圖。圖37係表示於使密封體成形之成形模具內配置有圖30所示之配線基板之狀態之主要部分剖面圖。又，圖38係表示對圖37所示之成形模具內供 給樹脂之狀態之主要部分剖面圖，圖39係表示圖37所示之成形模具內被樹脂充滿之狀態之主要部分剖面圖。又，圖40係表示將圖39所示之配線基板自成形模具中取出之狀態之主要部分剖面圖。又，圖51係表示針對圖39之研究例之主要部分剖面圖。圖37~圖40及圖51中，為便於觀察，而將積層體MCS視作一個半導體晶片3進行表示。
本步驟係首先準備圖37所示之成形模具40(模具準備步驟)。成形模具40係用以使圖35所示之密封體4成形之模具，且具備包含下表面(模具面)41a、及形成於下表面41a之模腔(凹部、凹陷部)41z之上模具(模具)41。又，成形模具40具備包含與上模具41之下表面(模具面)41a對向之上表面(模具面)42a之下模具(模具)42。
模腔41z係於俯視下為四角錐台形之槽(凹陷部)，且包含底面及4個側面。又，於上模具41分別形成有朝向模腔41z之樹脂4p(參照圖38)之供給口即澆口部41g、及配置於與澆口部41g不同之位置(例如對向之位置)之排氣孔部41v。澆口部41g係形成於例如模腔41z之一個側面。又，排氣孔部41v係形成於與澆口部41g不同之模腔41z之側面。以此方式將澆口部配置於模腔41z之側面之方式係稱為側澆口方式。
繼而，於成形模具40之下模具42上配置配線基板20(基材配置步驟)。此處，形成於與下模具42組合之上模具41之模腔41z係面積大於配線基板20之各器件區域20a，且以覆蓋複數個器件區域20a之方式配置一個模腔41z。換言之，模腔41z之周緣部係配置於配線基板20之框部20b上。
繼之，使上模具41與下模具42之距離靠近，利用上模具41與下模具42夾鉗配線基板20(夾鉗步驟)。藉此，於模腔41z內、澆口部41g、及排氣孔部41v以外之區域，上模具41(上模具41之下表面41a)與配線基板20之上表面2a密接。又，下模具42(下模具42之上表面42a)與配線基板20之下表面2b密接。
繼而，如圖38所示，對模腔41z內供給樹脂4p，使該樹脂4p硬化，藉此，形成密封體4(密封體形成步驟)。於本步驟中，使配置於未圖示之罐部之樹脂片加熱軟化，並自澆口部41g對模腔41z內供給樹脂4p。樹脂片係例如以作為熱固性樹脂之環氧系樹脂為主成分，且藉由於低於硬化溫度之溫度下進行加熱而軟化，具有流動性提昇之特性。因此，例如若利用未圖示之柱塞將經軟化之樹脂片壓入，則如圖38中標註二點鏈線之箭頭所示，經軟化之樹脂4p自形成於成形模具40之澆口部41g被壓入至模腔41z內(詳細而言為配線基板20之上表面2a上)。模腔41z內之氣體因樹脂4p流入之壓力而自排氣孔部41b中被排出，從而於模腔41z內充滿樹脂4p。其結果，搭載於配線基板20之上表面2a側之複數個半導體晶片3(邏輯晶片LC及積層體MCS)如圖39所示被樹脂4p整批地密封。其後，藉由將模腔41z內加熱，而使樹脂4p之至少一部分加熱硬化(預硬化)。
此處，根據本案發明者之研究，如圖51所示，發現於積層體MCS與配線基板20之間，存在未被接著材NCL1、NCL2填塞之間隙之情形時，在半導體裝置之可靠性之方面存在以下之課題。即，如圖51所示，可知在積層體MCS與配線基板20之間隙容易產生未填充樹脂4p之氣泡(空間)VD。若於完成品之半導體裝置，在積層體MCS與配線基板20之間殘留有氣泡VD，則半導體裝置受熱時，密封體容易破損。即，成為可靠性下降之原因。
本案發明者對如上所述容易產生氣泡VD之原因進而研究之後，未能確認於將圖51所示之邏輯晶片LC，置換為圖5所示之不具有貫通電極3tsv之半導體晶片之情形時，產生成為可靠性下降原因之氣泡VD。即，發現容易產生上述氣泡VD之現象係於將形成有貫通電極3tsv之邏輯晶片LC搭載於下段側之情形時尤其顯著化之課題。
容易產生氣泡VD之原因被認為與搭載於上段側之積層體MCS與 配線基板20之間隔距離存在關係。於未形成貫通電極3tsv之半導體晶片之情形時，半導體晶片之厚度與電氣特性之關聯性較低，故即便較薄者亦存在100μm左右之厚度。另一方面，於圖5所示之形成有貫通電極3tsv之邏輯晶片LC之情形時，若使邏輯晶片LC之厚度變薄，則貫通電極3tsv之高度(邏輯晶片LC之厚度方向之長度)變小，故可降低將正面電極3ap與背面電極3bp連接之導電路徑之阻抗。因使貫通電極3tsv之高度變小，故加工精度提昇，因而，可實現電路之積體化。因此，邏輯晶片LC係與不存在貫通電極3tsv之半導體晶片相比，厚度變薄。又，搭載於邏輯晶片LC上之積層體MCS與配線基板2(圖51所示之配線基板20)之間隔距離即間隔G2係對應著邏輯晶片LC之厚度T1變小，因此，間隔G2亦變小。例如，本案發明者所研究之邏輯晶片LC之厚度T1為50μm，間隔G2為70μm~100μm左右。
又，為將樹脂4p填入至積層體MCS與配線基板20之間隙，而必須以包覆下段側之邏輯晶片LC及其周圍之接著劑NCL1、NCL2之方式，使樹脂4p繞入，但若積層體MCS與配線基板20之間隙狹窄，則靜壓電阻(電導)變大。尤其，轉注成形方式中使用之樹脂4p(參照圖38)係黏性高於利用圖28說明之液狀之底部填充樹脂6a，因此，難以供給至狹窄之空間。又，若使樹脂4p之供給壓力上升，則成為半導體晶片3損傷之原因。
又，如圖51所示，於積層體MCS與配線基板20之間，存在未被接著材NCL1、NCL2填塞之間隙之情形時，存在樹脂4p中混合之複數個填料粒子FL中之粒徑較大者被間隙夾住之情形。若填料粒子FL夾在積層體MCS與配線基板20之間，則成為將樹脂4p之通路阻塞，產生氣泡VD之原因。又，存在將填料粒子FL壓抵於積層體MCS之正面3a(參照圖5)，成為積層體MCS損傷之原因之情形。
可藉由使複數個填料粒子FL分散於樹脂4p中，而使密封體4(參 照圖35)之功能提昇。然而，填料粒子FL之粒徑多種多樣，粒徑較大者中，亦存在例如具備100μm左右之粒徑之填料粒子FL。因此，若配線基板20與積層體MCS之間隔G2(參照圖5)縮小至70μm~100μm左右，則存在填料粒子FL被配線基板20與積層體MCS之間隙夾住之情形。作為防止夾住填料粒子FL之現象之方法，考慮有將樹脂4p中混合之填料粒子FL預先分級，且將粒徑較大之填料粒子FL排除之方法。然而，於該情形時，填料粒子FL之分級作業消耗時間。又，若變得不能使粒徑較大之填料粒子FL含於樹脂4p中，則材料選擇之自由度下降。因此，較佳為，例如即便使粒徑超過80μm之填料粒子含於FL樹脂4p中，亦不使填料粒子FL夾在配線基板20與積層體MCS之間。
因此，本實施形態係採取如下構成：於密封步驟之前，利用接著材NCL1及接著材NCL2預先將積層體MCS中之未與邏輯晶片LC重疊之部分與配線基板20之上表面2a之間填塞。即，本實施形態係於密封步驟之前，預先消除圖51所示之產生氣泡VD之區域(間隙)、或容易夾住填料粒子FL之區域(間隙)。其結果，如圖39所示，可防止或抑制氣泡VD(參照圖51)之產生。又，例如即便粒徑超過80μm之填料粒子FL包含於樹脂4p之情形，亦可避免在配線基板20與積層體MCS之間夾住填料粒子FL。
再者，根據抑制圖51所示之氣泡VD之產生、或填料粒子FL對積層體MCS之損傷之觀點，配線基板20與積層體MCS之間之構件亦可為接著材NCL1、NCL2中之任一者。但，如上所述，就控制接著材NCL1、NCL2之配置位置，將配線基板20與積層體MCS之間隙確實地填塞之觀點而言，尤佳為利用接著材NCL1、NCL2兩者進行填塞。即，如使用圖16及圖17進行說明般，第1接著材配置步驟中，較佳為將接著材NCL1之周緣部配置於相較晶片搭載區域2p1之周緣部接近於 晶片搭載區域2p2之周緣部之位置。又，於第2接著材配置步驟中，就減少接著材NCL2之塗佈量，容易控制接著材NCL2之配置範圍之觀點而言，較佳為，使接著材NCL1之厚度成為邏輯晶片LC之側面3c中之邏輯晶片LC之正面3a側之一半以上被接著材NCL1覆蓋之程度之厚度。
其次，如圖40所示，自上述密封體形成步驟中使用之成形模具40，將形成有密封體4之配線基板20取出(基板取出步驟)。本步驟係將圖39所示之上模具41與下模具42拉開，從而將配線基板20取出。
繼而，將自成形模具40中取出之配線基板20搬送至未圖示之加熱爐(烘烤爐)，再次將配線基板20進行熱處理(烘烤步驟、正式硬化步驟)。成形模具40內經加熱之樹脂4p成為樹脂中之硬化成分之一半以上(例如約70%左右)進行硬化之稱為所謂預硬化之狀態。於該預硬化之狀態下，並非樹脂4p中之所有硬化成分進行硬化，而是一半以上之硬化成分進行硬化，且於該時間點將半導體晶片3密封。然而，考慮到密封體4之強度之穩定性等觀點，較佳為使所有之硬化成分完全地硬化，因此，在烘烤步驟中，實施將經預硬化之密封體4再次進行加熱之所謂正式硬化。可藉由以此方式，將使樹脂4p硬化之步驟分為2次，而對搬送至成形模具40之下一個之配線基板20，儘早地實施密封步驟。因此，可使製造效率提昇。
又，如圖40所示，於密封體4之周緣部(框部20b上)，殘留有澆口部樹脂4g及排氣孔部樹脂4v。若視需要，將澆口部樹脂4g及排氣孔部樹脂4v去除，則如圖36所示，形成將分別搭載於複數個器件區域20a之複數個半導體晶片3(參照圖35)整批地密封之密封體(樹脂體)4。但，澆口部樹脂4g及排氣孔部樹脂4v係形成於隨後描述之單片化步驟中進行去除之框部20b，故可將去除該等之步驟省略。
<植球步驟>
其次，圖11所示之植球步驟係如圖41所示，在形成於配線基板20之下表面2b之複數個焊墊2g，接合成為外部端子之複數個焊球5。圖41係表示在圖35所示之配線基板之複數個焊墊上接合有焊球之狀態之放大剖面圖。
本步驟係如圖41所示，使配線基板20之上下反轉後，於配線基板20之下表面2b露出之複數個焊墊2g之各者上配置焊球5後，藉由進行加熱而將複數個焊球5與焊墊2g接合。藉由本步驟，而將複數個焊球5經由配線基板20，電性連接於複數個半導體晶片3(邏輯晶片LC及記憶體晶片MC1、MC2、MC3、MC4)。但，本實施形態中說明之技術並非僅限於適用於接合陣列狀焊球5而成之所謂BGA(Ball Grid Array(球狀柵格陣列))型之半導體裝置。例如，作為對於本實施形態之變化例，可適用於未形成焊球5且使焊墊2g露出之狀態、或在焊墊2g上比焊球5薄地塗佈有焊料膏之狀態下出貨之所謂LGA(Land Grid Array(平台柵格陣列))型之半導體裝置。於LGA型之半導體裝置之情形時，可將植球步驟省略。
<單片化步驟>
其次，圖11所示之單片化步驟係如圖42所示，將配線基板20分割為每一器件區域20a。圖42係表示使圖41所示之多數個配線基板單片化之狀態之剖面圖。本步驟係如圖31所示，沿著切晶線(切晶區域)20c，將配線基板20及密封體4切斷，獲得經單片化之複數個半導體裝置1(參照圖4)。切斷方法並無特別限定，圖42所示之例中表示使用切晶刀片(旋轉刀)45，將接著固定於膠帶材(切晶膠帶)46之配線基板20及密封體4，自配線基板20之下表面2b側切削加工進行切斷之實施態樣。但，本實施形態中說明之技術並非限定地適用於使用具備複數個器件區域20a之多數個基板即配線基板20之情形。例如，可適用於在相當於1個半導體裝置之配線基板2(參照圖4)之上積層有複數個 半導體晶片3之半導體裝置。於該情形時，可將單片化步驟省略。
藉由以上之各步驟，而獲得使用圖1~圖10所說明之半導體裝置1。其後，進行外觀檢查或電氣試驗等必要之檢查及試驗後出貨，或者安裝於未圖示之安裝基板。
(變化例)
以上，基於實施形態，對由本發明者開發之發明進行了具體說明，但勿庸置疑，本發明並非限定於上述實施形態，在未脫離其精神之範圍內可進行各種變更。
<變化例1>
例如，上述實施形態係以根據半導體裝置之可靠性之觀點之課題，對第2晶片搭載步驟中，因平面尺寸較大之積層體MCS以突起電極7為基點傾斜，而存在突起電極7與背面電極3bp之位置偏移之虞進行了說明。又，對密封步驟中，存在於積層體MCS與配線基板20之間隙形成氣泡VD之虞進行了說明。又，對密封步驟中，若在積層體MCS與配線基板20之間隙，將粒徑較大(例如大於積層體MCS與配線基板20之間隔距離)之填料粒子FL夾住，則存在積層體MCS損傷之虞進行了說明。上述課題係於與半導體裝置之可靠性相關之類的方面共通，且於在相較邏輯晶片LC用之晶片搭載區域2p1寬廣之範圍配置接著材NCL之類的方面，對策之主要部分共通，但用以解決各課題之最小限度之構成嚴格意義上不同。圖43及圖44係表示對於上述實施形態中說明之半導體裝置1之變化例之概要之主要部分剖面圖。
首先，作為消除因第2晶片搭載步驟中說明之積層體MCS以突起電極7為基點傾斜，而存在突起電極7與背面電極3bp之位置偏移之虞之結構，考量圖43所示之半導體裝置50。半導體裝置50係於在積層體MCS與配線基板20之間存在間隙之方面，不同於圖4所示之半導體裝置1。又，半導體裝置50係於未形成有圖4所示之密封體4之方面，與 圖4所示之半導體裝置1不同。換言之，半導體裝置50之製造方法中，將上述實施形態中說明之密封步驟省略。
即，於半導體裝置50之製造方法之情形時，因將密封步驟省略，故不產生密封步驟中說明之課題。因此，至少實施抑制積層體MCS以突起電極7(參照圖33)為基點傾斜之程度之對策即可。因此，當積層體MCS(半導體晶片3)以突起電極7為基點傾斜時，以積層體MCS與接著材NCL1最初接觸之程度之平面尺寸及厚度，形成接著材NCL1即可。詳細而言，將接著材NCL1之周緣部配置於相較晶片搭載區域2p1之周緣部接近於晶片搭載區域2p2之周緣部之位置。又，較佳為，使接著材NCL1之厚度為如圖43所示之邏輯晶片LC之側面3c中之邏輯晶片LC之正面3a側之一半以上被接著材NCL1覆蓋之程度之厚度。換言之，較佳為，以於剖視下，接著材NCL1之上表面NCL1a相較邏輯晶片LC之側面3c之中央部(一半之高度)位於邏輯晶片LC之背面3b側之方式，形成接著材NCL1。或者，較佳為，以接著材NCL1之上表面NCL1a位於與邏輯晶片LC之背面3b相同之高度之方式，形成接著材NCL1。但，就更確實地抑制積層體MCS以突起電極7(參照圖33)為基點傾斜之程度之觀點而言，較佳為，將接著材NCL1配置為覆蓋晶片搭載區域2p2之整體。又，於上述第2晶片搭載步驟中，就更確實地抑制半導體晶片2傾斜之觀點而言，較佳為，如使用圖33所說明，以覆蓋晶片搭載區域2p2之大部分之方式配置接著材NCL1。
另一方面，接著材NCL2之配置範圍相較接著材NCL1之配置範圍，對積層體MCS之傾斜之影響較小，因此，如圖43所示，例如可配置於邏輯晶片LC之背面3b。但，就使接著材NCL2之接著強度提昇之觀點而言，較佳為，如上述實施形態中說明之圖32所示，亦於邏輯晶片LC之背面3b及接著材NCL1之露出面(自邏輯晶片LC露出之部分之露出正面)配置接著材NCL2。
<變化例2>
其次，作為消除密封步驟中說明之於積層體MCS與配線基板20之間隙形成有氣泡VD之虞、或者於積層體MCS與配線基板20之間隙將粒徑較大之填料粒子FL夾住之虞之結構，而考量圖44所示之半導體裝置51。半導體裝置51係於接著材NCL1之配置範圍成為與晶片搭載區域2p1大致相同之平面尺寸之方面，不同於圖4所示之半導體裝置1。
於不考慮上述實施形態中說明之第2晶片搭載步驟中之積層體MCS之傾斜之情形時，於密封步驟之前，將積層體MCS與配線基板20之間隙填充即可，因此，可使接著材NCL1之平面尺寸變小。例如圖44所示之例係將接著材NCL1之周緣部配置於相較晶片搭載區域2p2之周緣部接近於晶片搭載區域2p1之周緣部之位置。又，邏輯晶片LC之側面3c之背面3b側之一半以上之區域係自接著材NCL1露出。即便如半導體裝置51般之構成，若於密封步驟之前，利用接著材NCL2將積層體MCS與配線基板20之間隙填塞，則亦可消除在積層體MCS與配線基板20之間隙形成氣泡VD之虞、或者在積層體MCS與配線基板20之間隙夾住粒徑較大之填料粒子FL之虞。
但，如上述實施形態中所述，於接著材NCL2中使用絕緣性膏(NCP)之情形時，尤其接著材NCL2將跟蹤接著材NCL1擴散。因此，就控制接著材NCL2之配置範圍，將積層體MCS與配線基板20之間隙確實地填塞的觀點而言，較佳為，如圖4所示，將接著材NCL1之周緣部配置於相較晶片搭載區域2p1之周緣部接近於晶片搭載區域2p2之周緣部的位置。
又，作為藉由接著材膏NCL1而將夾住粒徑較大之填料粒子FL之虞消除之結構，較佳為，如圖45及圖46所示之半導體裝置52般，將接著材膏NCL1配置為覆蓋晶片搭載區域2p2之大部分。圖45係表示對於 圖44所示之半導體裝置之變化例之概要之主要部分剖面圖。又，圖46係圖45之A部之放大剖面圖。
圖45及圖46所示之半導體裝置52係晶片搭載區域2p2之大部分被接著材NCL1覆蓋。詳細而言，如圖46所示，晶片搭載區域2p2中之未被接著材NCL1覆蓋之部分之寬度(圖46所示之間隔G3)小於複數個填料粒子FL中之體積最大之填料粒子FL(例如，直徑大於配線基板20與積層體MCS之間隔G2之填料粒子)之半徑R1。換言之，積層體MCS之側面3c與接著材NCL1之周緣部NCL1c之間隔G3(俯視下之間隔距離或間隙)小於複數個填料粒子FL中之體積最大之填料粒子FL之半徑R1。
於半導體裝置52之情形時，在上述第2晶片搭載步驟中即便接著材NCL1之周緣部NCL1c未被接著材NCL2覆蓋，亦可藉由接著材NCL1而防止或抑制填料粒子FL夾住之方面較佳。又，於在上述第2晶片搭載步驟中，接著材NCL1之周緣部NCL1c被接著材NCL2覆蓋之情形時，可將積層體MCS與配線基板20之間隙確實地填塞。
又，於半導體裝置52之情形時，由於晶片搭載區域2p2之一部分未被接著材NCL1覆蓋，故而在容易控制接著材NCL2之擴散之方面較佳。
<變化例3>
又，於上述第2晶片搭載步驟中，就抑制因積層體MCS傾斜，而使接著材NCL1之周緣部與積層體MCS之正面3a接觸，導致對形成於積層體MCS之記憶體電路施加應力之觀點而言，較佳為如圖47及圖48所示之半導體裝置53之類的構成。圖47係表示對於圖4所示之半導體裝置之其他變化例之概要之主要部分剖面圖。又，圖48係圖47之A部之放大剖面圖。
圖47及圖48所示之半導體裝置53係於設置在積層體MCS之記憶體區域MR之周緣部(最接近於側面3c之邊)MRc與積層體MCS之側面3c 之間，配置有接著材NCL1之側面NCL1c。
積層體MCS係例如如圖4所示具有複數個記憶體晶片MC1、MC2、MC3、MC4，且於各記憶體晶片MC1、MC2、MC3、MC4之各者，形成有記憶體區域MR。再者，記憶體區域MR之平面佈局係如使用圖6所說明，故將重複之說明省略。
於圖47及圖48所示之半導體裝置53之情形時，於俯視下，將設置於積層體MCS之記憶體區域MR之周緣部MRc相較接著材NCL1之周緣部NCL1c配置於內側。因此，於上述第2晶片搭載步驟中，即便積層體MCS傾斜，記憶體區域MR與接著材NCL1亦難以接觸。因此，於防止或抑制在第2晶片搭載步驟中，對記憶體區域MR施加應力之方面較佳。
<變化例4>
又，半導體裝置50、51、52、及半導體裝置53成為未接合圖4所示之焊球5，且複數個焊墊2g作為外部端子而露出的所謂LGA型之半導體裝置。於該情形時，可將上述實施形態中說明之焊球接合步驟省略。
<變化例5>
又，半導體裝置50、51、52、及半導體裝置53可於例如相當於1個半導體裝置之配線基板2之上，積層複數個半導體晶片3而製造。於該情形時，可將上述實施形態中說明之單片化步驟省略。
<變化例6>
又，例如，上述實施形態係對於將積層有複數個記憶體晶片MC1、MC2、MC3、MC4之積層體MCS搭載於邏輯晶片LC之背面3b上之實施態樣進行了說明，但積層於上段之半導體晶片3之數並未限定，亦可為例如1片。又，即便於在邏輯晶片LC之背面3b上積層複數個半導體晶片3之情形時，亦可藉由重複實施圖11所示之第2接著材配 置步驟~第2晶片搭載步驟為止之順序，而例如圖59所示之半導體裝置55般，經由接著材NCL1、NCL2、NCL3、NCL4、NCL5依次地積層複數個半導體晶片3。於半導體裝置55之情形時，因將各半導體晶片3依次地積層，故組裝步驟所需之時間變長，但可不使用圖4所示之密封體6地以倒裝晶片連接方式將複數個半導體晶片3積層。
<變化例7>
又，例如，上述實施形態及變化例係對在與晶片搭載區域2p2相同之範圍、或相較晶片搭載區域2p2狹窄之範圍內配置接著材NCL1之實施態樣進行了說明。然而，作為變化例，亦可在相較晶片搭載區域2p2寬闊之範圍內配置接著材NCL1。換言之，可使接著材NCL1之平面尺寸大於積層體MCS之平面尺寸。於該情形時，由於可在第2晶片搭載步驟中，使接著材NCL2接著於積層體MCS之側面3c，故容易形成圓角。其結果，可使積層體MCS與接著材NCL2之接著強度提昇。
<變化例8>
進而，在不脫離上述實施形態中所說明之技術思想之精神之範圍內，可組合地適用變化例彼此。
此外，將實施形態中所揭示之內容之一部分揭示如下。
(1)一種半導體裝置，其包括：配線基板，其具有第1面、形成於上述第1面之複數個接合引線、與上述第1面為相反側之第2面、及形成於上述第2面且與上述複數個接合引線分別電性連接之複數個焊墊；第1半導體晶片，其具有第1正面、形成於上述第1正面之複數個第1正面電極、與上述第1正面為相反側之第1背面、形成於第1背面之複數個第1背面電極、及以自上述第1正面及上述第1背面中之一者朝向另一者貫通之方式分別形成且將上述複數個第1正面電極與上述複數個第1背面電極分別電性連接之複數個貫通電極，且以上述第1正面 與上述配線基板之上述第1面對向之方式，經由第1接著材搭載於上述配線基板之上述第1面；及第2半導體晶片，其具有第2正面、形成於上述第2正面之複數個第2正面電極、與上述複數個第2正面電極分別電性連接之複數個突起電極、及與上述第2正面為相反側之第2背面，且以上述第2半導體晶片之上述第2正面與上述第1半導體晶片之上述第1背面對向之方式，經由第2接著材搭載於上述第1半導體晶片上；上述複數個第1正面電極與上述複數個接合引線係電性連接，上述複數個第2正面電極與上述複數個第1背面電極係經由上述複數個突起電極而電性連接，上述第2半導體晶片之平面尺寸大於上述第1半導體晶片之平面尺寸，上述第2半導體晶片係包含上述第1晶片搭載部，且，搭載於平面尺寸大於上述第1晶片搭載部之第2晶片搭載部上，且上述第1接著材之周緣部係配置於相較上述第1晶片搭載部之周緣部接近於上述第2晶片搭載部之周緣部之位置。
2a‧‧‧上表面(面、主面、晶片搭載面)
2d‧‧‧配線
2f‧‧‧接合引線
2p2‧‧‧晶片搭載區域
3‧‧‧半導體晶片
3a‧‧‧正面(主面、上表面)
3b‧‧‧背面(主面、下表面)
3c‧‧‧側面
3ap‧‧‧正面電極(電極、焊墊)
3bp‧‧‧背面電極(電極、焊墊)
7‧‧‧突起電極(導電性構件、凸塊電極)
8a‧‧‧焊料層
20‧‧‧配線基板
LC‧‧‧邏輯晶片
MCS‧‧‧積層體
NCL、NCL1、NCL2‧‧‧接著材(絕緣性接著材)
NCL1a‧‧‧接著材NCL1之上表面

Claims (20)

  1. 一種半導體裝置之製造方法，其包含以下之步驟：(a)準備配線基板，該配線基板具有第1面、形成於上述第1面之複數個接合引線、與上述第1面為相反側之第2面、及形成於上述第2面且與上述複數個接合引線分別電性連接之複數個焊墊；(b)於上述配線基板之上述第1面上配置第1接著材；(c)於上述(b)步驟後，將具有第1正面、形成於上述第1正面之複數個第1正面電極、與上述第1正面為相反側之第1背面、形成於第1背面之複數個第1背面電極、及以自上述第1正面及上述第1背面中之一者朝向另一者貫通之方式分別形成且將上述複數個第1正面電極與上述複數個第1背面電極分別電性連接之複數個貫通電極的第1半導體晶片，以上述第1半導體晶片之上述第1正面與上述配線基板之上述第1面對向之方式，經由上述第1接著材而搭載於上述配線基板之上述第1面，將上述複數個接合引線與上述複數個第1正面電極分別電性連接；(d)於上述(c)步驟後，於上述第1半導體晶片之上述第1背面上及自上述第1半導體晶片露出之上述第1接著材之正面上，配置第2接著材；(e)於上述(d)步驟後，將具有第2正面、形成於上述第2正面之複數個第2正面電極、及與上述第2正面為相反側之第2背面的第2半導體晶片，以上述第2半導體晶片之上述第2正面與上述第1半導體晶片之上述第1背面對向之方式，經由上述第2接著材而搭載於上述第1半導體晶片上，將上述複數個第1背面電極與上述複數個第2正面電極分別電性連接；及 (f)於上述(e)步驟後，以樹脂密封上述配線基板之上述第1面、上述第1半導體晶片及上述第2半導體晶片；其中於俯視時，上述第2半導體晶片之尺寸大於上述第1半導體晶片之尺寸；於上述俯視時，上述配線基板之上述第1面具有與上述第1半導體晶片重疊之第1晶片搭載區域、及與上述第2半導體晶片重疊之第2晶片搭載區域，上述第2晶片搭載區域包含上述第1晶片搭載區域；於上述(b)步驟，上述第1接著材係配置為使上述第1接著材之周緣部係(i)位於上述第1晶片搭載區域之周緣部與上述第2晶片搭載區域之周緣部之間，(ii)相較於上述第1晶片搭載區域之上述周緣部更接近於上述第2晶片搭載區域之上述周緣部；且於上述(e)步驟後且上述(f)步驟之前，將上述第2半導體晶片中之未與上述第1半導體晶片重疊之部分與上述配線基板之上述第1面之間利用上述第1及第2接著材填塞。
  2. 如請求項1之半導體裝置之製造方法，其中上述(f)步驟中，藉由將上述配線基板配置於成形模具內，並對上述成形模具內供給樹脂，而將上述配線基板之上述第1面、上述第1半導體晶片及上述第2半導體晶片密封，利用上述成形模具將上述樹脂成形。
  3. 如請求項2之半導體裝置之製造方法，其中上述(c)步驟中搭載之上述第1半導體晶片之厚度薄於上述(e)步驟中搭載之上述第2半導體晶片之厚度。
  4. 如請求項1之半導體裝置之製造方法，其中 於上述(f)步驟中，於上述配線基板之上述第1面、上述第1半導體晶片及上述第2半導體晶片密封之上述樹脂中包含複數個填料粒子。
  5. 如請求項4之半導體裝置之製造方法，其中於上述複數個填料粒子中，包含粒徑大於上述第2半導體晶片與上述配線基板之上述第1面之間隔距離之填料粒子。
  6. 如請求項1之半導體裝置之製造方法，其中上述(e)步驟中，將複數個上述第2半導體晶片積層於上述第1半導體晶片上，且複數個上述第2半導體晶片間藉由與上述密封體不同之密封體予以密封。
  7. 如請求項6之半導體裝置之製造方法，其中上述(f)步驟中，將上述配線基板之上述第1面、及上述第1半導體晶片密封之上述樹脂係黏度高於將複數個上述第2半導體晶片之間密封之上述密封體。
  8. 如請求項1之半導體裝置之製造方法，其中配置於上述配線基板之上述第1面之第1晶片搭載區域之上述第1接著材係膜狀之接著材。
  9. 如請求項1之半導體裝置之製造方法，其中上述(d)步驟係藉由將膏狀之上述第2接著材朝向上述第1半導體晶片之上述第1背面上及自上述第1半導體晶片露出之上述第1接著材之正面上進行塗佈，而配置上述第2接著材。
  10. 如請求項1之半導體裝置之製造方法，其中於上述(c)步驟中，上述第1半導體晶片之側面中、上述第1半導體晶片之上述正面側之一半以上由上述第1接著材所覆蓋。
  11. 如請求項1之半導體裝置之製造方法，其中 上述第1接著材之覆蓋範圍(footprint)係包含上述第1晶片搭載區域之整體覆蓋範圍。
  12. 如請求項1之半導體裝置之製造方法，其中上述第1半導體晶片之上述第1正面經由上述第1接著材與上述配線基板之上述第1面對向；且上述第1半導體晶片之側面之至少一部份係被相同之上述第1接著材所覆蓋。
  13. 如請求項12之半導體裝置之製造方法，其中上述第1接著材之覆蓋範圍(footprint)係包含與上述第1半導體晶片重疊的上述第1晶片搭載區域之整體覆蓋範圍。
  14. 一種半導體裝置之製造方法，其包括以下之步驟：(a)準備配線基板，該配線基板具有第1面、形成於上述第1面之複數個接合引線、與上述第1面為相反側之第2面、及形成於上述第2面且與上述複數個接合引線分別電性連接之複數個焊墊；(b)於上述配線基板之上述第1面上配置第1接著材；(c)上述(b)步驟後，將具有第1正面、形成於上述第1正面之複數個第1正面電極、形成於上述第1正面側且與上述複數個第1正面電極之各者電性連接之複數個第1電路、與上述第1正面為相反側之第1背面、形成於第1背面之複數個第1背面電極、及以自上述第1正面及上述第1背面中之一者朝向另一者貫通之方式分別形成且將上述複數個第1正面電極與上述複數個第1背面電極分別電性連接之複數個貫通電極的第1半導體晶片，以上述第1半導體晶片之上述第1正面與上述配線基板之上述第1面對向之方式，經由上述第1接著材而搭載於上述配線基板之上述第1面，將上述複數個接合引線與上述複數個第1正面電極分別電性 連接；(d)於上述(c)步驟後，在上述第1半導體晶片之上述第1背面上及自上述第1半導體晶片露出之上述第1接著材之正面上，配置第2接著材；(e)於上述(d)步驟後，將具有第2正面、形成於上述第2正面之複數個第2正面電極、形成於上述第2正面側且與上述複數個第2正面電極之各者電性連接之複數個第2電路、及與上述第2正面為相反側之第2背面的第2半導體晶片，以上述第2半導體晶片之上述第2正面與上述第1半導體晶片之上述第1背面對向之方式，經由上述第2接著材而搭載於上述第1半導體晶片上，將上述複數個第1背面電極與上述複數個第2正面電極分別電性連接；及(f)於上述(e)步驟後，以樹脂密封上述配線基板之上述第1面、上述第1半導體晶片及上述第2半導體晶片；其中於上述複數個第2電路中包含記憶電路，該記憶電路係記憶在與上述第1半導體晶片之間經由設置於上述第1半導體晶片與上述第2晶片之間之複數個第1突起電極進行通訊之資料；於上述複數個第1電路中包含控制電路，該控制電路係經由設置於上述第1半導體晶片與上述第2晶片之間之複數個第2突起電極而控制上述第2半導體晶片之上述記憶電路之動作；於俯視時，上述第2半導體晶片之尺寸大於上述第1半導體晶片之尺寸；於上述俯視時，上述配線基板之上述第1面具有與上述第1半導體晶片重疊之第1晶片搭載區域、及與上述第2半導體晶片重疊之第2晶片搭載區域，上述第2晶片搭載區域包含上述第1晶片搭載區域；於上述(b)步驟，上述第1接著材係配置為使上述第1接著材之 周緣部係(i)位於上述第1晶片搭載區域之周緣部與上述第2晶片搭載區域之周緣部之間，(ii)相較於上述第1晶片搭載區域之上述周緣部更靠近上述第2晶片搭載區域之上述周緣部；於上述(e)步驟之後且上述(f)步驟之前，上述第2半導體晶片中之未與上述第1半導體晶片重疊之部分與上述配線基板之上述第1面之間由上述第1及第2接著材填塞。
  15. 如請求項14之半導體裝置之製造方法，其中上述(c)步驟中，上述第1半導體晶片之側面中、上述第1半導體晶片之上述正面側之一半以上由上述第1接著材所覆蓋。
  16. 如請求項14之半導體裝置之製造方法，其中於上述(c)步驟之後且上述(d)步驟之前，包含使上述第1接著材硬化之步驟。
  17. 如請求項14之半導體裝置之製造方法，其中上述(b)步驟係將上述第1接著材以覆蓋上述第2晶片搭載區域整體之方式配置。
  18. 如請求項14之半導體裝置之製造方法，其中上述第1接著材之覆蓋範圍係包含上述第1晶片搭載區域之整體覆蓋範圍。
  19. 如請求項14之半導體裝置之製造方法，其中上述第1半導體晶片之上述第1正面經由上述第1接著材與上述配線基板之上述第1面對向；且上述第1半導體晶片之側面之至少一部份係被相同之上述第1接著材所覆蓋。
  20. 一種半導體裝置之製造方法，其包含以下之步驟： (a)準備配線基板，該配線基板具有第1面、形成於上述第1面之複數個接合引線、與上述第1面為相反側之第2面、及形成於上述第2面且與上述複數個接合引線分別電性連接之複數個焊墊；(b)於上述配線基板之上述第1面上配置第1接著材；(c)於上述(b)步驟後，將具有第1正面、形成於上述第1正面之複數個第1正面電極、與上述第1正面為相反側之第1背面、形成於第1背面之複數個第1背面電極、及以自上述第1正面及上述第1背面中之一者朝向另一者貫通之方式分別形成且將上述複數個第1正面電極與上述複數個第1背面電極分別電性連接之複數個貫通電極的第1半導體晶片，以上述第1半導體晶片之上述第1正面與上述配線基板之上述第1面對向之方式，經由上述第1接著材而搭載於上述配線基板之上述第1面，將上述複數個接合引線與上述複數個第1正面電極分別電性連接；(d)於上述(c)步驟後，於上述第1半導體晶片之上述第1背面上及自上述第1半導體晶片露出之上述第1接著材之正面上，配置第2接著材；(e)於上述(d)步驟後，將具有第2正面、形成於上述第2正面之複數個第2正面電極、及與上述第2正面為相反側之第2背面的第2半導體晶片，以上述第2半導體晶片之上述第2正面與上述第1半導體晶片之上述第1背面對向之方式，經由上述第2接著材而搭載於上述第1半導體晶片上，將上述複數個第1背面電極與上述複數個第2正面電極分別電性連接；及(f)於上述(e)步驟後，以樹脂密封上述配線基板之上述第1面、上述第1半導體晶片及上述第2半導體晶片；其中上述第1半導體晶片之上述第1正面經由上述第1接著材與上述 配線基板之上述第1面對向；上述第1半導體晶片之側面之至少一部份係被相同之上述第1接著材所覆蓋；上述第2半導體晶片之平面尺寸大於上述第1半導體晶片之平面尺寸；且於上述(e)步驟後且上述(f)步驟之前，將上述第2半導體晶片中之未與上述第1半導體晶片重疊之部分與上述配線基板之上述第1面之間利用上述第1及第2接著材填塞。
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