TWI567803B - Compliant bipolar micro device transfer head with silicon electrodes - Google Patents

Description

Compatible bipolar micro device transfer head with tantalum electrode

This invention relates to microdevices. More particularly, embodiments of the present invention relate to a compatible bipolar microdevice transfer head and a method of transferring one or more micro devices to a receiving substrate.

Integration and packaging issues are microdevices such as radio frequency (RF) microelectromechanical systems (MEMS) microswitches, light-emitting diode (LED) display systems, and MEMS or quartz based oscillators. One of the main obstacles to commercialization.

Conventional techniques for device transfer include transfer by wafer bonding from transfer wafer to receiving wafer. One such implementation is "direct printing," which includes a bonding step of a device array from a transfer wafer to a receiving wafer, followed by removal of the transfer wafer. Another such embodiment is a "transfer print" that includes two joining/separating steps. In transfer printing, the transfer wafer can pick up an array of devices from the donor wafer and then bond the device array to the receiving wafer, followed by removal of the transfer wafer.

A number of printing process variations have been developed in which the device can be selectively joined and separated during the transfer process. Direct printing and transfer printing in the traditional In both the technology and variations of direct printing and transfer printing techniques, the transfer wafer is separated from the device after bonding the device to the receiving wafer. In addition, the entire transfer wafer with the array of devices is involved in the transfer process.

A method of transferring a head and head array of compatible bipolar microdevices and transferring one or more microdevices to a receiving substrate is disclosed. For example, the receiving substrate can be, but is not limited to, a display substrate, an illumination substrate, a substrate having a functional device such as a transistor or an integrated circuit (IC), or a substrate having a metal redistribution line.

In an embodiment, the compatible bipolar microdevice transfer head array includes a base substrate and a patterned germanium layer over the base substrate. For example, the base substrate can be a (100) block-shaped germanium substrate. The patterned germanium layer includes a first germanium interconnect structure, a first germanium electrode array electrically connected to the germanium interconnect structure, a second germanium interconnect structure, and a second germanium electrically connected to the second germanium interconnect structure Electrode array. Each of the first tantalum electrode array and the second tantalum electrode array includes an electrode lead and a mesa structure that protrudes over the first tantalum interconnect structure and the second tantalum interconnect structure. The first tantalum electrode array and the second tantalum electrode array are aligned as an array of bipolar tantalum electrode pairs and are electrically insulated from each other. The first germanium interconnect structure and the second germanium interconnect structure may be parallel to each other. Each of the electrodes can also be deflected into the cavity between the base substrate and the ruthenium electrode. For example, one or more cavities can be formed in the base substrate. In an embodiment, the first tantalum electrode array and the second tantalum electrode array can be deflected into the same cavity in the base substrate. In this embodiment, the array of bipolar ruthenium electrode pairs can be deflected into the same cavity in the base substrate. The cavity may also surround the ends of one or both of the first and second electrodes. In an embodiment, bipolar Each bipolar 矽 electrode pair in the array of pairs of electrodes can be deflected into a separate cavity. A dielectric layer such as cerium oxide, cerium oxide, aluminum oxide or cerium oxide covers the top surface of each mesa structure. A buried oxide layer may be formed between the patterned germanium layer and the base substrate.

In an embodiment, the array of bipolar germanium electrode pairs forms an array of support beams between the tantalum interconnect structure and the second tantalum interconnect structure. For example, an oxide tab array can be formed between the first tantalum electrode array and the second tantalum electrode array. The patterned germanium layer can be on the buried oxide layer and in direct contact with the buried oxide layer, wherein the oxide joint is on the buried oxide layer and is in direct contact with the buried oxide layer. The oxide junction may be parallel or perpendicular to the first tantalum interconnect structure array and the second tantalum interconnect structure array, and the oxide joint is between the first tantalum electrode array and the second tantalum electrode array mesa structure. The support beam can also include, for example, a bend in the tantalum electrode lead of the tantalum electrode. The array of oxide tabs can separate the first tantalum electrode array and the second tantalum electrode array along a longitudinal or lateral width of the array of support beams.

In an embodiment, the array of bipolar germanium electrode pairs forms an array of cantilever beams spanning between the tantalum interconnect structure and the second tantalum interconnect structure. In an embodiment, each of the bipolar iridium electrode pairs is a separate cantilever beam, and the open space is between the mesa structures of the first ruthenium electrode array and the second ruthenium electrode array. The cantilever beam can include a bend. In an embodiment, the mesa structures of the first tantalum electrode array and the second tantalum electrode array are not separated by an open space. For example, an array of oxide junctions can be formed between the first tantalum electrode and the second tantalum electrode array of the cantilever beam array. The patterned germanium layer may be on the buried oxide layer and in direct contact with the buried oxide layer, wherein the oxide joint is on the buried oxide layer and Direct contact with the buried oxide layer. In an embodiment, the oxide joint separates the first tantalum electrode array and the second tantalum electrode array along a longitudinal length of the cantilever beam array. In an embodiment, the oxide junction is parallel to the first tantalum interconnect structure and the second tantalum interconnect structure and between the mesa structures of the first tantalum electrode array and the second tantalum electrode array.

In an embodiment, the buried ruthenium dioxide layer is between the patterned ruthenium layer and the base substrate. The first via extends through the base substrate and the buried erbium oxide layer from the rear side of the base substrate to the patterned germanium layer and is electrically connected to the first germanium interconnect structure and the first germanium electrode array. The second via extends through the base substrate and the buried ceria layer from the rear side of the base substrate to the patterned germanium layer and is electrically connected to the second germanium interconnect structure and the second germanium electrode array. The via may extend through the patterned germanium layer or terminate in a bottom surface of the patterned germanium layer.

A dielectric layer covering the top surface of each of the array and the second array of the second array may be formed of a material such as hafnium oxide, hafnium oxide, aluminum oxide, and hafnium oxide. In some embodiments, the first dielectric layer is laterally located between the tantalum electrode array in the bipolar electrode configuration and the mesa structure of the second tantalum electrode array, and the first dielectric layer is located in the overlay array and the second array. Below the dielectric layer of the top surface of each mesa structure. The dielectric layer can have a higher dielectric constant or dielectric breakdown strength than the first dielectric layer.

In an embodiment, a method of forming a compatible bipolar micro device transfer head array includes the steps of etching a top germanium layer of a stack of insulators on an insulator to form a first germanium electrode array electrically connected to the first germanium interconnect structure, and a second array of germanium electrodes aligned with the first tantalum electrode array and electrically connected to the second tantalum interconnect structure, thereby forming an array of bipolar tantalum electrode pairs, wherein each of the first tantalum electrode array and the second tantalum electrode array The ruthenium electrode includes an electrode lead and a mesa structure that protrudes over the first 矽 interconnect structure and the second 矽 interconnect structure. a dielectric layer is then formed over the first tantalum electrode array and the second tantalum electrode array, and one or more cavities are etched into the base substrate just below the first tantalum electrode array and the second tantalum electrode array, such that the first Each of the tantalum electrode array and the second tantalum electrode array can be deflected into one or more cavities. For example, etching of one or more cavities can be accomplished using a fluorinated plasma of SF ₆ or XeF ₂ . In an embodiment, the separate chambers are etched just below each pair of bipolar germanium electrodes in the base substrate. In an embodiment, a single cavity is etched just below the array of bipolar germanium electrodes in the base substrate. In an embodiment, a single cavity is etched in the base substrate such that the single cavity surrounds one or both of the first germanium interconnect structure and the second germanium interconnect structure.

Etching the top layer of germanium exposes the buried oxide layer. The formation of the dielectric layer can be accomplished using a variety of techniques. In some embodiments, the dielectric layer comprises thermal oxidation of a tantalum electrode array. In some embodiments, a patterned layer is formed over the buried oxide layer and over the dielectric layer after forming the dielectric layer, and the buried oxide layer is etched using the patterned layer to expose a portion of the base substrate . The dielectric layer can be used as an etch mask when one or more cavities are etched just below the first ruthenium electrode array and the second ruthenium electrode array in the base substrate.

In an embodiment, the joint trench array is etched between the mesa structures of the first tantalum electrode array and the second tantalum electrode array, and the top turn layer of the tantalum stack on the insulator is etched to form the first tantalum electrode array and the second tantalum electrode Array. The dielectric layer may also be formed inside the joint trench array and directly contact the buried oxide layer while forming over the first germanium electrode array and the second germanium electrode array. Dielectric layer. For example, the dielectric layer can be formed by thermal oxidation of the first tantalum electrode array and the second tantalum electrode array. The dielectric layer can also completely fill the joint trench array using a dielectric layer to form an oxide joint array between the first tantalum electrode array and the second tantalum electrode array.

The first back side via opening may be etched through the base substrate just below the first germanium interconnect structure, and the second back side via opening may be etched through the base substrate just below the second germanium interconnect structure, and A passivation layer may be formed inside the first back side via opening and the second back side via opening. In an embodiment, the passivation layer is formed in the first back side via opening and the second back side via opening by thermally oxidizing the base substrate while thermally oxidizing the array of the first tantalum electrode array and the second tantalum electrode array to form Dielectric layer. The patterned conductive layer can be formed in the first via opening and the second via opening to be electrically contacted with the first germanium interconnect structure and the second germanium interconnect structure, for example, by shadow mask deposition.

In an embodiment, the dielectric layer is etched to expose a portion of the first germanium interconnect structure and the second germanium interconnect structure while etching through the buried oxide layer to expose portions of the base substrate. Subsequently etching the first upper via opening through the first exposed portion of the first germanium interconnect structure and the buried oxide layer, and etching the second upper via opening through the second exposed portion of the second germanium interconnect structure And a buried oxide layer. A patterned conductive layer can then be formed in the first upper via opening and the second upper via opening to electrically contact the first germanium interconnect structure and the second germanium interconnect structure.

In an embodiment, the dielectric layer is etched to expose each of the terrace surface structures while etching through the buried oxide layer to expose portions of the base substrate. A second dielectric layer can then be formed over each of the mesa structures. In the embodiment This can be accomplished by blanket deposition of the second dielectric layer followed by removal of a portion of the second dielectric layer. In some embodiments, blanket deposition can be accomplished by atomic layer deposition. In an embodiment, the dielectric layer may be additionally etched to expose a portion of the first germanium interconnect structure and the second germanium interconnect structure, and then the first upper via opening is etched through the exposed portion of the first germanium interconnect structure and a buried oxide layer, etching the second upper via opening through the exposed portion of the second germanium interconnect structure and the buried oxide layer, and forming inside the first upper via opening and the second upper via opening The patterned conductive layer is in electrical contact with the germanium interconnect structure and the second germanium interconnect structure. The second dielectric layer formed over each of the mesa structures and the conductive layer formed inside the first upper via opening and the second upper via opening may also be used as an etch mask when etching one or more cavities cover.

100‧‧‧矽 substrate compatible bipolar micro device transfer head array

102‧‧‧Compatible transfer head

104‧‧‧矽 Trace interconnect structure

106‧‧‧ Bus Bar Interconnect Structure

110‧‧‧矽 electrode

112‧‧‧ countertop structure

114‧‧‧Electrode lead

115‧‧‧Bend

116‧‧‧ trench

117‧‧‧ joint groove

118‧‧‧ dielectric layer

119‧‧‧Oxide joint

120‧‧‧through hole

120A‧‧‧through opening

120B‧‧‧through opening

121‧‧‧ photoresist

122‧‧‧ patterned conductive layer

123‧‧‧ patterned conductive layer

124‧‧‧buried oxide layer

126‧‧‧Second dielectric layer

130‧‧‧Base substrate

132‧‧‧ Passivation layer

133‧‧‧passivation layer

136‧‧‧ cavity

137‧‧‧groove area

140‧‧‧矽

142‧‧‧ patterned hard mask

144‧‧ Island

160‧‧‧Transfer head components

200‧‧‧ Carrier substrate

202‧‧‧Microdevice

300‧‧‧ receiving substrate

3810‧‧‧ operation

3820‧‧‧ operation

3830‧‧‧ operation

3840‧‧‧ operation

3850‧‧‧ operation

1A is a plan view of a jointless, compatible bipolar microdevice transfer head array having a single side clamping cantilever pair, in accordance with an embodiment of the present invention.

1B is a plan view of a compatible bipolar microdevice transfer head having a pair of single-sided clamping cantilever beams and jointless, in accordance with an embodiment of the present invention.

1C is a cross-sectional side view of the transverse line C-C of the compatible bipolar microdevice transfer head illustrated in FIG. 1B, in accordance with an embodiment of the present invention.

1D is a cross-sectional side view of a longitudinal line D-D of the compatible bipolar microdevice transfer head illustrated in FIG. 1B, in accordance with an embodiment of the present invention.

2A through 2B are combined plan views and combined cross-sectional side views along lines VV, WW, XX, YY, and ZZ of Fig. 1A, including a pair of yttrium electrodes, in accordance with an embodiment of the present invention. Open joint groove Compatible bipolar microdevice transfer head with slot and rear side opening.

3A-3B are combined plan views and combined cross-sectional side views of a compatible bipolar microdevice transfer head including a double-sided clamping support beam, in accordance with an embodiment of the present invention. And an oxide connector connecting the pair of electrodes and connecting the pair of electrodes, and an upper through hole opening and a rear side through opening.

4A through 4B are combined plan views and combined cross-sectional side views of a compatible bipolar microdevice transfer head including a double-sided clamping support beam, in accordance with an embodiment of the present invention. And a deposition dielectric layer, a pair of germanium electrodes 110, and an oxide joint 119 connecting the pair of germanium electrodes 110, and an upper through hole opening and a rear side through hole opening.

5A through 15B illustrate a method of forming a compatible bipolar microdevice transfer head including an open joint groove and a rear side through hole opening between the pair of turns electrodes, in accordance with an embodiment of the present invention.

Figure 16A is a plan view of a compatible bipolar microdevice transfer head array having dual clamping support beams and mesa joints in accordance with an embodiment of the present invention.

Figure 16B is a plan view of a compatible bipolar microdevice transfer head having dual clamping support beams and mesa joints in accordance with an embodiment of the present invention.

Figure 16C is a cross-sectional side view of transverse line C-C of the compatible bipolar microdevice transfer head illustrated in Figure 16B, in accordance with an embodiment of the present invention.

Figure 16D is a cross-sectional side view of the longitudinal line D-D of the compatible bipolar microdevice transfer head illustrated in Figure 16B, in accordance with an embodiment of the present invention. Figure.

17A through 24B illustrate a method of forming a compatible bipolar microdevice transfer head including a double-sided clamping support beam and a pair of tantalum electrodes, in accordance with an embodiment of the present invention. And an oxide joint connecting the pair of electrodes and an upper through hole opening and a rear side through opening.

25A through 30B illustrate a method of forming a compatible bipolar microdevice transfer head including a double-sided clamping support beam and a deposition dielectric layer, in accordance with an embodiment of the present invention, An oxide connector connecting the pair of electrodes and an upper side opening and a rear side opening are connected between the pair of electrodes.

Figure 31 is a plan view and cross-sectional side view of line A-A along a compatible bipolar microdevice transfer head having a cantilever beam and a continuous joint, in accordance with an embodiment of the present invention.

Figure 32 is a plan view and cross-sectional side view of line A-A along a compatible bipolar microdevice transfer head having a cantilever beam and a mesa joint, in accordance with an embodiment of the present invention.

Figure 33 is a plan view and cross-sectional side view of line A-A along a compatible bipolar microdevice transfer head having a double sided clamping beam and a continuous joint, in accordance with an embodiment of the present invention.

Figure 34 is a plan view and cross-section of line AA of a compatible bipolar microdevice transfer head having a double sided clamping beam including a pair of 矽 electrodes (with double bends and mesa joints) in accordance with an embodiment of the present invention. Sectional side view.

Figure 35 is a diagram of compatibility along a double-sided clamping beam having a pair of tantalum electrodes (with a single curved and mesa joint) in accordance with an embodiment of the present invention. A plan view and a cross-sectional side view of line A-A of the bipolar microdevice transfer head.

Figure 36 is a plan view and cross-section of line AA of a compatible bipolar microdevice transfer head having a double-sided clamping beam including a pair of tantalum electrodes (with double bends and mesa joints) in accordance with an embodiment of the present invention. Sectional side view.

Figure 37 is a plan view and cross-section of line AA of a compatible bipolar microdevice transfer head having a double sided clamping beam including a pair of 矽 electrodes (with double bends and mesa joints) in accordance with an embodiment of the present invention. Sectional side view.

Figure 38 is a flow chart illustrating a method of picking up and transferring a microdevice array from a carrier substrate to a receiving substrate in accordance with an embodiment of the present invention.

Figure 39 is a cross-sectional side view of a compatible bipolar microdevice transfer head array over a microdevice array on a carrier substrate in accordance with an embodiment of the present invention.

Figure 40 is a cross-sectional side view of a compatible bipolar microdevice transfer head array of contact microdevice arrays in accordance with an embodiment of the present invention.

Figure 41 is a cross-sectional side view of a compatible bipolar microdevice transfer head array of a pick-up microdevice array in accordance with an embodiment of the present invention.

Figure 42 is a cross-sectional side view of an array of micro devices released onto a receiving substrate in accordance with an embodiment of the present invention.

Embodiments of the present invention describe a compatible bipolar microdevice transfer head and head array, and a method of transferring a microdevice and a microdevice array to a receiving substrate. For example, compatible bipolar micro device transfer heads and head arrays can be used to transfer micro devices such as, but not limited to, diodes, LEDs, transistors, ICs, and MEMS from a carrier substrate to, for example, but not limited to, display substrates, illumination Substrate and function A substrate of a device such as a transistor or an integrated circuit (IC) or a receiving substrate of a substrate having a metal redistribution line.

In various embodiments, the description is made with reference to the drawings. However, some embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as, In other instances, well-known semiconductor processes and fabrication techniques have not been described in detail, so as not to unnecessarily obscure the invention. The specific features, structures, configurations, or characteristics described in connection with the embodiments are included in the description of the embodiments. Thus, appearances of the phrases "in one embodiment", "the embodiment" Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

The terms "above", "to", "between" and "above" as used herein may denote the relative position of one layer relative to the other. A layer "on" or "above" another layer or "on" another layer may be in direct contact with the other layer or may have one or more intervening layers. A layer "between" the layers may be in direct contact with the layers or may have one or more intervening layers.

The term "micro" device or "micro" LED structure as used herein may refer to a descriptive size of certain devices or structures in accordance with embodiments of the present invention. As used herein, the term "micro" device or structure means of the order of 1 μm to 100 μm. However, it will be understood that embodiments of the invention are not necessarily limited thereto, and that certain aspects of the embodiments may be adapted to larger or possibly smaller feet. Insult order.

In one aspect, without being limited to a particular theory, embodiments of the present invention describe microdevice transfer heads and head arrays that operate according to the principle of electrostatic chucks, using oppositely charged attractive pickups Micro device. In accordance with an embodiment of the invention, a pull-in voltage is applied to the microdevice transfer head to create a clamping pressure and pick up the microdevice on the microdevice. For example, the transfer head can include a bipolar electrode configuration.

In one aspect, embodiments of the present invention describe a compatible bipolar microdevice transfer head and transfer method in which a compatible bipolar micro device transfer head array is assigned to an incompatible transfer head array. Improved contact with micro device arrays. The compatible bipolar microdevice transfer head includes an array of bipolar tantalum electrode pairs that are deflectable into one or more cavities between the base substrate and the bipolar tantalum electrode pair. In an application, when the compatible bipolar microdevice transfer head array is lowered onto the micro device array, the deflectable germanium electrode associated with the higher or contaminated microdevice can be compared to the shorter microdevice on the carrier substrate The associated tantalum electrode deflects more. In this manner, the compatible bipolar microdevice transfer head can compensate for variations in the height of the micro device. Compensating for height variations can result in reduced compression forces applied to certain microdevices, thereby protecting the physical integrity of the microdevice and transfer head array. Compensating for height variations can also help each compatible transfer head to make contact with each micro device and to ensure that each desired micro device is picked up. Without the compatible nature of the microdevice transfer head, irregular microdevice heights or particles on the top surface of a single microdevice can prevent the remaining transfer heads from coming into contact with the remaining microdevices in the array. Thus, an air gap can be formed between their transfer heads and the microdevice. Because of this air gap, it is possible that the target voltage will not be fully overcome. The clamping pressure of the air gap, resulting in an incomplete pick-up process.

In another aspect, embodiments of the invention describe a compatible silicon-on-insulator (SOI) substrate comprising a base substrate, a buried oxide layer, and a top germanium layer to form a compatible bipolar The way the micro device transfers the array of heads. In this embodiment, the germanium interconnect structure and the electrode array are formed by the top layer of the SOI substrate. In an embodiment, the bipolar electrostatic transfer head includes a pair of tantalum electrodes, wherein each of the tantalum electrodes includes a mesa structure and electrode leads. A mesa structure for the pair of turns electrodes extends over the respective turns interconnect structure of the pair of turns electrodes to provide local contact points for picking up particular micro devices during the picking operation. In this way, it is not necessary to form a patterned metal electrode. It has been observed that when the metal electrode and electrode lead are patterned using a negative photoresist, for example, it may be difficult to control the exposure of the photoresist at different depths (eg, along both the top and bottom sidewalls of the mesa structure). Peeling of the patterned metal layer has also been observed during photoresist removal, potentially affecting the operability of the transfer head. According to an embodiment of the invention, it is not necessary to form a patterned metal electrode over the mesa structure. In contrast, the projecting profile of the mesa structure is formed by patterning the erbium electrode to include a raised portion corresponding to the mesa structure that extends away from the base substrate and over the 矽 interconnect structure.

The tantalum electrode prepared in accordance with an embodiment of the present invention may comprise an integrally formed mesa structure that is substantially higher than a mesa structure having a patterned metal electrode that is not integrally formed. Photolithography can limit the patterned metal electrode structure to a height of 5 μm to 10 μm, whereas the tantalum electrode mesa structure can reach 20 μm to 30 μm or higher. The mesa structure height for the germanium electrode structure is etched by the aspect ratio and the electrode gap (eg, a pair of bipolar germanium electrodes) The groove between the mesa structures is limited. In an embodiment, the aspect ratio of the mesa structure height to the trench width of the tantalum electrode mesa structure may range from 10:1 to 20:1. For example, the tantalum electrode mesa structure in a bipolar electrode configuration can be 20 μm high, separated by a 2 μm trench gap between mesa structures. Higher electrode configurations can also provide greater clearance for contaminant particles and reduce spurious effects on non-target microdevices. The tantalum electrode having an integrally formed mesa structure may be more robust when compared to metallized mesa structures, for surface contamination and errors in the planar alignment of the microdevice transfer substrate with respect to the microdevice carrier substrate.

In another aspect, embodiments of the present invention describe a manner in which a microdevice transfer head array is formed from a commercially available insulator-on-insulator (SOI) substrate that allows for a processing sequence with minimal processing steps. The processing sequence does not require metal deposition and patterning steps to form the metal electrode, which reduces heat treatment limitations and allows the formation of dielectric and passivation layers by high temperature thermal oxidation, resulting in reduced deposition and patterning operations. A processing sequence in accordance with embodiments of the present invention can incorporate simultaneous etching or oxidation operations of different features to reduce the number of masks required during processing.

In another aspect, embodiments of the present invention describe a transfer head and a transfer head array including a through hole extending through a base substrate from a rear side of the base substrate to the patterned ruthenium layer, the pass The holes are used to connect the electrodes to the working circuitry of the transfer head element. The processing sequence in accordance with an embodiment of the present invention also imparts passivation that extends through the via of the base substrate using high temperature thermal oxidation growth.

In yet another aspect, embodiments of the present invention describe a manner for mass transfer of an array of pre-fabricated microdevices using a compatible transfer head array. Example In other words, pre-fabricated microdevices may have specific functions such as, but not limited to, LEDs for illumination, germanium ICs for logic and memory, and gallium arsenide (GaAs) circuits for radio frequency (RF) communication. In some embodiments, an array of micro LED devices that may be used for picking is described as having a pitch of 10 [mu]m by 10 [mu]m, or a pitch of 5 [mu]m by 5 [mu]m. At these densities, a 6-inch substrate, for example, can accommodate approximately 165 million micro-LED devices having a pitch of 10 μm by 10 μm, or approximately 660 million micro-LED devices having a pitch of 5 μm by 5 μm. A transfer tool comprising a compatible transfer head array that matches an integer multiple of the pitch of the corresponding array of micro LED devices can be used to pick up and transfer the array of micro LED devices to the receiving substrate. In this way, it is possible to integrate and assemble micro-LED devices to a heterogeneously integrated system at high transfer rates, including substrates of any size ranging from microdisplays to large area displays. For example, a 1 cm by 1 cm microdevice transfer head array can pick up and transfer more than 100,000 micro devices, with a larger micro device transfer head array capable of transferring more micro devices.

Referring now to FIG. 1A, a plan view of a portion of a bipolar microdevice transfer head array having a single-sided clamp cantilever pair without a joint is provided, and the plan view includes views at different depths. In the particular embodiment illustrated, the shaded regions illustrate the arrangement of the germanium electrodes and the germanium interconnect structure as viewed from the top surface of the compatible bipolar microdevice transfer head array. From the rear side surface of the compatible bipolar microdevice transfer head array, the darker shading shows the rear side via connection. In this way, the plan view provides details about the structure that has been formed by the sides of the SOI wafer.

As shown, the compatible bipolar microdevice transfer head array 100 includes an arrangement that is coupled to the turns trace interconnect structure 104 and the bus bar interconnect structure 106. An array of compatible transfer heads 102. As shown, the busbar interconnect structure 106 can be formed around or outside the perimeter of the work area of the compatible bipolar transfer head array including the array of compatible transfer heads 102. In an embodiment, each compatible transfer head 102 includes a pair of germanium electrodes 110, wherein each germanium electrode 110 includes a mesa structure 112 and an electrode lead 114 connected to the germanium trace interconnect structure 104. As shown, each compatible transfer head 102 is clamped on the opposite side of the meander line interconnect structure 104 in the form of a pair of single-sided clamp cantilever beams. The pair of germanium electrodes 110 for each of the compatible transfer heads 102 of the embodiment illustrated in FIG. 1A are not joined, as shown by the joint trenches 117 between the pair of mesa structures 112. In the illustrated embodiment, the mesa structure 112 in the compatible bipolar microdevice transfer head array 100 is arranged at approximately the same pitch as the micro device to be picked up, for example, 10 μm by 10 μm, or 5 μm multiplied by 5 μm.

In an embodiment, a plurality of vias 120 are formed through the back side of the base substrate to the patterned germanium layer to make contact with the bus bar interconnect structure 106 to electrically connect the germanium electrode 110 with the operating circuitry of the transfer head element. In the embodiment illustrated in FIG. 1A, the busbar interconnect structure 106 on the left side of the drawing can be connected to the first voltage source V _A , and the bus bar interconnect structure 106 on the right side of the drawing can be connected to the second voltage source V. _B. When each compatible transfer head 102 is operable as a bipolar transfer head, the voltage source V _A and the voltage source V _B can simultaneously apply opposite voltages such that each of the tantalum electrodes 110 in the respective compatible transfer heads 102 One has the opposite voltage.

1B is a plan view of a compatible bipolar microdevice transfer head having a pair of single-sided clamping cantilever beams and jointless, in accordance with an embodiment of the present invention. As shown, the opposing tantalum electrode 110 is clamped to the tantalum trace interconnect structure on the opposite side. 104. For purposes of clarity, only a single compatible transfer head 102 is illustrated in FIG. 1B spanning between two turns of trace interconnect structure 104, although a bipolar transfer head array may be crossed in accordance with an embodiment of the present invention. Between the trace interconnect structures 104. The pair of turns electrodes 110 for each compatible transfer head 102 are not joined, as shown by the joint grooves 117 between the pair of mesa structures 112. In the illustrated embodiment, the joint trench 117 is parallel to the meander trace interconnect structure 104. 1C is a cross-sectional side view of the transverse line C-C of the compatible bipolar microdevice transfer head illustrated in FIG. 1B, in accordance with an embodiment of the present invention. In the embodiment illustrated in FIG. 1C, each of the germanium electrodes 110 in the bipolar electrode configuration extends from the separate germanium trace interconnect structure 104. 1D is a cross-sectional side view of a longitudinal line D-D of the compatible bipolar microdevice transfer head illustrated in FIG. 1B, in accordance with an embodiment of the present invention. As illustrated in FIGS. 1C-1D, both of the erbium mesa structure 112 and the electrode leads 114 extend over the cavity 136 between the base substrate 130 and the 矽 electrode 110 and can be deflected into the cavity 136. In an embodiment, a single cavity 136 is formed under the bipolar germanium electrode array 110 and between two separate germanium trace interconnect structures 104. Referring again to FIG. 1A, a single or multiple separation cavities 136 can be formed between the array of meander line interconnect structures 104. In an embodiment, the cavities 136 are the same cavity. For example, cavity 136 can surround germanium trace interconnect structure 104 and be located below germanium electrode array 110. Trench 116 may also be formed in the patterned germanium layer to define germanium electrode 110 and germanium trace interconnect structure 104 and busbar interconnect structure 106, as described in more detail below. If the cavity 136 does not surround the end of the meandering interconnect structure 104, the trench 116 may also be formed at the end of the patterned trace interconnect structure 104 in the patterned germanium layer.

Referring now to Figures 2A through 2B, Figures 3A through 3B and 4A through 4B, which together illustrate various different compatible bipolar transfer head array configurations in accordance with embodiments of the present invention. It will be understood that while the following variations are illustrated and described separately, the variations are not necessarily incompatible with each other, and in one or more embodiments the variations may be combined in any suitable manner.

2A through 2B are combined plan views and combined cross-sectional side views along lines V-V, W-W, X-X, Y-Y, and Z-Z of Fig. 1A, in accordance with an embodiment of the present invention. 3A to 3B and 4A to 4B are combined plan views and combined cross-sectional side views as drawn in the similar manners in Figs. 2A to 2B. The combined view does not represent an exact relative position for all of the different features of the illustration, in particular, the combined view combines the specific features at different locations previously identified in Figure 1A to more easily represent the specificity of the processing sequence Variety. For example, although a combined cross-sectional side view illustrates one via 120 corresponding to one germanium electrode 110, as seen in FIG. 1A, one via 120 can be interconnected along one or more traces The plurality of germanium electrodes 110 of the structure 104 are electrically connected. As shown, the line W-W and the line Y-Y are along the through hole 120. As shown, lines V-V and lines Z-Z are along one or more trenches 116 that define germanium electrode 110 and germanium trace interconnect structure 104 and busbar interconnect structure 106. As shown, line X-X passes through a bipolar transfer head that includes a pair of turns electrodes 110. Referring again to FIG. 1A, one or more cavities 136 can be formed around and below all of the germanium electrodes 110, and between the germanium trace interconnect structure 104 and the busbar interconnect structure 106.

Referring again to FIGS. 2A-2B, the ruthenium electrode 110 includes a mesa structure 112 and an electrode lead 114, wherein the mesa structure 112 is a raised portion of the ruthenium electrode 110. A dielectric layer 118 may cover a top surface of the pair of germanium electrodes 110. The dielectric layer 118 may also laterally cover the side surface of the mesa structure 112 between the pair of mesa structures 112 of the pair of germanium electrodes 110 in the compatible transfer head 102. In the illustrated embodiment, each cantilever compatible transfer head 102 is separated by an open space in the joint groove 117, and each turn electrode 110 can be individually deflected into the cavity 136. The via opening 120A can extend through the base substrate 130 from the back side of the base substrate to the patterned germanium layer 140 where the busbar interconnect structure 106 is located. In the particular embodiment illustrated in FIGS. 2A-2B, the via opening 120A extends through the buried oxide layer 124 and terminates at the bottom surface of the patterned germanium layer 140 where the busbar interconnect structure 106 is located. A passivation layer 132 is formed on the rear side of the base substrate 130, and a passivation layer 133 is formed on a side surface inside the via opening 120A. When the base substrate is formed of tantalum, the passivation layer 132 and the passivation layer 133 insulate the electrical short between the vias 120. The buried oxide layer 124 also insulates electrical shorts between the germanium electrodes 110 and between the germanium trace interconnect structure 104 and the busbar interconnect structure 106.

The through holes 120 illustrated in FIGS. 2A to 2B extend through the base substrate 130 from the rear side of the base substrate to the patterned ruthenium layer 140. In an embodiment, the vias 120 contact one or more of the bus bar interconnect structures 106 in the patterned germanium layer 140. In other embodiments, the vias 120 may contact other features or interconnect structures in the patterned germanium layer 140. The via 120 along the line WW can be electrically connected to the first interconnect structure 106, the first bus interconnect structure 106 is connected to the first voltage source V _A , and the via 120 along the line YY is electrically Connected to the second busbar interconnect structure 106, the second busbar interconnect structure 106 is coupled to a second voltage source _VB . In the particular embodiment illustrated, the via opening 120A extends through the buried oxide layer 124 and terminates at the bottom surface of the busbar interconnect structure 106. The passivation layer 132 is formed on the rear side of the base substrate 130 and the side surface inside the via opening 120A. Conductive layer 122 is formed on passivation layer 133 and in electrical contact with the bottom surface of bus bar interconnect structure 106. In the particular embodiment illustrated, the conductive layer 122 does not completely fill the via opening 120A, and the conductive layer 122 is physically and electrically separated to prevent vias connected to different voltage sources V _A , V _B . Short circuit between 120. In an embodiment, the vias 120 electrically connected to the same voltage source may or may not be physically and electrically connected. For example, the conductive layer 122 can span the two via holes 120 on the left side of FIG. 1A, and the conductive layer 122 is also electrically and physically separated from the via hole 120 along the line YY on the right side of FIG. In the embodiment, the structures illustrated in FIGS. 2A to 2B are formed using a total of six masks.

3A-3B are combined plan views and combined cross-sectional side views of a compatible bipolar microdevice transfer head including a double-sided clamping support beam, in accordance with an embodiment of the present invention. And the pair of germanium electrodes 110 and the oxide joint 119 connecting the pair of germanium electrodes 110, and the upper through hole opening and the rear side through hole opening. It should be understood that although the oxide joint 119 and the upper through hole opening and the rear side through opening are collectively illustrated in FIGS. 3A to 3B, the embodiment of the present invention is not limited thereto, and the oxide joint 119 is not necessary. Together with the upper through hole opening and the rear side through hole opening. As shown, in one embodiment, an oxide joint 119 is formed between the mesa structures 112 for the counter electrode 110 and is coupled to the mesa structure 112, and the oxide tab 119 is located on the buried oxide layer 140. And directly contacting the buried oxide layer 124. Since the oxide joint 119 is connected to the tantalum electrode 110, the bipolar electrode elements illustrated in FIGS. 3A to 3B are characterized as supporting beam junctions between the tantalum interconnect structures. Structure. As shown, in one embodiment, an upper through hole opening 120B may be formed over the rear side through hole opening 120A to form a through hole 120. As will be apparent from the description below, the upper via opening 120B can be formed to make electrical contact with the busbar interconnect structure 106 and to form an opening through the buried oxide layer without being associated with lithography challenges. 124, without adversely affecting the passivation layer 133 along the sidewalls of the via opening 120A. Conductive layer 123 may optionally be formed over the exposed top surface of bus bar interconnect structure 106 and inside the inner side surface of bus bar interconnect structure 106. In this manner, forming the conductive layer 123 partially over the top surface of the busbar interconnect structure 106 can provide a larger surface area for ohmic contact with the busbar interconnect structure 106. Since the bus bar interconnect structure 106 is closer to the top surface of the SOI structure than the back side surface of the SOI structure, in accordance with some embodiments, the bus bar interconnects from above the top surface of the SOI structure as compared to the back surface of the SOI structure. Forming the conductive layer 123 inside the inner surface of the structure 106 may be more efficient. The conductive layer 123 may be formed of the same or different material as the conductive layer 122. The conductive layer 122 and the conductive layer 123 may form a continuous conductive layer along a side surface of the via 120. In the embodiment, the structures illustrated in FIGS. 3A to 3B are formed using a total of seven masks.

4A through 4B are combined plan views and combined cross-sectional side views of a compatible bipolar microdevice transfer head including a double-sided clamping support beam, in accordance with an embodiment of the present invention. And a deposition dielectric layer 126, an oxide interface 119 between the pair of germanium electrodes 110 and the pair of germanium electrodes 110, and an upper via opening and a rear via opening. It should be understood that although the dielectric layer 126, the oxide tab 119, and the upper back side via opening and the back side via opening are collectively illustrated in FIGS. 4A-4B, embodiments of the present invention are not limited thereto. It is not necessary to deposit the dielectric layer 126 along with the oxide tab 119 and the upper via opening and the back via opening. As shown, in one embodiment, the dielectric layer 118 can be partially or completely removed. In the particular embodiment illustrated in FIGS. 4A-4B, dielectric layer 118 is removed from mesa structure 112. A second dielectric layer 126 is formed over the top surface of the mesa structure 112 and over the remaining profile of the transfer head array, and the second dielectric layer 126 can include portions of the dielectric layer 118. The dielectric layer 126 may also cover any of the oxide via 119, the upper via opening 120B, and the corresponding conductive layer 123, and the dielectric layer 126 may partially or completely fill the upper side of the interior of the busbar interconnect structure 106. Through hole opening 120B. In an embodiment, dielectric layer 126 has a higher dielectric constant and/or dielectric breakdown strength than dielectric layer 118. In an embodiment, the dielectric layer 118 is thermally grown SiO ₂ and the dielectric layer 126 is atomic layer deposition (ALD) SiO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ or RuO ₂ . It should be understood that although FIGS. 4A-4B illustrate variants of FIGS. 3A-3B, the features of dielectric layer 126 may be combined with the embodiments illustrated in FIGS. 2A-2B. In the embodiment, a structure illustrated in FIGS. 4A to 4B is formed using a total of eight masks.

5A through 15B illustrate a method of forming a compatible bipolar microdevice transfer head including an open joint groove and a rear side through hole opening between a pair of tantalum electrodes, in accordance with an embodiment of the present invention. Initially, the processing sequence can begin with a commercially available SOI substrate, as illustrated in Figures 5A-5B. The SOI substrate may include a base substrate 130, a top end layer 140, a buried oxide layer 124 between the base substrate and the top end layer, and a back side passivation layer 132. In an embodiment, the base substrate is a (100) 矽 processed wafer having a thickness of 500 μm +/- 50 μm, the buried oxide layer 124 is 1 μm +/- 0.1 μm thick and the top ruthenium layer is 7 μm to 20 μm +/- 0.5 μm. thick. The top ruthenium layer can also be doped to improve conductivity. For example, a phosphorus-containing dopant concentration of about 10 ¹⁷ cm ^-3 produces a resistivity of less than 0.1 ohm-cm. In an embodiment, the backside passivation layer 132 is a thermal oxide having a thickness of up to about 2 [mu]m thick that is close to the upper limit of thermal oxidation of the ruthenium.

A mask layer 142 can then be formed over the top ruthenium layer 140, as illustrated in Figures 6A-6B. Mask layer 142 may be thermally grown from deposition or alternatively from top ruthenium layer 140. In an embodiment, the mask layer 142 is a thermally grown SiO ₂ layer having a thickness of about 0.1 μm. In an embodiment, when the mask layer 142 is thermally grown SiO ₂ , the mask layer 142 has a thickness that is significantly less than the thickness of the buried oxide (SiO ₂ ) layer 124 during removal of the patterned mask layer. The structural stability of the partially patterned SOI structure is maintained.

Referring to Figures 7A through 7B, the mask layer 142 is then patterned to form an array of islands 144 that will correspond to the mesa structure of the germanium electrode. In an embodiment, the mask layer is a thermally grown SiO ₂ layer, and the island 144 is exposed by a positive photoresist, using a potassium hydroxide (KOH) developer solution, and removing the undeveloped area of the photoresist. To form. Subsequent use such as ion milling, plasma etching, reactive ion etching (RIE) or reactive ion beam etching (RIBE), electron cyclotron resonance (ECR) or inductively coupled plasma ( A suitable technique for inductively coupled plasma (ICP) dry etches the mask layer 142 to form islands 144, terminating on the germanium layer 140. If required a high degree of anisotropic etching may be used such as the use of CF _4, SF ₆ or NF ₃ plasma etchant in a dry plasma etching techniques. The patterned photoresist is then removed by O ₂ ashing followed by piranha etching to produce the structures illustrated in Figures 7A-7B.

In an embodiment, the back side via opening 120A is subsequently formed in the SOI substrate. Initially, as illustrated in FIGS. 8A-8B, the backside via opening is formed through the backside passivation layer 132 and the base substrate 130, terminating on the buried oxide layer 124. In an embodiment, the 8A to 8B are formed by applying a patterned positive photoresist onto the backside passivation layer 132, followed by etching the exposed passivation layer 132 and the dry reactive ion etching (DRIE) base substrate 130. The rear side via opening 120A illustrated in the figure terminates on the buried oxide layer 124. The base substrate 130 may alternatively be etched using a wet etchant such as KOH. However, the KOH wet etchant preferentially etches germanium in the (100) plane and can produce an anisotropic V-etch with tapered sidewalls. A DRIE etch can be selected for the more vertical sidewalls in the backside via opening 120A. After etching the base substrate 130, the patterned positive photoresist can be removed by O ₂ ashing followed by piranha etching to produce a structure as illustrated in FIGS. 8A-8B.

Referring to Figures 9A through 10B, the germanium electrode 110 and the germanium trace interconnect structure 104 and the busbar interconnect structure 106 are patterned in a two-etch sequence. First, as illustrated in FIGS. 9A-9B, the top germanium layer 140 is partially etched through to define the patterns of the germanium electrode 110 and the germanium trace interconnect structure 104 and the busbar interconnect structure 106. In an embodiment, this can be accomplished using a thin patterned positive photoresist, which is etched approximately 5 [mu]m from a 7 [mu]m to 10 [mu]m thick top germanium layer 140 in a timed etch. The patterned positive photoresist can be removed using O ₂ ashing followed by piranha etching. According to an embodiment of the present invention, the opening in the photoresist 121 on the edge of FIG. 9A (illustrated only in FIG. 9A) corresponds to defining the germanium electrode 110 and the germanium trace interconnect structure 104 and the bus bar interconnection The size of the trenches 116 of the structure 106, however, may correspond to openings in the photoresist 121 above the islands 144 of the tab trenches 117 between the germanium electrode mesas 112. In this manner, the islands 144 in the patterned hard mask layer 142 can be used to form the tantalum electrode mesa structure 112 having the tab trenches 117 between the mesa structures as compared to the photoresist alone. Higher gap resolution. In an embodiment, the joint trench 117 opening is at least sufficiently wide to grow the dielectric layer 118 on the side surface of the adjacent mesa structure 112 and to allow each germanium electrode 110 to deflect into the cavity 136. For example, the joint groove 117 can be 2 μm wide or larger.

Second, the islands 144 as illustrated in FIGS. 10A-10B are still present, using the island 144 as a mask to continue the DRIE etch to form the germanium electrode 110 and the germanium trace interconnect structure 104 including the extended mesa structure 112 and The busbar interconnect structure 106 terminates on the underlying buried oxide layer 124. After the etching of the germanium layer 140 is completed, a dry etching technique is performed to remove the islands 144 by about 0.1 μm. In an embodiment, when only 0.1 μm of oxide is removed and the buried oxide layer 124 is approximately 1.0 μm thick, the exposed buried oxide layer 124 significantly exceeding 0.1 μm is not removed. In accordance with an embodiment of the present invention, the buried oxide layer 124 provides structural stability to the partially patterned SOI structure and significantly exceeds the thickness of the island 144 during removal of the island 144 from the buried oxide layer 124. As illustrated in FIG. 10B, the buried oxide layer 124 is exposed between the tab trenches 117 between the germanium electrodes and the trenches 116 surrounding the germanium electrodes and between the interconnect structures.

Referring now to Figures 11A through 11B, the front and back sides of the SOI wafer can then be oxidized to passivate the germanium electrode, the germanium interconnect structure, and the back side via. Opening. In an embodiment, high temperature wet oxidation may be performed to grow on the germanium electrode 110, inside the joint trench 117 between the mesa structures 112, on the germanium trace interconnect structure 104 and the busbar interconnect structure 106, and inside the trench 116. A dielectric layer 118 is about 1 μm thick. Where the buried oxide layer 124 has been exposed, the thickness of the buried oxide layer 124 may increase or remain the same depending on the thickness previously present. In an embodiment, the dielectric layer 118 and the buried oxide layer 124 are about the same thickness. An oxide passivation layer 133 of about 1 μm thick is also grown inside the back side via opening 120A along the sidewall of the base substrate 130.

Referring now to FIGS. 12A through 12B, a thick patterned positive photoresist is applied over the germanium trace interconnect structure 104 and the busbar interconnect structure 106 and the germanium electrode 110, followed by etching the joint trench 117 and the trench region. The buried oxide exposed in 137 will correspond to the location where cavity 136 is formed. The patterned positive photoresist can be removed using O ₂ ashing followed by piranha etching.

A dry oxide etch using a suitable dry etch technique can then be performed to create an opening in the buried oxide layer 124 inside the backside via opening 120A to expose the bottom surface of the patterned germanium layer 140, at the bottom surface The bus bar interconnect structure 106 is formed as illustrated in Figures 13A-13B. In an embodiment, a thin positive photoresist is formed over the back side of the SOI wafer and inside the back side via opening 120A and patterned. The buried oxide layer 124 is then etched to expose the bottom surface of the tantalum layer 140. In an embodiment, etching of the buried oxide layer 124 is performed using RIE. As shown, the opening in the buried oxide layer 124 is smaller (eg, smaller in diameter or cross-section) than the opening in the interior of the base substrate 130 (including the oxide passivation layer 133). In this way, inside the buried oxide layer 124 than in the base substrate (including the oxide passivation layer 133) The smaller opening prevents inadvertent etching through the oxide passivation layer 133 or the undercut oxide passivation layer 133 and the electrically short via 120 and the base substrate 130. Due to lithography tolerances and resolution capabilities, the openings inside the buried oxide layer 124 may have a minimum cross-section greater than 10 [mu]m.

Referring now to FIGS. 14A-14B, a patterned conductive layer 122 is formed over the passivation layer 133 inside the via opening 120A and in electrical contact with the bottom surface of the busbar interconnect structure 106. In an embodiment, the patterned conductive layer 122 is formed by sputtering through a shadow mask. In an embodiment, the patterned conductive layer 122 includes a 500 angstrom thick titanium (Ti) first layer, a 500 angstrom thick titanium-tungsten (TiW) intermediate layer, and a 1 μm to 2 μm thick gold (Au) outer layer. In an embodiment, the patterned conductive layer 122 is in ohmic contact with the bus bar interconnect structure 106.

Referring now to FIGS. 15A-15B, one or more cavities 136 can then be etched in the base substrate 130 just below the ruthenium electrode array such that the ruthenium electrode array can be deflected into one or more cavities. In an embodiment, a separate cavity 136 is formed just below each pair of ruthenium electrodes. In an embodiment, a single cavity 136 is formed just below the array of germanium electrodes in electrical communication with the first meandering interconnect structure and the second meandering interconnect structure 104. In an embodiment, a time-controlled release etch is used to form the cavity 136 into the base substrate 130, which etches the undercut electrode leads 114 and the mesa structure 112. For example, etching can be performed using a fluorine-based chemistry such as XeF ₂ or SF ₆ .

After forming one or more cavities 136, the SOI substrate can then be cut, for example, using laser cutting to form a compatible bipolar transfer head array that includes interconnects with the germanium traces Array and extension of the compatible transfer head 102 interconnected by the structure 104 and the busbar interconnect structure 106 The base substrate 130 extends from the rear side of the base substrate to the patterned germanium layer 140 to electrically connect the drain electrode 120 and the through hole 120 of the working circuit system of the transfer head element.

Figure 16A is a plan view of a compatible bipolar microdevice transfer head array having dual clamping support beams and mesa joints in accordance with an embodiment of the present invention. The particular embodiment illustrated in FIG. 16A is similar to the embodiment illustrated in FIG. 1A, with one difference being between the pair of 矽 electrodes 110 for each compatible transfer head 102 and the pair of mesa structures 112 The oxide joint 119 is joined. Due to the oxide joint 119, the pair of turns electrodes in the bipolar microdevice transfer head are in the form of a double-sided clamped support beam that is supported on the opposite side using the meander line interconnect structure 104. A single cavity 136 can be formed between the array of compatible transfer heads 102 across a pair of meander line interconnect structures 104. A plurality of cavities 136 may be formed between the plurality of pairs of trace trace interconnect structures 104 or a single cavity 136 may be formed between the plurality of pairs of trace trace interconnect structures 104. Trench 116 may also be formed to define germanium electrode 110 and germanium trace interconnect structure 104 and busbar interconnect structure 106 in the patterned germanium layer.

Figure 16B is a plan view of a compatible bipolar microdevice transfer head having dual clamping support beams and mesa joints in accordance with an embodiment of the present invention. Figure 16C is a cross-sectional side view of transverse line C-C of the compatible bipolar microdevice transfer head illustrated in Figure 16B, in accordance with an embodiment of the present invention. Figure 16D is a cross-sectional side view of the longitudinal line D-D of the compatible bipolar microdevice transfer head illustrated in Figure 16B, in accordance with an embodiment of the present invention. Similar to the embodiment illustrated in FIGS. 1B-1D, only a single compatible transfer head 102 is illustrated across the two trace interconnect structures 104 and through two traces of the traces in FIG. 16B. The structure 104 is supported, although the transfer head array may be spanned in accordance with an embodiment of the present invention Between the trace interconnect interconnect structures 104. The pair of germanium electrodes 110 for each compatible transfer head 102 are joined to the oxide joint 119 between the pair of mesa structures 112. In the illustrated embodiment, the oxide junction 119 is parallel to the meander trace interconnect structure 104. As illustrated in FIGS. 16C through 16D, both the tantalum mesa structure 112 and the electrode leads 114 extend over the cavity 136 between the base substrate 130 and the tantalum electrode 110 and can be deflected into the cavity 136. In the embodiment illustrated in FIG. 16D, oxide junction 119 is on buried oxide layer 124 and is in direct contact with buried oxide layer 124.

17A through 24B illustrate a method of forming a compatible bipolar microdevice transfer head including a double-sided clamping support beam and the pair of germanium electrodes, in accordance with an embodiment of the present invention. And an oxide joint connecting the pair of electrodes and an upper through hole opening and a rear side through opening. In an embodiment, the processing sequence directed to FIGS. 17A through 17B may be the same as the processing sequence of FIGS. 5A through 8B, with one difference being the distance between islands 144. As described in more detail in the following description, the patterning of islands 144 corresponds to the mesa structure 112 to be subsequently formed. Further, the distance between the islands 144 corresponds to the width of the oxide joint 119 which is formed between the pair of tantalum electrodes 110 and which is connected to the pair of tantalum electrodes 110. Therefore, since the oxide joint 119 is connected to the pair of 矽 electrodes 110 in the double-sided clamping support beam configuration, the distance between the islands 144 in FIGS. 17A to 17B can be smaller than those in FIGS. 8A to 8B. The distance between the islands 144. For example, the distance between the islands can be small enough to allow the joint trench 117 to be completely filled with oxide that is thermally grown from the mesa structure 112. For example, the joint groove 117 can be 2 μm wide or smaller.

Referring to FIGS. 17A through 18B, the germanium electrode 110 and the germanium trace interconnect structure 104 and the busbar interconnect structure 106 may be patterned in a two-etch sequence. First, as illustrated in FIGS. 17A-17B, the top germanium layer 140 is partially etched through to define the patterns of the germanium electrode 110 and the germanium trace interconnect structure 104 and the busbar interconnect structure 106. In an embodiment, this can be accomplished using a thin patterned positive photoresist in which DRIE etches a 7 μm to 10 μm thick top germanium layer 140 of about 5 μm in a timed etch. According to an embodiment of the present invention, the opening in the photoresist 121 on the edge of FIG. 17A (illustrated only in FIG. 17A) corresponds to defining the germanium electrode 110 and the germanium trace interconnect structure 104 and the bus bar interconnection The size of the trenches 116 of the structure 106, however, may correspond to openings in the photoresist 121 above the islands 144 of the tab trenches 117 between the germanium electrode mesas 112. In this manner, the islands 144 in the patterned hard mask layer 142 can be used to form the tantalum electrode mesa structure 112 having the tab trenches 117 between the mesa structures as compared to the photoresist alone. Higher gap resolution. In this manner, the islands 144 in the patterned hard mask layer 142 can be used to form the tantalum electrode mesa structure 112, which has a higher gap resolution between the mesa structures than the photoresist alone. This can help increase the effective area of the electrode and the resulting clamping force across the array of compatible transfer heads. For example, as the microdevice size decreases, a narrower gap between the mesa structures can increase the available electrode space with respect to the microdevice to be picked up. The patterned positive photoresist can be removed using O ₂ ashing followed by piranha etching.

Second, the islands 144 as illustrated in FIGS. 18A-18B are still present, using the island 144 as a mask to continue the DRIE etch to form the germanium electrode 110 and the germanium trace interconnect structure 104 including the extended mesa structure 112 and The busbar interconnect structure 106 terminates on the underlying buried oxide layer 124. After etching is completed After the germanium layer 140, a dry etching technique is performed to remove the island 144 by about 0.1 [mu]m. In an embodiment, when only 0.1 μm of oxide is removed and the buried oxide layer 124 is approximately 1.0 μm thick, the buried oxide layer 124 that is significantly exposed beyond 0.1 μm is not removed. In accordance with an embodiment of the present invention, the buried oxide layer 124 provides structural stability to the partially patterned SOI structure and significantly exceeds the thickness of the island 144 during removal of the island 144 from the buried oxide layer 124.

Referring now to Figures 19A through 19B, the front and back sides of the SOI wafer can then be oxidized to passivate the germanium electrode, the germanium interconnect structure, and the back side via opening. In an embodiment, high temperature wet oxidation may be performed to grow on the germanium electrode 110, inside the joint trench 117 between the mesa structures 112, on the germanium trace interconnect structure 104 and the busbar interconnect structure 106, and inside the trench 116. A dielectric layer 118 is about 1 μm thick. As described above, the dielectric (e.g., oxide) layer forms the oxide joint 119 as the dielectric layer 118 grows inside the joint trench 117 and fills the joint trench 117. In an embodiment, the oxide joint 119 completely fills the joint groove 117. After the buried oxide layer 124 has been exposed, the thickness of the buried oxide layer 124 may increase or remain the same depending on the thickness previously present. In an embodiment, the dielectric layer 118 and the buried oxide layer 124 are about the same thickness. An oxide passivation layer 133 of about 1 μm thick is also grown inside the back side via opening 120A along the sidewall of the base substrate 130.

Referring now to FIGS. 20A through 20B, openings (which will be part of the via opening 120B) are formed in the top dielectric layer 118 to be exposed just above the back side via opening 120A and in the trench region 137 ( A patterned germanium layer 140 at the region of the busbar interconnect structure 106 at one or more of the cavities 136) will be formed herein. The trench region 137 opening is also simultaneously formed in the buried oxide layer 124 to expose the base substrate 130 (where one or more cavities 136 will be formed). Openings may be formed in the top dielectric layer 118 and the buried oxide layer 124 using a thick patterned positive photoresist followed by a dry etched top dielectric layer 118. The patterned photoresist is then removed by O ₂ ashing followed by piranha etching to produce the structures in Figures 20A-20B. Forming the etch and patterning steps to form the via opening 120B and the trench region 137 opening also reduces the number of processing operations and the number of masks required.

Referring now to FIGS. 21A through 21B, openings are formed in the tantalum layer 140 and the buried oxide layer 124 to form an upper side via opening 120B that connects the back side via opening 120A. The ruthenium layer 140 can be formed by forming a thick patterned positive photoresist, then performing DRIE termination of the germanium layer 140 on the buried oxide layer 124, followed by RIE through the buried oxide layer 124. An opening is formed in the buried oxide layer 124. The patterned photoresist is then removed by O ₂ ashing followed by piranha etching to produce the structures in Figures 21A-21B. In this manner, forming an opening through the buried oxide layer 124 when the upper via opening 120B is formed may avoid lithography challenges associated with forming an opening in the buried oxide layer 124 from the back side of the SOI structure, The passivation layer 133 along the sidewalls of the via opening 120A is not adversely affected.

The patterned conductive layer 123 can then be formed over the exposed top surface of the bus bar interconnect structure 106 and inside the inner side surface of the bus bar interconnect structure 106, as illustrated in Figures 22A-22B. In this manner, forming the conductive layer 123 partially over the top surface of the busbar interconnect structure 106 can provide a larger surface area for ohmic contact with the busbar interconnect structure 106. Since the bus bar interconnect structure 106 is closer to the SOI junction than the rear side surface of the SOI structure The top surface of the structure, according to some embodiments, may be more efficient to form a conductive layer 123 inside the inner surface of the busbar interconnect structure 106 from above the top surface of the SOI structure as compared to the back surface of the SOI structure. In an embodiment, the patterned conductive layer 123 is formed by sputtering through a shadow mask. In an embodiment, the patterned conductive layer 123 includes a 500 angstrom thick titanium (Ti) first layer, a 500 angstrom thick titanium-tungsten (TiW) intermediate layer, and a 1 μm to 2 μm thick gold (Au) outer layer. In an embodiment, the patterned conductive layer 123 is in ohmic contact with the bus bar interconnect structure 106.

Referring now to FIGS. 23A-23B, the patterned conductive layer 122 can be formed in electrical contact with the patterned conductive layer 123 on the passivation layer 133 inside the via opening 120A. The conductive layer 122 may be formed of the same or different material as the conductive layer 123 and may have the same or different thicknesses. In an embodiment, the conductive layer 123 has a thicker gold layer.

Referring now to Figures 24A through 24B, one or more cavities 136 can then be etched in the base substrate 130 just below the xenon electrode array such that the tantalum electrode array can be deflected into one or more cavities. In an embodiment, a separate cavity 136 is formed just below each pair of ruthenium electrodes. In an embodiment, a single cavity 136 is formed just below the array of germanium electrodes in electrical communication with the first meandering interconnect structure and the second meandering interconnect structure 104. In an embodiment, a time-controlled release etch is used to form the cavity 136 into the base substrate 130, which etches the undercut electrode leads 114 and the mesa structure 112. For example, etching can be performed using a fluorine-based chemistry such as XeF ₂ or SF ₆ . In an embodiment, one or more of the cavities 136 are approximately 15 [mu]m deep.

After forming one or more cavities 136, the SOI base can then be cut The plates, for example, use laser cutting to form an array of compatible bipolar transfer heads including compatible transfer heads interconnected with the turns trace interconnect structure 104 and the bus bar interconnect structure 106 An array of 102 and a through hole 120 extending through the base substrate 130 from the rear side of the base substrate to the patterned germanium layer 140 and through the patterned germanium layer 140 to electrically connect the drain electrode 110 and the working circuitry of the transfer head element.

25A through 30B illustrate a method of forming a compatible bipolar microdevice transfer head including a double-sided clamping support beam and a deposition dielectric layer 126, in accordance with an embodiment of the present invention. The pair of germanium electrodes 110 and the oxide joint 119 connecting the pair of germanium electrodes 110 and the upper through hole opening and the rear side through hole opening. In the embodiment, the processing sequence leading to FIGS. 25A to 25B may be the same as the processing sequences of FIGS. 5A to 7B and 17A to 19B as described above. Referring now to Figures 25A through 25B, in an embodiment the opening is formed in the top dielectric layer 118 just above the back side via opening 120A and just above the mesa structure 112.

Referring now to Figures 25A through 25B, openings are formed in the top dielectric layer 118 to expose the terrace surface structure 112 and the oxide tabs 119 (and optionally portions of the electrode leads 114), and the openings (the openings will become A portion of the aperture opening 120B is formed in the top dielectric layer 118 just above the back side via opening 120A. The trench region 137 opening is also simultaneously formed in the buried oxide layer 124 to expose the base substrate 130 (where one or more cavities 136 will be formed). In the particular embodiment illustrated, the oxide joint 119 is not completely removed from between adjacent mesa structures 112 in the compatible transfer head 102. An opening can be formed in the top dielectric layer 118 and the buried oxide layer 124 using a thick patterned positive photoresist followed by dry etching of the top dielectric layer 118. In an embodiment, a time controlled dry oxide etch is performed to ensure that the oxide joint 119 is not completely removed. In an embodiment, the top dielectric layer 118 and the buried oxide layer 124 have approximately the same thickness, and when the thickness of the oxide joint 119 less than 0.2 μm is removed, it can be completely completed in a time-controlled dry oxide etch. The top dielectric layer 118 and the buried oxide layer 124 are removed. The patterned photoresist is then removed by O ₂ ashing followed by piranha etching to produce the structures in Figures 25A through 25B. Forming the etch and patterning steps to form the via opening 120A and the trench region 137 opening also reduces the number of processing operations and the number of masks required.

Referring now to FIGS. 26A through 26B, in an embodiment, a second dielectric layer 126 is formed over the top surface, the top surface including a patterned dielectric layer 118, a patterned germanium layer 140, and an oxide joint 119, followed by The second dielectric layer 126 is patterned using a thick positive photoresist and the second dielectric layer 126 is etched. After the etching is completed, the patterned second dielectric layer 126 covers the mesa structure 112 and may also cover portions of the electrode leads 114 and the patterned dielectric layer 118. The patterned second dielectric layer 126 is removed from directly above the upper back via opening 120A of the patterned germanium layer 140 and the trench region 137 where one or more cavities 136 will be formed. In an embodiment, the second dielectric layer can have a higher dielectric constant or dielectric breakdown strength than the dielectric layer 118, and the second dielectric layer has a thickness between 0.5 μm and 10 μm. For example, the second dielectric layer 126 is an Al ₂ O ₃ layer, a Ta ₂ O ₅ layer, or an HfO ₂ layer deposited by atomic layer deposition (ALD).

Referring now to FIGS. 27A through 27B, openings are formed in the tantalum layer 140 and the buried oxide layer 124 to form an upper side via opening 120B that connects the back side via opening 120A. The ruthenium layer 140 can be formed by forming a thick patterned positive photoresist, then performing DRIE termination of the germanium layer 140 on the buried oxide layer 124, followed by RIE through the buried oxide layer 124. An opening is formed in the buried oxide layer 124. The patterned photoresist is then removed by O ₂ ashing followed by piranha etching to produce the structures in panels 27A through 27B. In this manner, forming an opening through the buried oxide layer 124 when the upper via opening 120B is formed can avoid the lithography challenge associated with forming an opening in the buried oxide layer 124 from the back side of the SOI structure. The passivation layer 133 along the sidewalls of the via opening 120A is not adversely affected.

Patterned conductive layer 123 is then formed over the exposed top surface of bus bar interconnect structure 106 and inside the inner side surface of bus bar interconnect structure 106, as illustrated in Figures 28A-28B. In this manner, forming the conductive layer 123 partially over the top surface of the busbar interconnect structure 106 can provide a larger surface area for ohmic contact with the busbar interconnect structure 106. Since the bus bar interconnect structure 106 is closer to the top surface of the SOI structure than the back side surface of the SOI structure, in accordance with some embodiments, the bus bar interconnects from above the top surface of the SOI structure as compared to the back surface of the SOI structure. Forming a layer of conductive layer 123 inside the inner surface of structure 106 may be more efficient. In an embodiment, the patterned conductive layer 123 is formed by sputtering through a shadow mask. In an embodiment, the patterned conductive layer 123 includes a 500 angstrom thick titanium (Ti) first layer, a 500 angstrom thick titanium-tungsten (TiW) intermediate layer, and a 1 μm to 2 μm thick gold (Au) outer layer. In an embodiment, the patterned conductive layer 123 is in ohmic contact with the bus bar interconnect structure 106.

The patterned conductive layer 122 may be formed on the passivation layer 133 inside the via opening 120A and in electrical contact with the patterned conductive layer 123 as illustrated in FIGS. 29A-29B. The conductive layer 122 may be the same as or not the conductive layer 123 The same materials are formed and may have the same or different thicknesses. In an embodiment, the conductive layer 123 has a thicker gold layer. The conductive layer 122 and the conductive layer 123 may form a continuous conductive layer along a side surface of the via 120.

Referring now to FIGS. 30A through 30B, one or more cavities 136 can then be etched in the base substrate 130 just below the xenon electrode array such that the tantalum electrode array can be deflected into one or more cavities. In an embodiment, separate chambers 136 are formed directly below each pair of ruthenium electrodes. In an embodiment, a single cavity 136 is formed just below the array of germanium electrodes in electrical communication with the first meandering interconnect structure and the second meandering interconnect structure 104. In an embodiment, a time-controlled release etch is used to form the cavity 136 into the base substrate 130, which etches the undercut electrode leads 114 and the mesa structure 112. For example, etching can be performed using a fluorine-based chemistry such as XeF ₂ or SF ₆ . In an embodiment, one or more of the cavities 136 are approximately 15 [mu]m deep.

After forming one or more cavities 136, the SOI substrate can then be diced, for example, using laser dicing to form an array of compatible bipolar transfer heads including interconnected trace interconnect structures An array of compatible transfer heads 102 interconnected by the bus bar interconnect structure 106 and extending through the base substrate 130 from the rear side of the base substrate to the patterned germanium layer 140 and through the patterned germanium layer 140 for electrical connection The electrode 110 is connected to the through hole 120 of the working circuit system of the transfer head element.

31 through 37 illustrate various modifications of a compatible bipolar microdevice transfer head between the turns trace interconnect structures 104 in accordance with an embodiment of the present invention. Although FIGS. 31 to 37 are respectively illustrated according to the processing sequence illustrated above, it should be understood that many various modifications regarding FIGS. 31 to 37 may be The aforementioned processing sequence is implemented.

Figure 31 is a plan view and cross-sectional side view of line A-A along a compatible bipolar microdevice transfer head having a cantilever beam and a continuous joint, in accordance with an embodiment of the present invention. As shown, the tantalum electrode cantilever beam can include a pair of electrode leads 114 extending from two turns trace interconnect structures 104 and a pair of mesa structures 112 separated by a continuous oxide joint 119, the continuous oxide A joint 119 is located on the buried oxide layer 124 and is in direct contact with the buried oxide layer 124 and extends parallel to the pair of meander trace interconnect structures 104 in a longitudinal extent of the cantilever beam. In this embodiment, the oxide tab 119 electrically insulates the pair of turns in the bipolar electrode configuration along both the pair of electrode leads 114 and the pair of mesa structures 112 along the longitudinal length of the cantilever beam. As shown, the electrode lead 114 can include a bend 115 (shown as a 90 degree bend).

Figure 32 is a plan view and cross-sectional side view of line A-A along a compatible bipolar microdevice transfer head having a cantilever beam and a mesa joint, in accordance with an embodiment of the present invention. As shown, the tantalum electrode cantilever beam can include a pair of electrode leads 114 extending from the tantalum trace interconnect structure 104 and a pair of mesa structures 112 separated by mesa oxide tabs 119, the mesa oxide tabs 119 being located The buried oxide layer 124 is in direct contact with the buried oxide layer 124 and extends parallel to the pair of meander trace interconnect structures 104 in the longitudinal length of the cantilever beam. In this embodiment, the oxide tab 119 electrically insulates the pair of turns of the bipolar electrode configuration along the pair of mesa structures 112 along the longitudinal length of the cantilever beam. As shown, the pair of electrode leads 114 can include a bend 115 (shown as a 90 degree bend) by patterning physical separation.

Figure 33 is a diagram showing a double side clip along an embodiment in accordance with the present invention. A plan view and a cross-sectional side view of a line A-A of a compatible bipolar microdevice transfer head of a tight beam and a continuous joint. As shown, the tantalum electrode double side clamping beam can include a pair of curved electrode leads 114 extending from the two meander line interconnect structures 104 and a pair of mesa structures 112 separated by a continuous oxide joint 119, which A continuous oxide joint 119 is located on the buried oxide layer 124 and in direct contact with the buried oxide layer 124 such that the longitudinal length of the cantilever beam extends parallel to the pair of meander trace interconnect structures 104. In this embodiment, the oxide joint 119 electrically insulates the pair of turns in the bipolar electrode configuration along both the pair of electrode leads 114 and the pair of mesa structures 112 along the longitudinal length of the double-sided clamping beam. As shown, the electrode leads 114 can each include a bend 115 (shown as 90 degrees) at adjacent and distal locations where the electrode leads extend from the meander line interconnect structure 104.

Figure 34 is a plan view and cross-section of line AA of a compatible bipolar microdevice transfer head having a double sided clamping beam including a pair of 矽 electrodes (with double bends and mesa joints) in accordance with an embodiment of the present invention. Sectional side view. As shown, the tantalum electrode double-sided clamping beam can include a pair of electrode leads 114 extending from two turns of trace interconnect structure 104 (each electrode lead 114 having a double bend 115) and by a mesa oxide joint 119 A separate pair of mesa structures 112 on the buried oxide layer 124 and in direct contact with the buried oxide layer 124 and the lateral width of the double-sided clamping beam is parallel to the pair of meandering traces The interconnect structure 104 extends. In this embodiment, the oxide tab 119 electrically insulates the pair of turns in the bipolar electrode configuration along the lateral width of the cantilever beam between the pair of mesa structures 112, the pair of electrode leads 114 being separated by a patterned entity . In the illustrated embodiment, each electrode lead 114 is separated such that the beam configuration has an 8-shaped configuration of electrode leads 114.

Figure 35 is a plan view and cross-section of line AA of a compatible bipolar microdevice transfer head having a double-sided clamping beam including a pair of 矽 electrodes (having a single curved and mesa joint) in accordance with an embodiment of the present invention. Sectional side view. As shown, the tantalum electrode double-sided clamping beam can include a pair of electrode leads 114 extending from a meandering trace interconnect structure 104 (each electrode lead 114 having a single double bend 115) and by a mesa oxide joint 119 a separate pair of mesa structures 112 on the buried oxide layer 124 and in direct contact with the buried oxide layer 124. The lateral widths of the double-sided clamping beams are perpendicular to the pair of meandering traces. The structure 104 extends. In this embodiment, the oxide joint 119 electrically insulates the pair of tantalum electrodes in the bipolar electrode configuration along a lateral width of the double-sided clamping beam between the pair of mesa structures 112, the pair of electrode leads 114 The patterned entities are separated.

36 through 37 are lines AA of a compatible bipolar microdevice transfer head having a double-sided clamping beam including a pair of tantalum electrodes (with double bends and mesa joints) in accordance with an embodiment of the present invention. Plan view and cross section side view. As shown, the tantalum electrode double-sided clamping beam can include a pair of electrode leads 114 (each electrode lead 114 having a double bend 115) and a pair of mesa structures 112 separated by a mesa oxide joint 119, the mesa oxide The joint 119 is located on the buried oxide layer 124 and is in direct contact with the buried oxide layer 124. The lateral width of the double-sided clamping beam extends parallel to the pair of meander line interconnect structures 104. In this embodiment, the oxide joint 119 electrically insulates the pair of turns in the bipolar electrode configuration along the lateral width of the double-sided clamping beam between the pair of mesa structures 112. In the particular embodiment illustrated in Figure 36, the beam is in a W-shape configuration. In the particular embodiment illustrated in Figure 37, the beam is in an S-shape configuration.

In accordance with an embodiment of the present invention, the dielectric layer 118 or dielectric layer 126 covering the mesa structure 112 has a suitable thickness and dielectric constant for the clamping pressure required by the microdevice transfer head, and has sufficient dielectric strength to Not operating voltage collapses. Figure 38 is a flow chart illustrating a method of picking up and transferring a microdevice array from a carrier substrate to a receiving substrate in accordance with an embodiment of the present invention. At operation 3810, the compatible transfer head array is positioned over the array of micro devices on the carrier substrate. Figure 39 is a cross-sectional side view of an array of compatible transfer heads 102 over a microdevice array on a carrier substrate 200, in accordance with an embodiment of the present invention. At operation 3820, the micro device array contacts the compatible transfer head array. In an alternate embodiment, the compatible transfer head array is positioned above the micro device array with appropriate separation of the micro device air gaps, for example, 1 nm to 10 nm. The air gap does not significantly affect the clamping pressure. Figure 40 is a cross-sectional side view of an array of compatible transfer heads 102 of an array of contact microdevices 202 in accordance with an embodiment of the present invention. As shown, the pitch of the array of compatible transfer heads 102 is an integer multiple of the pitch of the array of micro devices 202. At operation 3830, a voltage is applied to the array of compatible transfer heads 102. A voltage can be applied from a working circuit system internal to the transfer head element 160 that is electrically coupled to the compatible transfer head array via 120. At operation 3840, the array of microdevices is picked up using a compatible array of transfer heads. Figure 41 is a cross-sectional side view of an array of compatible transfer heads 102 of an array of pick-up micro-devices 202 in accordance with an embodiment of the present invention. The microdevice array is then released onto the receiving substrate at operation 3850. For example, the receiving substrate can be, but is not limited to, a display substrate, an illumination substrate, a substrate having a functional device such as a transistor or an IC, or a substrate having a metal redistribution line. Figure 42 is a cross section of an array of micro devices 202 that are released onto the receiving substrate 300 in accordance with an embodiment of the present invention. Side view.

Although operation 3810 through operation 3850 have been illustrated in sequence in FIG. 38, it will be understood that the embodiments are not limited thereto and that additional operations may be performed to perform certain operations in a different order. For example, in one embodiment, an operation is performed to generate a phase change of the bonding layer connecting the micro device to the carrier substrate before or at the time of picking up the micro device. For example, the tie layer can have a liquidus temperature of less than 350 °C, or, more specifically, a liquidus temperature of less than 200 °C. The bonding layer may be formed of a material that is bonded to the carrier substrate, but may also be formed of a medium that can easily release the micro device. In an embodiment, the bonding layer is a material such as indium or an indium alloy. If a micro-device is used to pick up a portion of the bonding layer, additional operations can be performed to control the phase of the portion of the bonding layer during subsequent processing. For example, heat can be applied to the bonding layer from a heat source located within the transfer head element 160, the carrier substrate 200, and/or the receiving substrate 300.

Moreover, operation 3830 of applying a voltage to create a clamping pressure on the micro device can be performed variously. For example, a voltage can be applied before the micro device array contacts the compatible transfer head array, when the micro device contacts the compatible transfer head array, or after the micro device contacts the compatible transfer head array. It is also possible to apply a voltage before, during or after the phase change in the bonding layer.

The compatible transfer head 102 includes a bipolar germanium electrode that applies an alternating voltage across the pair of germanium electrodes in each compatible transfer head 102 such that a positive voltage is applied when a negative voltage is applied to a germanium electrode at a particular point To the other of the pair of electrodes, and vice versa, thereby generating a pick-up pressure. Release of the microdevice from the compatible transfer head 102 can be accomplished using a modified method that includes turning off the voltage source, varying the voltage across the pair of electrodes, and varying the AC voltage. Waveform and ground the voltage source. Release can also be accomplished by discharge associated with the microdevice on the receiving substrate.

In making use of the various aspects of the present invention, it will be apparent to those skilled in the art that combinations or variations of the above embodiments may be used to form compatible bipolar microdevice transfer heads and head arrays and for transferring microdevices and Micro device array. Although the present invention has been described in a language specific to the structure and/or method of operation, it is understood that the invention defined in the appended claims Rather, the specifics and acts of the disclosure are to be understood as a particularly preferred embodiment of the claimed invention.

112‧‧‧ countertop structure

114‧‧‧Electrode lead

116‧‧‧ trench

118‧‧‧ dielectric layer

119‧‧‧Oxide joint

120‧‧‧through hole

120A‧‧‧through opening

120B‧‧‧through opening

122‧‧‧ patterned conductive layer

123‧‧‧ patterned conductive layer

124‧‧‧buried oxide layer

130‧‧‧Base substrate

132‧‧‧ Passivation layer

133‧‧‧passivation layer

136‧‧‧ cavity

140‧‧‧矽

Claims (20)

A bipolar micro device transfer head array comprising: a base substrate; an electrostatic transfer head array, each electrostatic transfer head comprising a pair of germanium electrodes and a dielectric material covering a top surface of one of the pair of germanium electrodes, the pair The ruthenium electrode can be deflected into a cavity between the base substrate and the pair of ruthenium electrodes. The microdevice transfer head array of claim 1 wherein each pair of germanium electrodes is deflectable into the same cavity. The microdevice transfer head array of claim 2, wherein the cavity is located in the base substrate. The microdevice transfer head array of claim 1 wherein each pair of xenon electrodes is deflectable into a separate cavity. The microdevice transfer head array of claim 4, wherein each cavity is located in the base substrate. The micro device transfer head array of claim 1, wherein the electrostatic transfer head array comprises: a first electrode array electrically connected to a first bus bar interconnect; A second electrode array is electrically connected to a second bus bar interconnect structure. The micro device transfer head array of claim 6, wherein the electrostatic transfer head array comprises: a first plurality of trace interconnect structures electrically interconnecting the first tantalum electrode array and the first bus bar interconnect structure And a second plurality of trace interconnect structures electrically interconnecting the second drain electrode array and the second bus interconnect structure. The micro device transfer head array of claim 7, wherein the first and second plurality of trace interconnect structures are trace trace interconnect structures, and the first and second bus bar interconnect structures are connected to each other Even structure. The micro device transfer head array of claim 7, further comprising a first through hole and a second through hole, the first through hole extending through the first bus bar interconnection structure and the base substrate, the second A via extends through the second busbar interconnect structure and the base substrate. A compatible bipolar transfer head array comprising: a base substrate; a patterned germanium layer over the base substrate, the patterned germanium layer comprising a first germanium interconnect structure electrically connected to the first germanium interconnect a first germanium electrode array, a second germanium interconnect structure, and an electrical connection to the second interconnect a second electrode array of the structure, wherein each of the first electrode array and the second electrode array includes an electrode lead and a mesa structure, and each mesa structure protrudes from the first interconnect structure And a second 矽 interconnect structure, and each 矽 electrode is deflectable into a cavity between the base substrate and the 矽 electrode, wherein the first 矽 electrode array and the second 矽 electrode array are electrically insulated from each other And a dielectric layer covering a top surface of each mesa structure of the first tantalum electrode array and the second tantalum electrode array. The compatible bipolar transfer head array of claim 10, wherein each of the first tantalum electrode array and the second tantalum electrode array is deflectable into a cavity in the base substrate. The compatible bipolar transfer head array of claim 11, wherein the first tantalum electrode array and the second tantalum electrode array are deflectable into the cavity in the base substrate. The compatible bipolar transfer head array of claim 10, wherein the first tantalum electrode array and the second tantalum electrode array are formed across one of the first tantalum interconnect structure and the second tantalum interconnect structure Support beam array. The compatible bipolar transfer head array of claim 13 further comprising an oxide interface array between the second tantalum electrode arrays of the first tantalum electrode array. The compatible bipolar transfer head array of claim 13 wherein the support beams comprise a bend. A compatible bipolar transfer head array comprising: a base substrate; an insulating layer on the base substrate; a patterned device layer on the insulating layer, the patterned device layer comprising: a first trace a line interconnect structure integrally formed with a first electrode array; a second trace interconnect structure integrally formed with a second electrode array; wherein each of the first electrode array and the second electrode array An electrode includes a mesa structure protruding above the first trace interconnect structure and the second trace interconnect structure; wherein the first electrode array and the second electrode array are aligned and electrically insulated from each other, and the first An electrode array and each electrode of the second electrode array are deflectable toward the base substrate; and a dielectric layer covering a top surface of each of the first electrode array and the second electrode array. The compatible bipolar transfer head array of claim 16, wherein the first trace interconnect structure and the second trace interconnect structure comprise the compatibility of the first electrode array and the second electrode array One of the working areas of the bipolar transfer head array. The compatible bipolar transfer head array of claim 16, wherein the first electrode array and the second electrode array are formed across the first trace interconnect structure and the second trace interconnect structure A support beam array. The compatible bipolar transfer head array of claim 18, further comprising a dielectric junction array between the first electrode array and the second electrode array. The compatible bipolar transfer head array of claim 18, wherein the support beams comprise bends.