TWI533362B - Compliant monopolar micro device transfer head with silicon electrode - Google Patents

Description

Compliance single-pole micro device transmission head with 矽 electrode

This invention relates to microdevices. More particularly, embodiments of the present invention relate to a method of compliant microdevice transfer heads and transferring one or more micro devices to a receiving substrate.

Integration and packaging issues are microdevices such as radio frequency (RF) microelectromechanical systems (MEMS) microswitches, light-emitting diode (LED) display systems, and MEMS or quartz based oscillators. One of the main obstacles to commercialization.

Conventional techniques for transmission devices include transmission by wafer bonding from a transfer wafer to a receiving wafer. One such implementation is "direct printing," which involves a bonding step of the device array from the transfer wafer to the receiving wafer, followed by removal of the transfer wafer. Another such embodiment is "transfer printing" involving two joining/separating steps. In transport printing, the transport wafer can pick up an array of devices from the donor wafer and then bond the device array to the receiving wafer, then remove the transfer wafer.

Some printing process variants have been developed, during which the transfer process The device can be selectively joined and separated. In both conventional direct print and transfer printing techniques and variations of direct print and transfer printing techniques, the transfer wafer is separated from the device after bonding the device to the receiving wafer. In addition, the entire transfer wafer with the array of devices is involved in the transfer process.

The present invention discloses a compliant monopolar micro device transfer head and head array, and a method of transmitting one or more micro devices to a receiving substrate. For example, the receiving substrate can be, but is not limited to, a display substrate, an illumination substrate, a substrate having a functional device such as a transistor or an integrated circuit (IC), or a substrate having a metal redistribution line.

In an embodiment, the compliant microdevice transport head array includes a base substrate and a patterned germanium layer over the base substrate. For example, the base substrate can be a (100) block-shaped germanium substrate. The patterned germanium layer includes a germanium interconnect structure and a tantalum electrode array electrically connected to the germanium interconnect structure. Each of the electrodes includes an electrode lead and a mesa structure that extends above the tantalum interconnect structure. Each of the electrodes can also be deflected into the cavity between the base substrate and the ruthenium electrode. For example, one or more cavities can be formed in the base substrate. In an embodiment, each of the turns electrodes can be deflected into separate chambers in the base substrate. In an embodiment, each of the turns electrodes can be deflected into the same cavity in the base substrate. The cavity can also surround the end of the interconnect structure. The cavity can also surround the ends of the plurality of interconnect structures. A dielectric layer such as cerium oxide, cerium oxide, aluminum oxide or cerium oxide covers the top surface of each mesa structure. A buried oxide layer may be formed between the patterned germanium layer and the base substrate. In an embodiment, the via extends through the base substrate and the buried ceria layer, and is electrically connected from the rear side of the base substrate to the patterned germanium layer and the germanium interconnect structure and the germanium electrode array.

In an embodiment, the first tantalum electrode array extends from a first side of the tantalum interconnect structure and the second tantalum electrode array extends from a second side of the tantalum interconnect structure opposite the first side. In this embodiment, the first and second electrode arrays can be deflected into the same cavity in the base substrate, the cavity surrounding the one end of the interconnect structure or the first and second electrode arrays can be deflected into the base substrate. Inside the cavity.

In an embodiment, the patterned germanium layer further includes a second germanium interconnect structure and a second germanium electrode array electrically coupled to the second germanium interconnect structure. Each of the second electrodes in the second array includes an electrode lead and a mesa structure that protrudes over the second tantalum interconnect structure. Each of the electrodes in the second array can also be deflected into the cavity between the base substrate and the ruthenium electrode. A dielectric layer such as hafnium oxide, hafnium oxide, aluminum oxide or hafnium oxide covers the top surface of each mesa structure in the second array. In an embodiment, each of the first and second tantalum electrode arrays can be deflected into a cavity in the base substrate. For example, the first and second tantalum electrode arrays can be deflected into the same cavity or separation chamber in the base substrate.

In an embodiment, the buried ruthenium dioxide layer is between the patterned ruthenium layer and the base substrate. The first via extends through the base substrate and the buried ceria layer from the rear side of the base substrate to the patterned germanium layer and is electrically connected to the germanium interconnect structure and the germanium electrode array. The second via extends through the base substrate and the buried ceria layer from the rear side of the base substrate to the patterned germanium layer and is electrically connected to the second germanium interconnect structure and the second germanium electrode array. The via may extend through the patterned germanium layer or terminate in a bottom surface of the patterned germanium layer.

In an embodiment, the patterned germanium layer includes a first germanium interconnect structure and a second germanium interconnect structure electrically connected to the first germanium interconnect structure and a germanium electrode, the germanium electrode including the interconnected from the first germanium a first electrode lead extending from the structure and from the A second electrode lead extending from the second interconnect structure, wherein the first and second electrode leads are joined at the mesa structure. In an embodiment, the via extends through the base substrate and the buried ceria layer from the rear side of the base substrate to the patterned germanium layer, wherein the via and the first and second germanium interconnect structures and the germanium electrode array Electrical connection. The first and second electrode leads can be straight or can include, for example, one or more bends in the tantalum electrode lead of the tantalum electrode. In an embodiment, the tantalum electrode array is formed across an array of support beams between the first and second tantalum interconnect structures. For example, the longitudinal length of the array of support beams can be perpendicular to the tantalum interconnect structure. In an embodiment, the tantalum electrode array forms an array of cantilever beams between the first and second tantalum interconnect structures. For example, the longitudinal length of the cantilever beam array can be parallel to the tantalum interconnect structure.

A dielectric layer covering the top surface of each of the array and the second array of the second array may be formed of a material such as hafnium oxide, hafnium oxide, aluminum oxide, and hafnium oxide. In some embodiments, the first dielectric layer is under the dielectric layer covering the top surface of each mesa structure in the array and the second array. The dielectric layer can have a higher dielectric constant or dielectric breakdown strength than the first dielectric layer.

In an embodiment, a method of forming a compliant microdevice transfer head array includes the steps of etching a top germanium layer of a stack of insulators on an insulator to form a germanium electrode array electrically coupled to the germanium interconnect structure, wherein each germanium electrode includes an electrode A lead and mesa structure extending over the interconnect structure. A dielectric layer is then formed over the tantalum electrode array and one or more cavities are etched into the base substrate just below the tantalum electrode array such that each tantalum electrode in the tantalum electrode array can be deflected to one or more Inside the cavity. For example, etching of one or more cavities can be accomplished using a fluorinated plasma of SF ₆ or XeF ₂ . In an embodiment, the separate chambers are etched just below each of the ruthenium electrodes in the base substrate. In an embodiment, a single cavity is etched just below each germanium electrode in the base substrate. A single cavity can also be etched into the base substrate such that the single cavity surrounds one end of the interconnect structure.

Etching the top layer of germanium exposes the buried oxide layer. The formation of the dielectric layer can be accomplished using a variety of techniques. In some embodiments, the dielectric layer comprises thermal oxidation of a tantalum electrode array. In some embodiments, a patterned layer is formed over the buried oxide layer and over the dielectric layer after forming the dielectric layer, and the buried oxide layer is etched using the patterned layer to expose a portion of the base substrate . The dielectric layer can be used as an etch mask when one or more cavities are etched just below the ruthenium electrode array in the base substrate.

The back side via opening may be etched through the base substrate just below the germanium interconnect structure, and a passivation layer may be formed inside the back side via opening. In an embodiment, the passivation layer is formed inside the via opening by thermally oxidizing the base substrate while thermally oxidizing the tantalum electrode array to form a dielectric layer. The patterned conductive layer can be formed in the via opening through electrical contact, for example, by shadow mask deposition to make electrical contact with the germanium interconnect structure.

In an embodiment, the dielectric layer is etched to expose a portion of the germanium interconnect structure while etching through the buried oxide layer to expose portions of the base substrate. The upper via opening is then etched through the exposed portion of the germanium interconnect structure and the buried oxide layer. A patterned conductive layer can then be formed inside the upper via opening to make electrical contact with the germanium interconnect structure.

In an embodiment, the dielectric layer is etched to expose each of the terrace surface structures while etching through the buried oxide layer to expose portions of the base substrate. A second dielectric layer can then be formed over each of the mesa structures. In an embodiment, this can be accomplished by blanket deposition of a second dielectric layer followed by removal of a portion of the second dielectric layer. In some embodiments, blanket deposition can be accomplished by atomic layer deposition. In an embodiment, the dielectric layer may be additionally etched to expose a portion of the germanium interconnect structure, followed by etching the first upper via opening through the exposed portion of the germanium interconnect structure and the buried oxide layer, and on the upper side A patterned conductive layer is formed inside the aperture opening to make electrical contact with the germanium interconnect structure. The second dielectric layer formed over each of the mesa structures and the conductive layer formed inside the upper via opening are also useful as an etch mask when etching one or more cavities.

100‧‧‧Blocked 矽 substrate/compliant monopolar micro device transfer head array

104‧‧‧矽 Trace interconnect structure

106‧‧‧ Bus Bar Interconnect Structure

110‧‧‧矽 electrode

112‧‧‧ countertop structure

114‧‧‧Electrode lead

115‧‧‧Bend

116‧‧‧ trench

118‧‧‧ dielectric layer

120‧‧‧through hole

120A‧‧‧through opening

120B‧‧‧through opening

122‧‧‧ Conductive layer

123‧‧‧ Conductive layer

124‧‧‧buried oxide layer

126‧‧‧ dielectric layer

130‧‧‧Base substrate

132‧‧‧ Passivation layer

133‧‧‧passivation layer

136‧‧‧ cavity

137‧‧‧groove area

140‧‧‧矽

142‧‧‧mask layer

144‧‧ Island

160‧‧‧Transport head assembly

200‧‧‧ Carrier substrate

202‧‧‧Microdevice

300‧‧‧ receiving substrate

4210‧‧‧ operation

4220‧‧‧ operation

4230‧‧‧ operation

4240‧‧‧ operation

4250‧‧‧ operation

1A is a plan view of an array of compliant single-pole microdevice transfer heads for one-sided clamping cantilever beams in accordance with an embodiment of the present invention.

1B is a plan view of a compliant single pole microdevice transfer head having a pair of one-sided clamping cantilever beams in accordance with an embodiment of the present invention.

1C is a cross-sectional side view of the transverse line C-C of the compliant monopolar microdevice transfer head illustrated in FIG. 1B, in accordance with an embodiment of the present invention.

1D is a cross-sectional side view of the longitudinal line D-D of the compliant monopole microdevice transfer head illustrated in FIG. 1B, in accordance with an embodiment of the present invention.

1E is a plan view of an array of compliant single-pole microdevice transfer heads for one-sided clamping cantilever beams in accordance with an embodiment of the present invention.

2A through 2B are combined plan views and combined cross-sectional side views of lines VV, WW, XX, YY, and ZZ of Fig. 1A, illustrating a unipolar microdevice transfer head and a cross-sectional view thereof, in accordance with an embodiment of the present invention. The rear side through hole is open.

3A-3B are compliant monopoles in accordance with an embodiment of the present invention A combined plan view and a combined cross-sectional side view of the microdevice transfer head and the upper through hole opening and the rear side through hole opening.

4A through 4B are combined plan views and combined cross-sectional side views of a compliant single pole micro device transfer head and an upper through hole opening and a rear side through hole opening, in accordance with an embodiment of the present invention.

5A through 15B illustrate a method of forming a compliant monopolar micro device transfer head and a rear side via opening in accordance with an embodiment of the present invention.

Figure 16A is a plan view of a compliant single pole microdevice transfer head array of a double side clamped support beam in accordance with an embodiment of the present invention.

Figure 16B is a plan view of a compliant single pole microdevice transfer head having a double clamping support beam in accordance with an embodiment of the present invention.

Figure 16C is a cross-sectional side view of the transverse line C-C of the compliant monopole microdevice transfer head illustrated in Figure 16B, in accordance with an embodiment of the present invention.

Figure 16D is a cross-sectional side view of the longitudinal line D-D of the compliant single pole microdevice transfer head illustrated in Figure 16B, in accordance with an embodiment of the present invention.

17A to 28B illustrate a method of forming a compliant single-pole micro device transfer head including a double-sided clamping support beam and an upper side through hole opening and a rear side through hole opening according to an embodiment of the present invention. .

29A through 34B illustrate a method of forming a compliant single-pole microdevice transfer head including a double-sided clamping support beam and a deposited dielectric layer and an upper via opening, in accordance with an embodiment of the present invention. And the rear side through hole opening.

Figure 35 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having a cantilever beam, in accordance with an embodiment of the present invention. Figure.

Figure 36 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having cantilever beams and separate electrode leads in accordance with an embodiment of the present invention.

Figure 37 is a plan view and a cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having a double sided clamping beam in accordance with an embodiment of the present invention.

Figure 38 is a plan view and cross-sectional side view of line A-A of a compliant single pole microdevice transfer head having a support beam structure and separate curved electrode leads in accordance with an embodiment of the present invention.

Figure 39 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having a support beam structure and a plurality of bends in accordance with an embodiment of the present invention.

Figure 40 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having a support beam structure and a plurality of bends in accordance with an embodiment of the present invention.

Figure 41 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having a support beam structure and a plurality of bends in accordance with an embodiment of the present invention.

Figure 42 is a flow chart illustrating a method of picking up and transporting a microdevice array from a carrier substrate to a receiving substrate in accordance with an embodiment of the present invention.

Figure 43 is a cross-sectional side view of a compliant monopolar microdevice transfer head array over a microdevice array on a carrier substrate in accordance with an embodiment of the present invention.

Figure 44 is a cross-sectional side view of a compliant single pole micro device transfer head array in contact with a micro device array in accordance with an embodiment of the present invention.

Figure 45 is a cross-sectional side view of a compliant single pole micro device transfer head array for picking up a micro device array in accordance with an embodiment of the present invention.

Figure 46 is a cross-sectional side view of an array of micro devices released onto a receiving substrate in accordance with an embodiment of the present invention.

Embodiments of the present invention describe a method of compliant monopolar micro device transfer heads and head arrays, and a transfer micro device and micro device array to a receiving substrate. For example, a compliant monopolar micro device transfer head and head array can be used to transfer micro devices such as, but not limited to, diodes, LEDs, transistors, ICs, and MEMS from a carrier substrate to a receiving substrate, such as but not It is limited to a display substrate, an illumination substrate, and a substrate having a functional device such as a transistor or an integrated circuit (IC) or a substrate having a metal redistribution line.

In various embodiments, the description is made with reference to the drawings. However, some embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as, In other instances, well-known semiconductor processes and fabrication techniques have not been described in detail in order to not unnecessarily obscure the invention. The specific features, structures, configurations, or characteristics described in connection with the embodiments are included in the description of the embodiments. Therefore, the appearance of the phrase "in one embodiment", "embodiment", etc. throughout the specification is not necessarily Representative of the same embodiment of the invention. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

The terms "above", "to", "between" and "above" as used herein may denote the relative position of one layer relative to the other. A layer "on" or "above" another layer or "on" another layer may be in direct contact with the other layer or may have one or more intervening layers. A layer "between" the layers may be in direct contact with the layers or may have one or more intervening layers.

The term "micro" device or "micro" LED structure as used herein may refer to a descriptive size of certain devices or structures in accordance with embodiments of the present invention. As used herein, the term "micro" device or structure means of the order of magnitude of 1 to 100 μm. However, it will be understood that embodiments of the invention are not necessarily limited thereto, and that certain aspects of the embodiments may be suitable for larger or possibly smaller orders of magnitude.

In one aspect, without being limited to a particular theory, embodiments of the present invention describe microdevice transfer heads and head arrays that operate according to the principle of electrostatic chucks, using an attractive charge of opposite charges Micro device. In accordance with an embodiment of the invention, a pull-in voltage is applied to the micro device transfer head to create a clamping pressure and pick up the micro device on the micro device. For example, the transfer head can include a monopolar electrode configuration.

In one aspect, embodiments of the present invention describe a compliant monopolar micro device transfer head and a method of transmission in which unidirectional micro-device transfer head arrays are energized and micro-compared to non-compliant transfer head arrays Improved contact of the array of devices. The compliant monopolar microdevice transfer head includes a ruthenium electrode that can be deflected into a cavity between the base substrate and the ruthenium electrode. In the application, when When the monopole micro device transfer head array is lowered onto the micro device array, the deflectable xenon electrode associated with the higher or contaminated micro device can deflect more than the xenon electrode associated with the shorter micro device on the carrier substrate. . In this way, the compliant monopolar microdevice transfer head can compensate for variations in the height of the micro device. Compensating for height variations can result in reduced compression forces applied to certain microdevices, resulting in physical integrity of the protection microdevice and the array of transport heads. Compensating for height variations also helps each compliant transfer head to make contact with each micro device and to ensure that each desired micro device is picked up. Without the compliant nature of the microdevice transfer head, the irregular microdevice height or particles on the top surface of the individual microdevices may prevent the remaining transport heads from coming into contact with the remaining microdevices in the array. Thus, an air gap can be formed between their transfer heads and the micro device. Because of this air gap, it is possible that the target applied voltage does not produce a sufficient clamping pressure against the air gap, resulting in an incomplete pick-up process.

In another aspect, embodiments of the present invention describe a compliant unipolar microdevice formed from a commercially available silicon-on-insulator (SOI) substrate including a base substrate, a buried oxide layer, and a top germanium layer. The way the head array is transmitted. In this embodiment, the germanium interconnect structure and the germanium electrode array are formed by the top germanium layer of the SOI substrate. In an embodiment, the monopolar electrostatic transfer head includes a germanium electrode comprising a mesa structure and one or more electrode leads. A mesa structure for the tantalum electrode extends over the tantalum interconnect structure to provide a local contact point to pick up a particular micro device during the picking operation. In this way, it is not necessary to form a patterned metal electrode. It has been observed that when the metal electrode and electrode lead are patterned using a negative photoresist, for example, it may be difficult to control the exposure of the photoresist at different depths (eg, along both the top and bottom sidewalls of the mesa structure). Stripping of the patterned metal layer has also been observed during photoresist removal Falling, potentially affecting the operability of the transport head. According to an embodiment of the invention, it is not necessary to form a patterned metal electrode over the mesa structure. In contrast, the projecting profile of the mesa structure is formed by patterning the erbium electrode to include a raised portion corresponding to the mesa structure that extends away from the base substrate and over the 矽 interconnect structure.

The tantalum electrode prepared in accordance with an embodiment of the present invention may comprise an integrally formed mesa structure that is substantially higher than a mesa structure having a patterned metal electrode that is not integrally formed. Photolithography can limit the patterned metal electrode structure to a height of 5 μm to 10 μm, whereas the tantalum electrode mesa structure can reach 20 μm to 30 μm or higher. Higher electrode configurations can also provide greater clearance for contaminant particles and reduce spurious effects on non-target microdevices. The tantalum electrode having an integrally formed mesa structure may be more robust when compared to metallized mesa structures, for surface contamination and errors in the planar alignment of the microdevice carrier with respect to the microdevice carrier substrate.

In another aspect, embodiments of the present invention describe a manner in which a microdevice transport head array is formed from a commercially available insulator-on-insulator (SOI) substrate that allows for a processing sequence with minimal processing steps. The processing sequence does not require metal deposition and patterning steps to form the metal electrode, which reduces heat treatment limitations and allows the formation of dielectric and passivation layers by high temperature thermal oxidation, resulting in reduced deposition and patterning operations. A processing sequence in accordance with embodiments of the present invention can incorporate simultaneous etching or oxidation operations of different features to reduce the number of masks required during processing.

In another aspect, embodiments of the present invention describe a transmission head and an array of transmission heads, the transmission head and the array of transmission heads including extending through the base substrate from the bottom The back side of the base substrate is to the through hole of the patterned ruthenium layer for connecting the working circuit of the electrode and the transfer head element. The processing sequence in accordance with an embodiment of the present invention also imparts passivation that extends through the via of the base substrate using high temperature thermal oxidation growth.

In yet another aspect, embodiments of the present invention describe a manner for mass transmitting an array of pre-fabricated microdevices using a compliant transport head array. For example, pre-fabricated microdevices may have specific functions such as, but not limited to, LEDs for illumination, germanium ICs for logic and memory, and gallium arsenide (GaAs) circuits for radio frequency (RF) communication. . In some embodiments, an array of micro LED devices that may be used for picking is described as having a pitch of 10 [mu]m by 10 [mu]m, or a pitch of 5 [mu]m by 5 [mu]m. At these densities, a 6-inch substrate, for example, can accommodate approximately 165 million micro-LED devices having a pitch of 10 μm by 10 μm, or approximately 660 million micro-LED devices having a pitch of 5 μm by 5 μm. A transfer tool comprising a compliant transfer head array that matches an integer multiple of the pitch of the corresponding array of micro LED devices can be used to pick up and transport the array of micro LED devices to the receiving substrate. In this way, it is possible to integrate and assemble micro LED devices to different types of integrated systems at high transmission rates, including substrates of any size ranging from microdisplays to large area displays. For example, a 1 cm by 1 cm array of micro device transfer heads can pick up and transport more than 100,000 micro devices, with larger micro device transfer head arrays capable of transmitting more micro devices.

Referring now to FIG. 1A, a plan view of a portion of a single pole microdevice transfer head array of single side clamp cantilever beams is provided, and the plan view includes views at different depths. In the particular embodiment illustrated, the shaded area illustrates the tantalum electrode and the tantalum interconnect as viewed from the top surface of the array of unidirectional microdevice transfer head arrays. The layout of the structure. The darker shading illustrates the rear side via connection as viewed from the rear side surface of the array of unidirectional microdevice transfer heads. In this way, the plan view provides details about the structure that has been formed by the sides of the SOI wafer.

As shown, the compliant monopolar microdevice transfer head array 100 includes a compliant transfer head array, each of which includes a tantalum electrode connected to the arrangement of the meander trace interconnect structure 104 and the busbar interconnect structure 106. 110. As shown, the busbar interconnect structure 106 can be formed around or outside the perimeter of the work area including the array of compliant transport heads that conform to the array of transport heads. In an embodiment, each compliant transfer head includes a germanium electrode 110, wherein each germanium electrode 110 includes a mesa structure 112 and an electrode lead 114 connected to the germanium interconnect structure 104. As shown, each compliant transfer head is clamped to the meander line interconnect structure 104 in the form of a one-sided clamp cantilever beam. In the illustrated embodiment, the mesa structure array 112 in the unipolar microdevice transfer head array 100 is arranged at approximately the same pitch as the micro device to be picked up, for example, 10 [mu]m by 10 [mu]m, or 5 [mu]m by 5 [mu]m.

In an embodiment, one or more vias 120 are formed through the back side of the base substrate to the patterned germanium layer to make contact with the interconnect structure 106 to electrically connect the drain electrode 110 with the working circuitry of the transfer head element. . In the embodiment illustrated in FIG. 1A, the interconnect structure 106 on the left side of the drawing can be connected to the first voltage source V _A , and the interconnect structure 106 on the right side of the drawing can be connected to the second voltage source V _B , or connected To the first voltage source V _A . When each of the transfer heads is operable as a unipolar transfer head, the voltage source V _A and the voltage source V _B can simultaneously apply the same voltage such that each of the germanium electrodes has the same voltage.

1B is a pair of single side clips in accordance with an embodiment of the present invention A plan view of the compliant single-pole microdevice transfer head of the cantilever beam. In the particular embodiment illustrated, the erbium electrode 110 is clamped to the opposite side of the erbium trace interconnect structure 104. For purposes of clarity of illustration, only a single pair of transfer heads are illustrated in FIG. 1B extending from opposite sides of the germanium interconnect structure 104, although an array of interconnect structures may be from one of the interconnect structures 104 in accordance with an embodiment of the present invention. Extending side or side. 1C is a cross-sectional side view of the transverse line C-C of the compliant monopolar microdevice transfer head illustrated in FIG. 1B, in accordance with an embodiment of the present invention. In the embodiment illustrated in FIG. 1C, the first tantalum electrode array 110 extends from one side of the tantalum interconnect structure and the second tantalum electrode array 110 extends from the opposite side of the tantalum interconnect structure 104. In another embodiment, the erbium electrode array 110 extends only from one side of the erbium interconnect structure 104. 1D is a cross-sectional side view of the longitudinal line D-D of the compliant monopole microdevice transfer head illustrated in FIG. 1B, in accordance with an embodiment of the present invention. As illustrated in FIGS. 1C-1D, one or more cavities 136 may be formed under the ruthenium electrode array 110 in the base substrate 130 such that the 矽 electrode mesa structure 112 and the leads 114 are in the one or more cavities 136. The upper portion extends and can be deflected into the one or more cavities 136. In an embodiment, the cavity 136 is a separate cavity on the opposite side of the germanium interconnect structure 104. In an embodiment, the cavities 136 are the same cavity. For example, the cavity 136 can surround the germanium interconnect structure 104 and be located below the first and second germanium electrode arrays 110. Trench 116 may also be formed in the patterned germanium layer to define germanium electrode 110 and germanium interconnect structure 104, germanium interconnect structure 106, as described in more detail below. If the cavity 136 does not surround the end of the germanium interconnect structure 104, the trench 116 may also be formed in the patterned germanium layer at the end of the germanium interconnect structure 104.

1E is a plan view of a compliant single-pole microdevice transfer head array of a one-sided clamp cantilever beam in accordance with an embodiment of the present invention. Figure 1E is similar to the first 1A, one of the differences is that the tantalum electrode array 110 in FIG. 1A extends away from the tantalum interconnect structure 104 toward the other tantalum interconnect structure 104. In the embodiment illustrated in FIG. 1e, the tantalum electrode array 110 extends away from the tantalum interconnect structure 104 toward the other tantalum electrode array 110. In this embodiment, a single cavity 136 can occupy the space between the opposing tantalum electrode arrays 110, or the trenches 116 can be formed in the space between the opposing tantalum electrode arrays 110.

Referring now to FIGS. 2A-2B, 3A-3B, and 4A-4B, the figures together illustrate various different compliant monopole head array configurations in accordance with embodiments of the present invention. It will be understood that while the following variations are illustrated and described separately, the variations are not necessarily incompatible with each other, and in one or more embodiments the variations may be combined in any suitable manner.

2A through 2B are combined plan views and combined cross-sectional side views of lines V-V, W-W, X-X, Y-Y, and Z-Z along Figs. 1A and 1E, in accordance with an embodiment of the present invention. 3A to 3B and 4A to 4B are combined plan views and combined cross-sectional side views similar to those in the 2A to 2B drawings. The combined view does not represent an exact relative position for all of the different features of the illustration, in particular, the combined view combines the specific features at different locations previously identified in Figure 1A to more easily represent the specificity of the processing sequence Variety. For example, although a combined cross-sectional side view illustrates one via 120 corresponding to one germanium electrode 110, it is clear from FIG. 1A that one via 120 can be complex with one or more interconnect structures 104. The germanium electrodes 110 are electrically connected. As shown, the line W-W and the line Y-Y are along the through hole 120. As shown, the lines V-V and the lines Z-Z are along a side defining the germanium electrode 110 and the germanium interconnect structure 104, the germanium interconnect structure 106. Or more than one groove 116. As shown, line X-X passes through a monopole transfer head that includes a ruthenium electrode 110. Referring again to FIG. 1A, one or more cavities 136 can be formed around and below all of the germanium electrodes 110, and between the interconnect structure 104, the interconnect structure 106.

Referring again to FIGS. 2A-2B, the ruthenium electrode 110 includes a mesa structure 112 and an electrode lead 114, wherein the mesa structure 112 is a raised portion of the ruthenium electrode 110. Dielectric layer 118 covers the top surface of germanium electrode 110. In the illustrated embodiment, each cantilever compliant transfer head can be individually deflected into the cavity 136. The via opening 120A can extend through the base substrate 130 from the back side of the base substrate to the patterned germanium layer 140 where the interconnect structure 106 is located. In the particular embodiment illustrated in FIGS. 2A-2B, the via opening 120A extends through the buried oxide layer 124 and terminates at the bottom surface of the patterned germanium layer 140 where the interconnect structure 106 is positioned. A passivation layer 132 is formed on the rear side of the base substrate 130, and a passivation layer 133 is formed on a side surface inside the via opening 120A. When the base substrate is formed of tantalum, the passivation layer 132 and the passivation layer 133 insulate the electrical short between the vias 120. The buried oxide layer 124 also insulates the tantalum electrode 110 from the electrical short between the interconnect structures 104,106.

The through holes 120 illustrated in FIGS. 2A-2B extend through the base substrate 130 from the rear side of the base substrate to the patterned ruthenium layer 140. In an embodiment, the vias 120 contact one or more of the bus bar interconnect structures 106 in the patterned germanium layer 140. In other embodiments, the vias 120 may contact other features or interconnect structures in the patterned germanium layer 140. The via 120 along the line WW can be electrically connected to the first interconnect structure 106, the first interconnect structure 106 is connected to the first voltage source V _A , and the via 120 along the line YY can be electrically connected to A second interconnect structure 106 is coupled to the second voltage source V _B . In an embodiment, the vias 120 along the line WW and along line YY are connected to the same voltage source. In the particular embodiment illustrated, via opening 120A extends through buried oxide layer 124 and terminates at the bottom surface of interconnect structure 106. The passivation layer 132 is formed on the rear side of the base substrate 130 and the side surface inside the via opening 120A. Conductive layer 122 is formed on passivation layer 133 and in electrical contact with the bottom surface of interconnect structure 106. In the particular embodiment illustrated, the conductive layer 122 does not completely fill the via opening 120A, and the conductive layer 122 is physically and electrically separated to prevent vias connected to different voltage sources V _A , V _B . Short circuit between 120. The conductive layer 122 can span the two via holes 120 on the left side of FIG. 1A, and the conductive layer 122 is also electrically and physically separated from the via hole 120 along the line YY on the right side of FIG. In an embodiment, the vias 120 electrically connected to the same voltage source may or may not be physically and electrically connected. In the embodiment, the structures illustrated in FIGS. 2A to 2B are formed using a total of six masks.

3A through 3B are combined plan views and combined cross-sectional side views of a compliant single pole micro device transfer head, an upper side through hole opening, and a rear side through hole opening, in accordance with an embodiment of the present invention. As shown, in one embodiment, an upper through hole opening 120B may be formed over the rear side through hole opening 120A to form a through hole 120. As will be apparent from the description below, upper via opening 120B can be formed to make electrical contact with germanium interconnect structure 106 and to form openings through buried oxide layer 124 without the challenges associated with lithography, The passivation layer 133 along the sidewalls of the via opening 120A is not adversely affected. Conductive layer 123 may optionally be formed over the exposed top surface of germanium interconnect structure 106 and inside the inner surface of germanium interconnect structure 106. In this way, at the top of the interconnect structure 106 The partial formation of the conductive layer 123 over the surface can provide a larger surface area for ohmic contact with the germanium interconnect structure 106. Since the germanium interconnect structure 106 is closer to the top surface of the SOI structure than the back side surface of the SOI structure, in accordance with some embodiments, the interconnect structure 106 is over the top surface of the SOI structure from the back surface of the SOI structure. Forming the conductive layer 123 inside the inner surface may be more efficient. The conductive layer 123 may be formed of the same or different material as the conductive layer 122. The conductive layer 122 and the conductive layer 123 may form a continuous conductive layer along a side surface of the via 120. In the embodiment, the structures illustrated in FIGS. 3A to 3B are formed using a total of eight masks.

4A through 4B are combined plan views and combined cross-sectional side views of a compliant monopolar microdevice transfer head including a deposited dielectric layer 126 and an upper via opening, in accordance with an embodiment of the present invention. And the rear side through hole opening. It should be understood that although the deposition dielectric layer 126 and the upper side via opening and the back side via opening are collectively illustrated in FIGS. 4A-4B, the embodiment of the present invention is not limited thereto, and deposition is not required. The electrical layer 126 is along with the upper through hole opening and the rear side through hole opening. As shown, in one embodiment, the dielectric layer 118 can be partially or completely removed. In the particular embodiment illustrated in FIGS. 4A-4B, dielectric layer 118 is removed from mesa structure 112. A second dielectric layer 126 is formed over the top surface of the mesa structure 112 and over the remaining profile of the transfer head array, and the second dielectric layer 126 can include portions of the dielectric layer 118. The dielectric layer 126 may also cover any of the upper via opening 120B and the corresponding conductive layer 123, and the dielectric layer 126 may partially or completely fill the upper via opening 120B inside the germanium interconnect structure 106. In an embodiment, dielectric layer 126 has a higher dielectric constant and/or dielectric breakdown strength than dielectric layer 118. In an embodiment, the dielectric layer 118 is thermally grown SiO ₂ and the dielectric layer 126 is atomic layer deposition (ALD) SiO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ or RuO ₂ . It will be understood that although FIGS. 4A-4B illustrate variants of FIGS. 3A-3B, the features of dielectric layer 126 may be combined with the embodiments illustrated in FIGS. 2A-2B. In the embodiment, a structure illustrated in FIGS. 4A to 4B is formed using a total of nine masks.

5A through 15B illustrate a method of forming a compliant monopolar micro device transfer head and a rear side via opening in accordance with an embodiment of the present invention. Initially, the processing sequence can begin with a commercially available SOI substrate, as illustrated in Figures 5A-5B. The SOI substrate may include a base substrate 130, a top end layer 140, a buried oxide layer 124 between the base substrate and the top end layer, and a back side passivation layer 132. In an embodiment, the base substrate is a (100) 矽 processed wafer having a thickness of 500 μ n +/- 50 μm, the buried oxide layer 124 is 1 μm +/- 0.1 μm thick and the top ruthenium layer is 7 μm to 20 μm +/- 0.5 μm. thick. The top ruthenium layer can also be doped to improve conductivity. For example, a phosphorus-containing dopant concentration of about 10 ¹⁷ cm ^-3 produces a resistivity of less than 0.1 ohm-cm. In an embodiment, the backside passivation layer 132 is a thermal oxide having a thickness of up to about 2 [mu]m thick that is close to the upper limit of thermal oxidation of the ruthenium.

A mask layer 142 can then be formed over the top ruthenium layer 140, as illustrated in Figures 6A-6B. The mask layer 142 may be deposited or alternatively thermally grown from the top ruthenium layer 140. In an embodiment, the mask layer 142 is a thermally grown SiO ₂ layer having a thickness of about 0.1 μm. In an embodiment, when the mask layer 142 is thermally grown SiO ₂ , the mask layer 142 has a thickness that is significantly less than the thickness of the buried oxide (SiO ₂ ) layer 124 during removal of the patterned mask layer. The structural stability of the partially patterned SOI structure is maintained.

Referring to Figures 7A through 7B, mask layer 142 is then patterned to form island array 144, which will correspond to the mesa structure of the germanium electrode. In an embodiment, the mask layer is a thermally grown SiO ₂ layer and is formed by coating a positive photoresist, exposing with a potassium hydroxide (KOH) developer, and removing the undeveloped regions of the photoresist. Island 144. Subsequent use such as ion milling, plasma etching, reactive ion etching (RIE) or reactive ion beam etching (RIBE), electron cyclotron resonance (ECR) or inductively coupled plasma ( A suitable technique for inductively coupled plasma (ICP) dry etches the mask layer 142 to form islands 144, terminating on the germanium layer 140. If required a high degree of anisotropic etching may be used such as the use of CF _4, SF ₆ or NF ₃ plasma etchant in a dry plasma etching techniques. The patterned photoresist is then removed by O ₂ ashing followed by piranha etching to produce the structures illustrated in Figures 7A-7B.

In an embodiment, the back side via opening 120A is subsequently formed in the SOI substrate. Initially, as illustrated in FIGS. 8A-8B, the rear via opening is formed through the backside passivation layer 132 and the base substrate 130, terminating on the buried oxide layer 124. In an embodiment, 8A through 8B are formed by applying a patterned positive photoresist onto the backside passivation layer 132, followed by etching the exposed passivation layer 132 and the dry reactive ion etching (DRIE) base substrate 130. The rear side via opening 120A illustrated in the figure terminates on the buried oxide layer 124. The base substrate 130 may alternatively be etched using a wet etchant such as KOH. However, the KOH wet etchant preferentially etches germanium in the (100) plane and can produce an anisotropic V etch with tapered sidewalls. A DRIE etch can be selected for the more vertical sidewalls in the backside via opening 120A. After etching the base substrate 130, the patterned positive photoresist can be removed by O ₂ ashing followed by piranha etching to produce a structure as illustrated in FIGS. 8A-8B.

Referring to Figures 9A through 10B, the germanium electrode 110 and interconnect structures 104, 106 are patterned with a two-part etch sequence. First, as illustrated in FIGS. 9A-9B, the top germanium layer 140 is partially etched away to define the pattern of the germanium electrode 110 and interconnect structures 104,106. In an embodiment, this can be accomplished using a thin patterned positive photoresist, which is etched approximately 5 [mu]m from a 7 [mu]m to 10 [mu]m thick top germanium layer 140 in a timed etch. The patterned positive photoresist can be removed using O ₂ ashing followed by piranha etching. In accordance with an embodiment of the present invention, the opening in photoresist 111 (illustrated only in FIG. 9A) corresponds to the size of trench 116 used to define germanium electrode 110 and interconnect structures 104,106. As shown, the photoresist 121 can overlap the islands 144 that define the mesa structure 112. In this manner, the islands 144 in the patterned hard mask layer 142 can be used to form the tantalum electrode mesa structure 112, which has a higher resolution than the photoresist alone.

Second, as illustrated in FIGS. 10A-10B, islands 144 are still present, using island 144 as a mask to continue DRIE etching to form germanium electrodes 110 and germanium interconnect structures 104, 106 including extended mesa structures 112, The termination is performed on the underlying buried oxide layer 124. After the etching of the germanium layer 140 is completed, a dry etching technique is performed to remove the islands 144 by about 0.1 μm. In an embodiment, when only 0.1 μm of oxide and buried oxide 124 are removed by about 1.0 μm thick, the exposed buried oxide 124 significantly exceeding 0.1 μm is not removed. In accordance with an embodiment of the invention, the buried oxide 124 provides a junction of a partially patterned SOI structure The stability of the structure and the significant extent beyond the island 144 during removal of the island 144 are not removed from the buried oxide 124. As illustrated in FIG. 10B, the buried oxide layer 124 is exposed in the trench 116 around the germanium electrode and between the interconnect structures.

Referring now to Figures 11A through 11B, the front and back sides of the SOI wafer can then be oxidized to passivate the germanium electrode, the germanium interconnect structure, and the back side via opening. In an embodiment, high temperature wet oxidation may be performed to grow an oxide layer 118 of about 1 [mu]m thick on the germanium electrode 110, on the germanium interconnect structures 104, 106, and inside the trenches 116. Where the buried oxide layer 124 has been exposed, the thickness of the buried oxide layer 124 may increase or remain the same depending on the thickness previously present. In an embodiment, oxide layer 118 is approximately the same thickness as buried oxide layer 124. An oxide passivation layer 133 of about 1 μm thick is also grown inside the back side via opening 120A along the sidewall of the base substrate 130.

Referring now to FIGS. 12A through 12B, a thick patterned positive photoresist is applied over the interconnect structures 104, 106 and the germanium electrode 110, followed by etching the buried oxide exposed in the trench region 137, the exposed The buried oxide will correspond to the location where cavity 136 is formed. The patterned positive photoresist can be removed using O ₂ ashing followed by piranha etching.

A dry oxide etch using a suitable dry etch technique can then be performed to create an opening in the buried oxide layer 124 inside the backside via opening 120A to expose the bottom surface of the patterned germanium layer 140, at the bottom surface A germanium interconnect structure 106 is formed as illustrated in Figures 13A-13B. In an embodiment, a thin positive photoresist is formed over the back side of the SOI wafer and inside the back side via opening 120A and patterned. The buried oxide layer 124 is then etched to expose the bottom surface of the tantalum layer 140. In an embodiment, burying oxygen is performed using RIE Etching of the layer 124. As shown, the opening in the buried oxide layer 124 is smaller (eg, smaller in diameter or cross-section) than the opening in the interior of the base substrate 130 (including the oxide passivation layer 133). In this manner, having a smaller opening inside the buried oxide layer 124 than in the base substrate (including the oxide passivation layer 133) prevents inadvertent etching through the oxide passivation layer 133 or the undercut oxide passivation layer 133 And electrically shorting the rear side via 120 and the base substrate 130. Due to lithography tolerances and resolution capabilities, the openings inside the buried oxide layer 124 may have a minimum cross-section greater than 10 [mu]m.

Referring now to FIGS. 14A through 14B, patterned conductive layer 122 is formed over passivation layer 133 inside via opening 120A and in electrical contact with the bottom surface of germanium interconnect structure 106. In an embodiment, the patterned conductive layer 122 is formed by sputtering through a shadow mask. In an embodiment, the patterned conductive layer 122 includes a first layer of titanium (Ti) having a thickness of 500 angstroms, an intermediate layer of titanium-tungsten (TiW) of 500 angstroms thick, and an outer layer of gold (Au) having a thickness of 1 μm to 2 μm. In an embodiment, the patterned conductive layer 122 is in ohmic contact with the germanium interconnect structure 106.

Referring now to FIGS. 15A-15B, one or more cavities 136 can then be etched in the base substrate 130 just below the ruthenium electrode array such that the ruthenium electrode array can be deflected into one or more cavities. In an embodiment, a separate cavity 136 is formed just below each of the ruthenium electrodes. In an embodiment, a single cavity 136 is formed just below the first germanium electrode array in electrical communication with the first interconnect structure 104 and just below the second germanium electrode array electrically coupled to the second interconnect structure. . In an embodiment, the separate cavity 136 is formed just below the first electrode array in electrical communication with the first interconnect structure 104 and is formed just in the second electrode array electrically coupled to the second interconnect structure. Below. In an embodiment, a time-controlled release etch is used to form the cavity 136 into the base substrate 130, which etches the undercut electrode leads 114 and the mesa structure 112. For example, etching can be performed using a fluorine-based chemistry such as XeF ₂ or SF ₆ .

After forming one or more cavities 136, the SOI substrate can then be subsequently cut, for example using laser cutting, to form an array of compliant transport heads including compliant arrays interconnected with germanium interconnect structures 104, 106 The pole transfer head array extends through the base substrate 130 from the rear side of the base substrate to the patterned germanium layer 140 to electrically connect the drain electrode 110 with the through hole 120 of the working circuit system of the transfer head element.

Figure 16A is a plan view of a compliant single pole microdevice transfer head array of a double sided clamping support beam in accordance with an embodiment of the present invention. The particular embodiment illustrated in Figure 16A is similar to the embodiment illustrated in Figure 1A, wherein one difference is that the germanium electrode 110 for each compliant monopole transfer head includes a first extension from the first interconnect structure An electrode lead 114, a second electrode lead 114 extending from the second interconnect structure 104, wherein the first and second electrode leads 114 are joined at the mesa structure 112. Thus, the haptic electrode 110 forms a double-sided clamping support beam that is supported on the opposite side using a 矽 interconnect structure 104. In an embodiment, the first and second interconnect structures 104 are connected to the same voltage source.

Figure 16B is a plan view of a compliant single pole microdevice transfer head having a double clamping support beam in accordance with an embodiment of the present invention. Figure 16C is a cross-sectional side view of the transverse line C-C of the compliant monopole microdevice transfer head illustrated in Figure 16B, in accordance with an embodiment of the present invention. Figure 16D is a cross-sectional side view of the longitudinal line D-D of the compliant single pole microdevice transfer head illustrated in Figure 16B, in accordance with an embodiment of the present invention. Similar to the embodiment illustrated in Figures 1B through 1D, In Fig. 16B, only a single transfer head is illustrated spanning between two turns of trace interconnect structure 104 and supported by two turns of trace interconnect structure 104, although an array of transfer heads may be crossed in accordance with an embodiment of the present invention. Between the interconnect structures 104. In the illustrated embodiment, the longitudinal length of the support beam is parallel to the tantalum interconnect structure 104. As illustrated in FIGS. 16C through 16D, both the erbium mesa structure 112 and the leads 114 extend over the cavity 136 between the base substrate 130 and the 矽 electrode 110 and are deflectable into the cavity 136.

Referring again to FIG. 16A, a single cavity 136 can be formed under the tantalum electrode array 110 between a pair of tantalum interconnect structures 104. In another embodiment, a separate cavity 136 can be formed under each of the ruthenium electrodes 110. In another embodiment, a single cavity 136 can be formed under the first 矽 electrode array between the first 矽 interconnect structure and across the second 矽 electrode array between the second 矽 interconnect structures . In another embodiment, the first cavity 136 can be formed over the first 矽 electrode array between the first pair of 矽 interconnect structures and the second cavity 136 separated from the first cavity 136 is formed across the second Opposite the second electrode array between the interconnect structures. Trench 116 may also be formed to define germanium electrode 110 and germanium interconnect structures 104, 106 in the patterned germanium layer. If the cavity 136 does not surround one end of the germanium interconnect structure 104, the trench 116 may also be formed in the patterned germanium layer at the end of the germanium interconnect structure 104.

17A to 28B illustrate a method of forming a compliant single-pole micro device transfer head including a double-sided clamping support beam and an upper side through hole opening and a rear side through hole opening according to an embodiment of the present invention. . In the embodiment, the processing sequence of FIGS. 17A to 20B may be the same as the processing sequence described with respect to FIGS. 5A to 8B. Referring to Figures 21A-22B, the germanium electrode 110 and interconnect structures 104, 106 can be patterned in a two-part etch sequence. First, as illustrated in FIGS. 21A-21B, the top germanium layer 140 is partially etched away to define the pattern of the germanium electrode 110 and the interconnect structures 104,106. In an embodiment, this can be accomplished using a thin patterned positive photoresist in which DRIE etches a 7 μm to 10 μm thick top germanium layer 140 of about 5 μm in a timed etch. The patterned positive photoresist can be removed using O ₂ ashing followed by piranha etching.

Second, the islands 144 as illustrated in Figures 18A through 18B are still present, using the island 144 as a mask to continue the DRIE etch to form the germanium electrode 110 and interconnect structures 104, 106 including the extended mesa structure 112, terminating On the oxide layer 124 buried in the lower layer. After the etching of the germanium layer 140 is completed, a dry etching technique is performed to remove the islands 144 by about 0.1 μm. In an embodiment, when only 0.1 [mu]m of oxide is removed and the buried oxide 124 is about 1.0 [mu]m thick, the buried oxide 124 that is significantly over 0.1 [mu]m exposed is not removed. In accordance with an embodiment of the invention, the buried oxide 124 provides structural stability to the partially patterned SOI structure and significantly exceeds the thickness of the island 144 during removal of the island 144 from being removed from the buried oxide 124.

Referring now to Figures 23A through 23B, the front and back sides of the SOI wafer can then be oxidized to passivate the germanium electrode, the germanium interconnect structure, and the back side via opening. In an embodiment, high temperature wet oxidation may be performed to grow an oxide layer 118 of about 1 [mu]m thick on the germanium electrode 110, on the germanium interconnect structures 104, 106, and inside the trenches 116. Where the buried oxide layer 124 has been exposed, the thickness of the buried oxide layer 124 may increase or remain the same during thermal oxidation, depending on the thickness previously present. In an embodiment, oxide layer 118 is approximately the same thickness as buried oxide layer 124. An oxide passivation layer 133 of about 1 μm thick At the same time, it is grown inside the rear side through hole opening 120A along the side wall of the base substrate 130.

Referring now to Figures 24A through 24B, openings (which will be part of the via opening 120B) are formed in the top dielectric layer 118 to be exposed just above the back side via opening 120A and in the trench region 137 ( A patterned germanium layer 140 at the region of the germanium interconnect structure 106 at one or more of the cavities 136) will be formed herein. The trench region 137 opening is also simultaneously formed in the buried oxide layer 124 to expose the base substrate 130 (where one or more cavities 136 will be formed). Openings can be formed in the top dielectric layer 118 and the buried oxide layer 124 using a thick patterned positive photoresist followed by dry etching of the top dielectric layer 118. The patterned photoresist is then removed by O ₂ ashing followed by piranha etching to produce the structures illustrated in Figures 20A-20B. Forming the etch and patterning steps to form the via opening 120B and the trench region 137 opening also reduces the number of processing operations and the number of masks required.

Referring now to FIGS. 25A through 25B, openings are formed in the tantalum layer 140 and the buried oxide layer 124 to form an upper side via opening 120B that connects the back side via opening 120A. By forming a thick patterned positive photoresist, DRIE of the germanium layer 140 terminating on the buried oxide layer 124 is then performed, followed by RIE through the buried oxide layer 124, and the opening can be formed in the germanium layer 140 and buried oxide layer 124. O ₂ ashing followed by piranha etch followed by removing the patterned photoresist to produce the structure of FIG. 25A through FIG. 25B. In this manner, forming an opening through the buried oxide layer 124 when the upper via opening 120B is formed can avoid the lithography challenge associated with forming an opening in the buried oxide layer 124 from the back side of the SOI structure. The passivation layer 133 along the sidewalls of the via opening 120A is not adversely affected.

Subsequent patterned conductive layer 123 may be formed over the exposed top surface of germanium interconnect structure 106 and inside the inner surface of germanium interconnect structure 106, as illustrated in Figures 26A-26B. In this manner, the partial formation of the conductive layer 123 over the top surface of the germanium interconnect structure 106 can provide a larger surface area for ohmic contact with the germanium interconnect structure 106. Since the germanium interconnect structure 106 is closer to the top surface of the SOI structure than the back side surface of the SOI structure, in accordance with some embodiments, the interconnect structure 106 is over the top surface of the SOI structure from the back surface of the SOI structure. Forming a conductive layer 123 inside the inner surface may be more efficient. In an embodiment, the patterned conductive layer 123 is formed by sputtering through a shadow mask. In an embodiment, the patterned conductive layer 123 comprises a first layer of 500 angstroms thick titanium (Ti), an intermediate layer of 500 angstroms thick titanium-tungsten (TiW), and an outer layer of gold (Au) 1 μm to 2 μm thick. . In an embodiment, the patterned conductive layer 123 is in ohmic contact with the germanium interconnect structure 106.

Referring now to FIGS. 27A through 27B, the patterned conductive layer 122 can be formed on the passivation layer 133 inside the via opening 120A and in electrical contact with the patterned conductive layer 123. The conductive layer 122 may be formed of the same or different material as the conductive layer 123 and may have the same or different thicknesses. In an embodiment, the conductive layer 123 has a thicker gold layer.

Referring now to Figures 28A through 28B, one or more cavities 136 can then be etched in the base substrate 130 just below the tantalum electrode array such that the tantalum electrode array can be deflected into one or more cavities. In an embodiment, a separate cavity 136 is formed just below each of the ruthenium electrodes. In an embodiment, a single cavity 136 is formed just below the array of germanium electrodes in electrical communication with the first and second interconnect structures 104. Other cavity configurations can be etched as described above with respect to Figure 16A. In an embodiment, a time-controlled release etch is used to form the cavity 136 into the base substrate 130, which etches the undercut electrode leads 114 and the mesa structure 112. For example, etching can be performed using a fluorine-based chemistry such as XeF ₂ or SF ₆ . In an embodiment, one or more of the cavities 136 are approximately 15 [mu]m deep.

After forming one or more cavities 136, the SOI substrate can then be subsequently cut, for example using laser cutting, to form a compliant unipolar transmission head array that includes the 矽 interconnect structures 104, 106 a compliant monopolar transmission head array and a working circuit system extending through the base substrate 130 from the rear side of the base substrate to the patterned germanium layer 140 and through the patterned germanium layer 140 to electrically connect the germanium electrode 110 and the transfer head element Through hole 120.

29A through 34B illustrate a method of forming a compliant single-pole microdevice transfer head including a double-sided clamping support beam and a deposited dielectric layer and an upper via opening, in accordance with an embodiment of the present invention. And the rear side through hole opening. In the embodiment, the processing sequence leading to FIGS. 29A to 29B may be the same as the processing sequence of FIGS. 17A to 23B as described above. Referring now to Figures 29A through 29B, in the embodiment the opening is formed in the top dielectric layer 118 just above the back side via opening 120A and just above the mesa structure 112. The trench region 137 opening is also simultaneously formed in the buried oxide layer 124 to expose the base substrate 130 (where one or more cavities 136 will be formed). Openings can be formed in the top dielectric layer 118 and the buried oxide layer 124 using a thick patterned positive photoresist followed by dry etching of the top dielectric layer 118. In an embodiment, the top dielectric layer 118 and the buried oxide layer 124 have approximately the same thickness. In an embodiment, the top dielectric layer 118 and the buried oxide layer 124 can be removed using a time-controlled dry oxide etch. O ₂ ashing followed by piranha etch followed by removing the patterned photoresist to produce the structure of FIG. 29A through FIG. 29B. Forming the etch and patterning steps to form via openings 120A and trench regions 137 openings also reduces processing operations and the number of masks required.

Referring now to FIGS. 30A through 30B, in an embodiment, a second dielectric layer 126 is formed over the top surface, and the second dielectric layer 126 includes a patterned dielectric layer 118 and a patterned germanium layer 140 for subsequent use. A thick positive photoresist patterns the second dielectric layer 126 and etches the second dielectric layer 126. After the etching is completed, the patterned second dielectric layer 126 covers the mesa structure 112 and may also cover portions of the electrode leads 114 and the patterned dielectric layer 118. The patterned second dielectric layer 126 is removed from directly above the upper back via opening 120A of the patterned germanium layer 140 and the trench region 137 where one or more cavities 136 will be formed. In an embodiment, the second dielectric layer can have a higher dielectric constant or dielectric breakdown strength than the dielectric layer 118 and have a thickness between 0.5 μm and 10 μm. For example, the second dielectric layer 126 is an Al ₂ O ₃ , Ta ₂ O _{5 ,} or HfO ₂ layer deposited by atomic layer deposition (ALD).

Referring now to FIGS. 31A through 31B, openings are formed in the tantalum layer 140 and the buried oxide layer 124 to form upper side via openings 120B that connect the back side via openings 120A. By forming a thick patterned positive photoresist, DRIE of the germanium layer 140 terminating on the buried oxide layer 124 is then performed, followed by RIE through the buried oxide layer 124, and the opening can be formed in the germanium layer 140 and buried oxide layer 124. O ₂ ashing followed by piranha etch followed by removing the patterned photoresist to produce the structure of FIGS. 31A through 31B illustrated in FIG. In this manner, forming an opening through the buried oxide layer 124 when the upper via opening 120B is formed can avoid the lithography challenge associated with forming an opening in the buried oxide layer 124 from the back side of the SOI structure. The passivation layer 133 along the sidewalls of the via opening 120A is not adversely affected.

Patterned conductive layer 123 is then formed over the exposed top surface of germanium interconnect structure 106 and inside the inner surface of germanium interconnect structure 106, as illustrated in Figures 32A-32B. In this manner, the partial formation of the conductive layer 123 over the top surface of the germanium interconnect structure 106 can provide a larger surface area for ohmic contact with the germanium interconnect structure 106. Since the germanium interconnect structure 106 is closer to the top surface of the SOI structure than the back side surface of the SOI structure, in accordance with some embodiments, the interconnect structure 106 is over the top surface of the SOI structure from the back surface of the SOI structure. Forming a conductive layer 123 inside the inner surface may be more efficient. In an embodiment, the patterned conductive layer 123 is formed by sputtering through a shadow mask. In an embodiment, the patterned conductive layer 123 includes a first layer of 500 angstroms thick titanium (Ti), an intermediate layer of 500 angstroms thick titanium-tungsten (TiW), and an outer layer of gold (Au) 1 μm to 2 μm thick. In an embodiment, the patterned conductive layer 123 is in ohmic contact with the germanium interconnect structure 106.

The patterned conductive layer 122 may be formed on the passivation layer 133 inside the via opening 120A and in electrical contact with the patterned conductive layer 123 as illustrated in FIGS. 33A to 33B. The conductive layer 122 may be formed of the same or different material as the conductive layer 123 and may have the same or different thicknesses. In an embodiment, the conductive layer 123 has a thicker gold layer. The conductive layers 122, 123 may form a continuous conductive layer along the side surface of the via 120.

Referring now to Figures 34A through 34B, one or more cavities 136 can then be etched in the base substrate 130 just below the xenon electrode array such that the tantalum electrode array can be deflected into one or more cavities. In an embodiment, a separate cavity 136 is formed just below each of the ruthenium electrodes. In an embodiment, a single cavity 136 is formed just below the array of germanium electrodes in electrical communication with the first and second interconnect structures 104. Other cavity configurations can be etched as described above with respect to Figure 16A. In an embodiment, a time-controlled release etch is used to form the cavity 136 into the base substrate 130, which etches the undercut electrode leads 114 and the mesa structure 112. For example, etching can be performed using a fluorine-based chemistry such as XeF ₂ or SF ₆ . In an embodiment, one or more of the cavities 136 are approximately 15 [mu]m deep.

After forming one or more cavities 136, the SOI substrate can then be subsequently cut, for example using laser cutting, to form a compliant transfer head array that includes compliant transmissions interconnected with the germanium interconnect structures 104, 106 The head array and the through hole 120 extending through the base substrate 130 from the rear side of the base substrate to the patterned germanium layer 140 and through the patterned germanium layer 140 to electrically connect the drain electrode 110 and the working circuit system of the transfer head element.

35 through 41 illustrate various modifications of a compliant single pole micro device transfer head between the turns interconnect structures 104 in accordance with an embodiment of the present invention. Although FIGS. 35 to 41 are respectively illustrated in accordance with the processing sequence illustrated above, it will be understood that many of the various modifications described with respect to FIGS. 31 to 37 can be implemented in the aforementioned processing sequence.

Figure 35 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having a cantilever beam, in accordance with an embodiment of the present invention. In an embodiment, the tantalum electrode cantilever beam can include a pair of bonded tantalum electrode leads 114 and mesa structures 112. In the illustrated embodiment, a pair of tantalum electrode leads 114 extend from a pair of tantalum interconnect structures 104, including a bend 115 (shown as 90) And bent as a single tantalum electrode lead 114 extending parallel to the tantalum interconnect structure pair 104. As shown, the longitudinal length of the 矽 electrode cantilever beam is parallel to the 矽 interconnect structure pair 104.

Figure 36 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having cantilever beams and separate electrode leads in accordance with an embodiment of the present invention. In an embodiment, the tantalum electrode cantilever beam can include a pair of bonded tantalum electrode leads 114 and mesa structures 112. In the illustrated embodiment, a pair of tantalum electrode leads 114 extend from a pair of tantalum interconnect structures 104, including bends 115 (shown as 90 degree bends) and joined at mesa structure 112. As shown, the longitudinal length of the 矽 electrode cantilever beam is parallel to the 矽 interconnect structure pair 104.

Figure 37 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having a double sided clamping beam, in accordance with an embodiment of the present invention. As shown, the tantalum electrode double side clamping beam can include a pair of curved tantalum electrode leads 114 extending from the two tantalum interconnect structures 104. The curved tantalum electrode lead pair 114 is joined to the two tantalum interconnect structures 104 at two locations and joined together along a longitudinal length of the support beam parallel to the tantalum interconnect structure pair. The electrode lead pair 114 can span between the two turns interconnect structures 104, with each electrode lead including a pair of bends 115 (shown as a 90 degree bend).

Figure 38 is a plan view and cross-sectional side view of line A-A of a compliant single pole microdevice transfer head having a support beam structure and separate curved electrode leads in accordance with an embodiment of the present invention. As shown, a pair of tantalum electrode leads 114 extend from a pair of tantalum interconnect structures 104 and are joined at mesa structure 112, wherein each tantalum electrode lead includes a double bend 115 (shown as a 90 degree bend). In addition, each of the detachable electrode leads 114 enables beam configuration The 8-shape configuration between the erbium electrode leads 114 is assumed.

Figure 39 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having a support beam structure and a plurality of bends in accordance with an embodiment of the present invention. As shown, the tantalum electrode double side clamping beam can include a pair of tantalum electrode leads 114 extending from a pair of interconnect structures 104 and joined at the mesa structure 112. Each turn electrode lead 114 includes a single bend 115.

Figure 40 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having a support beam structure and a plurality of bends in accordance with an embodiment of the present invention. Figure 41 is a plan view and cross-sectional side view of line A-A along a compliant single pole microdevice transfer head having a support beam structure and a plurality of bends in accordance with an embodiment of the present invention. As shown, the tantalum electrode double side clamping beam can include a pair of tantalum electrode leads 114, each tantalum electrode lead 114 having a double bend 115. In the particular embodiment illustrated in Figure 40, the beam is in a W-shaped configuration. In the particular embodiment illustrated in Figure 41, the beam is in an S-shape configuration.

In accordance with an embodiment of the present invention, the dielectric layer 118 or 126 covering the mesa structure 112 has a suitable thickness and dielectric constant for achieving the clamping pressure required for the microdevice transfer head and has sufficient dielectric strength to be out of operation. Breakdown under voltage. Figure 42 is a flow chart illustrating a method of picking up and transporting a microdevice array from a carrier substrate to a receiving substrate in accordance with an embodiment of the present invention. At operation 4210, the compliant transfer head array is positioned over the array of micro devices on the carrier substrate. Figure 43 is a cross-sectional side view of a compliant monopolar microdevice transfer head array over a microdevice array on a carrier substrate 200, in accordance with an embodiment of the present invention. At operation 4220, the array of micro devices contacts the array of compliant transfer heads. In an alternative embodiment, the compliant transmission head array is positioned above the micro device array, the micro The array of devices has an appropriate air gap separating the micro devices, for example, 1 nm to 10 nm, which does not significantly affect the clamping pressure. Figure 44 is a cross-sectional side view of a compliant monopolar microdevice transfer head array in contact with a microdevice array 202 in accordance with an embodiment of the present invention. As shown, the pitch of the compliant transmission head array is an integer multiple of the pitch of the microdevice array 202. At operation 4230, a voltage is applied to the compliant transmission head array. A voltage can be applied from a working circuitry internal to the compliant transfer head element 160 that is electrically coupled to the compliant transfer head array via vias 120. At operation 4240, the array of microdevices is picked up using an array of compliant transport heads. Figure 45 is a cross-sectional side view of a compliant transmission head array for picking up a microdevice array 202 in accordance with an embodiment of the present invention. At operation 4250, the micro device array is then released onto the receiving substrate. For example, the receiving substrate can be, but is not limited to, a display substrate, an illumination substrate, a substrate having a functional device such as a transistor or an IC, or a substrate having a metal redistribution line. Figure 46 is a cross-sectional side view of a microdevice array 202 released onto a receiving substrate 300 in accordance with an embodiment of the present invention.

Although operation 4210 through operation 4250 have been sequentially illustrated in FIG. 42, it will be understood that the embodiments are not limited thereto and that additional operations may be performed, and that certain operations may be performed in a different order. For example, in one embodiment, an operation is performed to generate a phase change of the bonding layer connecting the micro device to the carrier substrate before or at the time of picking up the micro device. For example, the tie layer can have a liquidus temperature of less than 350 °C, or, more specifically, a liquidus temperature of less than 200 °C. The bonding layer may be formed of a material that is bonded to the carrier substrate, but may also be formed of a medium that can easily release the micro device. In an embodiment, the bonding layer is a material such as indium or an indium alloy. Executable if a micro device is used to pick up a part of the bonding layer Additional operations are performed to control the phase of the portion of the bonding layer during subsequent processing. For example, heat can be applied to the bonding layer from a heat source located within the transfer head element 160, the carrier substrate 200, and/or the receiving substrate 300.

Moreover, operation 4230 of applying a voltage to create a clamping pressure on the micro device can be performed in various orders. For example, a voltage can be applied before the micro device array contacts the compliant transport head array, when the micro device contacts the compliant transport head array, or after the micro device contacts the compliant transport head array. It is also possible to apply a voltage before, during or after the phase change in the bonding layer.

Where the compliant transfer head includes a monopolar germanium electrode, a voltage is applied to the monopolar germanium electrode array to generate a pick-up pressure. The release of the microdevice from the compliant transfer head can be accomplished using a modified method that includes turning off the voltage source, lowering the voltage, and grounding the voltage source. Release can also be accomplished by discharge associated with placing the microdevice on the receiving substrate.

In making use of the various aspects of the present invention, it will be apparent to those skilled in the art that combinations or variations of the above embodiments may be used to form compliant monopolar microdevice transfer heads and head arrays and for transmitting microdevices and micro Device array. Although the present invention has been described in language specific to structural features and/or methods, it is to be understood that the invention is not limited to the specific features or acts described. Rather, the specific features and acts disclosed are to be understood as a particularly preferred embodiment of the claimed invention.

112‧‧‧ countertop structure

114‧‧‧Electrode lead

116‧‧‧ trench

118‧‧‧ dielectric layer

120‧‧‧through hole

120A‧‧‧Back side through hole opening

120B‧‧‧Upper through hole opening

122‧‧‧ patterned conductive layer

123‧‧‧ patterned conductive layer

124‧‧‧buried oxide layer

130‧‧‧Base substrate

132‧‧‧ Passivation layer

133‧‧‧passivation layer

136‧‧‧ cavity

140‧‧‧矽

Claims (20)

A compliant micro device transmission head array includes: a base substrate; a patterned germanium layer over the base substrate, the patterned germanium layer including a germanium interconnect structure and electrical An array of electrodes connected to the germanium interconnect structure, wherein each germanium electrode includes an electrode lead and a mesa structure, wherein each mesa structure protrudes above the germanium interconnect structure and each germanium electrode is deflectable to the a cavity between the base substrate and the germanium electrode; and a dielectric layer covering a top surface of each mesa structure. The compliant micro device transport head array of claim 1, wherein each of the xenon electrode arrays is deflectable into a cavity in the base substrate. The compliant microdevice transport head array of claim 2, wherein the tantalum electrode array is deflectable into the same cavity in the base substrate. The compliant micro device transmission head array of claim 3, wherein the 矽 electrode array extends from a first side of the 矽 interconnect structure, and further comprising a second 矽 electrode array, the second 矽 electrode array The first side of the first side extends opposite a second side of the meandering interconnect structure. The compliant microdevice transport head array of claim 1, wherein the patterned germanium layer is on a buried oxide layer and is in direct contact with the buried oxide layer. The compliant micro device transmission head array according to claim 5, the compliant micro device transmission head array further comprising a through hole extending through the base substrate and the buried erbium oxide layer, from the base substrate A back side to the patterned germanium layer is electrically connected to the germanium interconnect structure and the germanium electrode array. The compliant microdevice transport head array of claim 4, wherein the second tantalum electrode array is deflectable into a second cavity in the base substrate that is separated from the cavity. The compliant microdevice transport head array of claim 4, wherein the second tantalum electrode array is deflectable into the same cavity in the base substrate, wherein the cavity surrounds one end of the tantalum interconnect structure. The compliant micro device transfer head array of claim 1, wherein the patterned germanium layer further comprises a second germanium interconnect structure and a second germanium electrode array electrically connected to the second germanium interconnect structure, wherein Each of the germanium electrodes in the second electrode array includes an electrode lead and a mesa structure, wherein each mesa structure protrudes above the second germanium interconnect structure and each of the second germanium electrode arrays A drain electrode may be deflected into a cavity between the base substrate and the drain electrode; and the dielectric layer covers a top surface of each of the mesa structures in the second tantalum electrode array. The compliant micro device transmission head array of claim 9, wherein each of the 矽 electrode array and each of the second 矽 electrode arrays are deflectable into a cavity in the base substrate. The compliant micro device transmission head array of claim 10, wherein the 矽 electrode array is deflectable into one of the first cavities of the base substrate, and the second 矽 electrode array is deflectable into the pedestal substrate A cavity separates one of the second chambers. The compliant micro device transport head array of claim 10, wherein the 矽 electrode array and the second 矽 electrode array are deflectable into the same cavity in the base substrate. The compliant micro device transport head array of claim 10, further comprising: a buried ruthenium dioxide layer between the patterned ruthenium layer and the base substrate; a first through hole extending through the base substrate and the buried ruthenium dioxide layer, from a rear side of the base substrate to the patterned ruthenium layer, and the 矽 interconnect structure and the 矽 electrode array Electrically connecting; and a second through hole extending through the base substrate and the buried ruthenium dioxide layer, from the rear side of the base substrate to the patterned ruthenium layer, and interacting with the second 矽The connection structure and the second electrode array are electrically connected; wherein the germanium interconnect structure is electrically insulated from the second germanium interconnect structure. The compliant micro device transport head array of claim 1, wherein the patterned germanium layer further comprises a second germanium interconnect structure electrically connected to the germanium interconnect structure, wherein each germanium electrode further comprises a second An electrode lead, wherein the electrode lead extends from the germanium interconnect structure, and the second electrode lead extends from the second germanium interconnect structure. The compliant microdevice transport head array of claim 14, wherein the electrode lead and the second electrode lead each comprise one or more bends. The compliant microdevice transport head array of claim 14, wherein the tantalum electrode array forms an array of support beams that span between the tantalum interconnect structure and the second tantalum interconnect structure. The compliant microdevice transport head array of claim 16, wherein the longitudinal length of the support beam array is perpendicular to the 矽 interconnect structure and the second 矽 interconnect structure. The compliant microdevice transport head array of claim 14, wherein the tantalum electrode array forms an array of cantilever beams between the tantalum interconnect structure and the second tantalum interconnect structure. The compliant microdevice transport head array of claim 18, wherein the longitudinal length of the cantilever beam array is parallel to the tantalum interconnect structure and the second tantalum interconnect structure. The compliant micro device transport head array of claim 14, further comprising: a buried ruthenium dioxide layer between the patterned ruthenium layer and the base substrate; a through hole extending through the base substrate and the buried ruthenium dioxide layer, from a rear of the base substrate The patterned germanium layer is laterally connected to the germanium interconnect structure, the second germanium interconnect structure, and the germanium electrode array.