TWI537697B - Programmable low-dropout regulator and methods therefor - Google Patents

Description

Programmable low dropout regulator and method thereof

The present disclosure relates generally to low dropout (LDO) regulators, and more particularly to programmable LDOs and methods therefor.

Low dropout (LDO) regulators are intended to provide well-defined voltage supply levels for a wide variety of operating conditions, including variable supply voltage, load current, temperature, and the like. Typically, these devices cannot be equipped with user-programmable digitally programmable features. Conventionally, LDO regulators sometimes include disposable programmable devices that can be programmed using one-time programmable techniques, such as laser trimming during product testing or melting of metal wire fuses.

Some LDO regulators include control terminals that can be connected to ground or can be supplied with specific levels to select a correction value for the nominal output voltage, providing limited programmability. Some other LDO regulators include terminals or terminal sets that provide an irreversible one-time programmable function to adjust the level of the output voltage. However, this limited programmability is not responsible for the multiple applications of a particular LDO regulator, nor does it address the needs of various end users.

Embodiments of a programmable LDO regulator are disclosed below. The programmable LDO regulator includes a digital trimming mechanism based on a binary control sequence that can be used to configure various circuit blocks in the LDO regulator, including voltage reference circuits. , transfer devices, error amplifiers, and feedback circuits. Binary control The sequence can be stored in the non-volatile register of the LDO regulator, allowing the programmed settings to be restored upon power up.

By incorporating a digital trimming mechanism into a programmable LDO regulator, the number of fabrication masks required to achieve various output voltage levels is reduced. In addition, digital trimming provides a reliable solution for adjusting the functional parameters of the LDO regulator circuit during both front-end testing and back-end testing. In addition, the digital fine-tuning mechanism allows such parameters to be programmed multiple times, increasing the flexibility of processing inventory and reducing the turnaround time for providing LDO regulator products to customers.

In addition, the digital trimming mechanism includes a serial interface that provides an end user solution for changing or adjusting the functional parameters of the LDO regulator. The serial interface provides means for digitally controlling the performance parameters of the LDO regulator, allowing for easy functional connection to various control systems or simple function integration in other circuits such as power management integrated circuit (PMIC) systems. . In addition, the serial interface allows easy access to user-programmable features of the LDO regulator.

Digital trimming techniques can be used to adjust the DC and AC parameters associated with the output voltage of the LDO regulator. For example, digital trimming techniques can be used to change the output voltage level, such as by selecting a nominal value from a predetermined range of predetermined levels. Alternatively or additionally, these digital trimming techniques can be applied to adjust the output voltage to provide enhanced accuracy. In addition, digital trimming can be used to adjust one or more impedances to optimize AC performance. In one example, the control circuit includes a non-volatile data storage medium for storing digital sequences of signals to control the functional components and performance of the LDP regulator parameter. The use of digital sequences to control the parameters of programmable LDO regulators makes it possible to program LDO regulators multiple times when compared to one-time programmable laser trimming or electrical techniques for melting fuses. In addition, digital stylization of DC and AC parameters can be utilized for both product testing and for the purpose of providing fine-tuning capabilities for the user mode.

1 is a partial schematic and partial block diagram of an embodiment of a low dropout (LDO) regulator circuit 100 that includes a control circuit 110. The LDO regulator circuit 100 includes a voltage input (V _IN ) coupled to the programmable voltage reference circuit 102 that is configured to provide a reference voltage (V _REF ) to the output terminal 103. Output terminal 103 is coupled to a first input of programmable error amplifier 104. The programmable error amplifier 104 also includes a second input coupled to the programmable feedback circuit 108 to receive the feedback signal (V _F ) and includes an amplifier output 120 coupled to the control input of the programmable transfer device 106.

The programmable transfer device 106 includes a first input coupled to a voltage input (V _IN ) and an output terminal 114 configured to carry an output voltage (V _OUT ) and a load current (I _L ). The programmable transfer device 106 provides power from the voltage input (V _IN ) to the load 116, which is typically indicated as the load impedance (Z _L ).

In the illustrated embodiment, control circuit 110 is coupled to programmable voltage reference circuit 102 via reference control input 122 to provide one or more control signals to selectively adjust the thermal coefficient of the reference voltage. Control circuit 110 is also coupled to programmable error amplifier 104 via control input 124 to provide control signals for adjusting adaptive bias parameters, short circuit protection parameters, and/or offset parameters. In the first mode, the bias parameter is disabled to apply a fixed bias with a predetermined level to control the quiescent current flowing through the error amplifier 104. In the second mode, the bias parameter is enabled to apply an adaptive bias configured to automatically adjust the quiescent current flowing through the error amplifier 104 based on the load current (I _L ). Additionally, the short circuit protection parameter can be configured using one or more control signals received via control input 124 to adjust the level used to provide such protection, the protection being triggered in response to load current (I _L ). Moreover, the DC offset parameter can be configured by controlling the control signal on input 124 to adjust the input offset of the error amplifier. Likewise, the AC frequency compensation mechanism can be enabled using control signals on control input 124.

In addition, control circuit 110 is coupled to programmable transfer device 106 via transfer device control input 126 to selectively enable or disable circuitry within programmable device 106 to control load current (I _L ). In one example, the programmable transfer device 106 includes a transistor network that can be configured to program a transient response. Additionally, control circuit 110 is coupled to programmable feedback circuit 108 via feedback control input 128 to selectively adjust the impedance of programmable feedback circuit 108. The programmable feedback circuit 108 can include a resistor-capacitor (RC) network that can be programmed to provide the desired complex impedance. In addition, the programmable feedback circuit 108 can also include a resistive network that can be programmed to provide the required resistance. The programmable feedback circuit 108 provides the ability to adjust the DC output voltage level and the AC performance parameters of the LDO regulator circuit 100.

In the embodiment shown in FIG. 1, the programmable LDO regulator 100 is provided with a serial interface 112 for receiving instructions from an external source and for exchanging data with an external source. The serial interface 112 can be a custom single-wire, two-wire, or three-wire serial interface. Alternatively, the serial interface 112 can be a standard I ² C bus interface, a serial peripheral interface (SPI), a microwire serial bus interface, a universal serial bus interface, other serial interfaces, or Some combinations of them. The external source can be a microcontroller, a microprocessor, a power management integrated circuit (PMIC), a system single chip (SOC) circuit, other types of circuits, or any combination thereof. The serial interface 112 is coupled to the control circuit 110 to receive and transmit control information 130 and other data 132 from an external source.

In addition to the digital signals transmitted via the serial interface 112, other external signals can be applied to the LDO regulator circuit 100 during the staging cycle to provide the programmed voltage levels required for the tunneling process in the floating gate MOS device. Quasi (V _PP ). Even when the device is not powered, information that is programmed by the tunneling process can be maintained on the floating gate, and the information can be erased or reprogrammed by using a stylized signal, the stylization The signal is, for example, a signal with a voltage level required to induce charge tunneling to or from the floating gate. In an implementation, a stylized signal including (V _PP ) is provided via the serial interface 112. In another implementation, a (V _PP ) can be generated internally using a charge pump (not shown) on the wafer. Floating gate MOS devices can be implemented using electrically erasable programmable read only memory (EEPROM) technology, CMOS technology, Bi-CMOS, and other MOS technologies.

In an embodiment, various features of the programmable error amplifier 104 can be enabled or disabled by a digital control signal from the control circuit 110. One of the representative features is an adaptive bias that is compared to a fixed offset in error amplifier 104. The adaptive bias increases the quiescent current of the error amplifier 104, and the increased current load (I _L ) passes through the programmable transfer device 106, thus providing a faster transient response. However, such a feature increases power consumption and reduces the DC efficiency of the LDO regulator circuit 100. Because power consumption and DC efficiency may be significant in some applications, the ability to disable the adaptive biasing feature and limit the quiescent current of the error amplifier 104 to a certain maximum may be useful for certain low power applications. of. Such a control function can be implemented using a digital signal that can be programmed via the serial interface 112 and applied by the control circuit 110.

Another characteristic of the error amplifier 104 that can be easily programmed using the digital control signal is the short circuit protection parameter. Depending on its implementation, the digital control signal from control circuit 110 and/or from serial interface 112 can be used to select the level of load current (I _L ) that triggers the short circuit protection, turning off transfer device 106.

The programmable offset control mechanism can also be implemented using a digital control signal to modify the DC offset of the error amplifier 104. Moreover, the AC performance of the error amplifier 104 can be modified using a digital control signal configured with a programmable feedback circuit 108 that operates in conjunction with the error amplifier 104.

In operation, LDO regulator circuit 100 is capable of receiving instructions and data via serial interface 112 for controlling DC and AC performance parameters of LDO regulator circuit 100. In this manner, LDO regulator circuit 100 is considered to be digitally programmable. In some embodiments, it may be desirable to store configuration parameters in memory. Control circuitry 110 can include a volatile data store such as a scratchpad, cache, or other volatile memory. An example of an embodiment of control circuit 110 is depicted in FIG. 2, which includes both volatile and non-volatile Two types of registers.

2 is a partial schematic and partial block diagram of an embodiment of an LDO regulator circuit 200, such as the LDO regulator circuit 100 of FIG. 1, with an expanded view of an embodiment of the control circuit 110. In the illustrated embodiment, control circuit 110 includes a volatile configuration register 202, a non-volatile register 204, and control logic 206. The volatile and non-volatile registers 202 and 204 can be used to store one or more digital sequences to control the programmable voltage reference circuit 102, the programmable error amplifier 104, and the programmable transfer device. 106, and a programmable feedback circuit 108.

In an example, control circuit 110 receives a digital control sequence from an external source via serial interface 112 and stores the digital control sequence in configuration register 202. The stored digital control sequence configures the parameters of the programmable voltage reference circuit 102, the programmable error amplifier 104, the programmable transfer device 106, and the programmable feedback circuit 108 to control the DC and AC parameters associated with the output voltage. . Once the desired performance of the LDO regulator circuit 200 is implemented using one or more digital sequences, the control logic 206 stores configuration data, such as a sequence of digits, into the non-volatile registers 204. Control logic 206 can reload configuration data from non-volatile registers 204 to volatile configuration registers 202 in the event of an unexpected power loss, or when power is restored after a shutdown event. In order to configure the operation of the LDO regulator circuit 100.

The output voltage and associated AC and DC characteristics can be partially adjusted using the programmable feedback circuit 108. The programmable feedback circuit 108 can be implemented in a variety of ways. Representatives of the programmable feedback circuit 108 are depicted in Figures 3-5 An example of a sexual embodiment.

3 is a block diagram of an embodiment of a programmable feedback circuit 108 of the LDO regulator 100 of FIG. The programmable feedback circuit 108 is a negative feedback network that includes a first impedance network (or input stage) 302 and second and third impedance networks (or output stages) 304 and 306. Each of the impedance networks 302, 304, and 306 is coupled to the control circuit 110 via a feedback control input 128 that includes first, second, and third feedback control inputs 322, 324, and 326. The first impedance network 302 includes a feedback input coupled to the output terminal 114 of the LDO regulator circuit 100, and feedback control for receiving a first feedback control signal labeled "FC1[0:m-1]" from the control circuit 110. Input 322, and terminal 312. The second impedance network 304 includes an input coupled to terminal 312, a second feedback control input 324 for receiving a second feedback control signal labeled "FC2[0:n-1]" from control circuit 110, and a feedback output (V _OUTF ) 314, the feedback output (V _OUTF ) 314 is coupled to the input of the error amplifier 104 depicted in FIG. The second impedance network 304 also includes a terminal 316 that is coupled to the third impedance network 306. The third impedance network 306 includes a third feedback control input 326 to receive a third feedback control signal labeled "FC3[0:p-1]" from the control circuit 110. Additionally, the third impedance network 306 is coupled to a power supply terminal, such as a ground terminal.

In operation, control circuit 110 is adapted to selectively configure at least one of first, second, and third impedance networks 302, 304, and 306 to provide a desired impedance, thereby modifying the programmable The transfer function T _v (s) of the feedback circuit 108. An example of one possible embodiment of the first impedance network 302 is depicted in Figure 4 below. An example of another possible embodiment of the first impedance network 302 and an example of a possible embodiment of the second and third impedance networks 304 and 306 are depicted in Figure 5 below.

4 is a partial schematic and partial block diagram of a first embodiment of a first impedance network 400 in the programmable feedback circuit 108, such as the first impedance network 302 depicted in FIG. The first impedance network 400 includes a feedback input coupled to the voltage output 114 and includes a terminal 312. The first impedance network 400 also includes a first impedance 402 that includes a first terminal coupled to terminal 312 and a second terminal coupled to the feedback input via a feedback control switch 412. The first impedance network 400 also includes a second impedance 404 that includes a first terminal that is coupled to the terminal 312 and a second terminal that is coupled to the feedback input via a feedback control switch 414. Additionally, the first impedance network 400 includes a third impedance 406 that includes a first terminal coupled to terminal 312 and a second terminal coupled to the feedback input via feedback control switch 416.

In operation, control circuit 110 selectively activates one or more of switches 412, 414, and 416 to selectively connect one or more of impedances 402, 404, and 406 in parallel to produce the desired Impedance. While three impedances 402, 404, and 406 and associated switches 412, 414, and 416 are shown, it should be understood that any number of impedances and their associated switches can be used to achieve the desired impedance. Moreover, it should be understood that each of the impedances 402, 404, and 406 can include a resistor, a capacitor, or both, and control signals from the controller 110 can be used to selectively connect the impedances 402 in parallel. One or more of 404, 406, and 406 to produce the desired impedance.

Figure 5 is a second embodiment of a first impedance network 501 such as a first impedance network A block diagram of 302, and a block diagram of an embodiment of the second impedance network 304 and the third impedance network 306 of the programmable feedback circuit 108 depicted in FIG. The first impedance network 501 includes a feedback input coupled to the voltage output 114 of the LDO regulator circuit 100 depicted in FIG. 1 and includes a terminal 312 coupled to a feedback input in the second impedance network 304. The second impedance network 304 includes a feedback output 314 and a second terminal 316. The third impedance network 306 includes a feedback input coupled to the second terminal 316 and a second terminal coupled to the ground.

In the embodiment shown in FIG. 5, the first impedance network 501 includes resistors 502, 504, 506, 508, 510, 512, 514, and 516, capacitors 518, 520, 522, and 524, and a switch 526, 528, 530, 532, 534, 536, 538, and 540. Resistor 502 includes a first terminal connected to voltage output 114 and a second terminal connected to node 503. Resistors 504, 506, 508, 510, 512, and 514 are connected in series between node 503 and terminal 312. Capacitor 518 is connected in parallel with resistor 504. Capacitor 520 is connected in parallel with resistors 506, 508, and 510. Capacitor 522 is connected in parallel with resistors 512 and 514. Capacitor 524 is connected in parallel with resistor 516.

Each of the switches 526, 528, 530, 532, 534, 536, and 538 includes a first terminal connected to the node 503, a control terminal connected to the control circuit 110, and a second terminal. A second terminal of switch 526 is coupled to a second terminal of resistor 504. The second terminal of switch 528 is coupled to a first terminal of resistor 506 that is parallel to resistor 504 and one or more additional resistors and capacitors (not shown). The second terminal of switch 530 is coupled to a node between resistors 506 and 508. The second terminal of switch 532 is coupled to a node between resistors 508 and 510. A second terminal of the switch 534 is coupled to the resistor 510, And parallel to resistors 504, 506, 508, 510 and any intervening resistors, and parallel to capacitors 518, 520 and any intervening capacitors. The second terminal of switch 536 includes a first terminal connected to node 503 and a second terminal connected to resistor 512. Switch 538 includes a first terminal connected to node 503 and a second terminal connected to a node between resistors 512 and 514. Switch 540 includes a first terminal connected to node 503 and a second terminal connected to a node between resistors 514 and 516.

In operation, each of the switches 526, 528, 530, 532, 534, 536, 538, and 540 is configured to receive a control signal from the control circuit 110 to selectively bypass the resistors 504, 506, 508 One or more of 510, 512, and 514 and capacitors 518, 520, and 522 to achieve the desired impedance.

The second impedance network 304 includes an input coupled to terminal 312, a feedback output 314 coupled to the input of error amplifier 104, and a terminal 316 coupled to the input of third impedance network 306. The second impedance network 304 also includes a plurality of impedances 542, 544, 546, and 548 (and optionally other similar impedances, which are not represented in FIG. 5) that are connected in series at terminal 312 and terminal 316. between. Additionally, the second impedance network 304 includes a plurality of switches 550, 552, 554, 556, 558, and 560 (and optionally other similar switches, which are not shown in FIG. 5). Each of the plurality of switches 550, 552, 554, 556, and 558 includes a first electrode coupled to the feedback output 314, a control input coupled to the control circuit 110, and a second electrode. Switch 550 includes a second electrode that is coupled to a node between terminal 312 and impedance 542. Switches 552 and 554 include a connection to a different node between impedance 542 and impedance 544. Two electrodes. Switch 556 includes a second electrode that is coupled to a node between impedances 544 and 546. Switches 558 and 560 include a second electrode that is coupled to a different node between impedances 546 and 548. Switch 562 includes a second electrode that is coupled to a node between impedance 548 and terminal 316.

In operation, control circuit 110 applies one or more second feedback control signals to a plurality of switches 550, 552, 554, 556, 558, 560, and 562 to selectively adjust the impedance between terminals 312 and 316. And the impedance between terminals 312 and 316 and feedback output 314.

The third impedance network 306 includes an input connected to terminal 316 and an output connected to ground. The third impedance network 306 includes a plurality of impedances 570, 572, 574, and 576 that are connected in series between the terminal 316 and the ground. The third impedance network 306 also includes a plurality of switches 578, 580, 582, and 584, each of which is coupled in parallel with a respective one of the plurality of impedances 570, 572, 574, and 576. Each of the plurality of switches 578, 580, 582, and 584 is responsive to control circuitry 110 (depicted in FIG. 1) to selectively bypass a respective one or more of the impedances to control a third The effective impedance of impedance network 306. In operation, control circuit 110 is configured to program each of the first, second, and third impedance networks 501, 304, and 306 to provide the desired feedback impedance that can be used The output voltage of the LDO regulator 100 is trimmed digitally.

The implementation of digital trimming of 150mA LDO regulators with non-volatile MOS technology. The circuit has a grain size similar to that of a conventional LDO regulator based on fuse melting trimming techniques, ie, small enough to fit into a small outline transistor package, such as an SC-70 or other small form factor package. In such an implementation having eight control bits for fine-tuning the output voltage (V _OUT ), the LDO regulator is characterized by a programmable program for configuring the first impedance network 501 (or the input stage of the feedback loop) The bits, and the programmable bits used to configure the second and third impedance networks 304 and 306 (or the output stage of the feedback loop) for high resolution adjustment. As previously discussed, the LDO regulator circuit 100 includes a non-volatile register for storing control bits (such as the non-volatile register 204 of FIG. 2) configured to configure programmable feedback. Circuit 108 is to achieve a target output voltage value.

In a particular example, by controlling the impedance networks 501, 304, and 306, the DC output voltage of the LDO regulator can be fine-tuned with a step compensation of 10 mV. The initial range of the 300 mV output voltage (V _OUT ) can be reduced to 100 mV after digital trimming. In addition, most of the circuits can be adjusted to a target voltage in the range of 20 mV centered at 2.5 V in increments of 10 mV. The distribution of values before and after fine tuning is shown in Figures 6 and 7, respectively.

6 is a diagram 600 depicting the output voltage of a large number of tested portions prior to trimming using an LDO regulator circuit such as the LDO regulator circuit 100 depicted in FIG. Prior to fine tuning, graph 600 indicates that the output voltage ( _VOUT ) has a value ranging from about 2.35V to about 2.64V with respect to a target voltage of about 2.5V.

7 is a diagram 700 depicting the output voltage of a large number of tested portions after fine tuning using an LDO regulator circuit such as the LDO regulator circuit 100 depicted in FIG. In the illustrated diagram 700, most of the output voltage with respect to the portion being tested is in the range of 20 mV centered at a target voltage of 2.5V.

Compared to metal-fused fuse technology, the digital trimming mechanism offers the advantage of multiple flexible programming at the wafer level and after assembly as needed. This stylization capability eliminates the potential shifts that may occur after packaging and provides flexibility in setting the final configuration of the circuit.

While the precise fine-tuning of the output level during the production test flow is one of the most important applications of the voltage regulator's digital stylization capabilities, the stylization capabilities of the user mode are also useful for efficient power management. For example, portable transceivers can use a variety of output power levels for near or long range transmission, thereby mitigating the trade-off between power consumption and communication quality. Even when the battery power supply is discharged below its rated output value, assuming that the portable application supports low-power, low-voltage operation, the battery power can still be carried in the port by adjusting the LDO regulator 100 to a lower output level. Used in applications.

The digital trimming of the programmable feedback circuit also provides means for adjusting the frequency compensation mechanism of the LDO. Therefore, a simplified mode is envisioned in which the first impedance network is equivalent to the impedance of the resistor R _C and the capacitor C _C that are connected in parallel, and these components introduce zeros and poles that contribute to the global stability of the LDO system. The zero is related to the product of R _C and C _C , and the pole is related to C _C and the equivalent impedance at node 312 of the feedback network. When the first impedance is programmed, the configuration of the impedance network changes, thereby changing the values of R _C and C _C in the equivalent model, thereby adjusting the position of the zero and pole introduced by R _C and C _C And corrected the AC activity of the LDO.

In addition to programming the programmable feedback circuit 108, the programmable voltage reference circuit 102 is also programmable. In particular, the programmable voltage Reference circuit 102 can provide a voltage mode bandgap reference as depicted in Figure 8, or a current mode bandgap reference as depicted in Figure 11 below.

8 is a schematic diagram of an embodiment of a voltage mode bandgap reference circuit 800, which is one possible implementation of the programmable voltage reference circuit 102 depicted in FIG. The voltage mode bandgap reference circuit includes a PMOS transistor 802 having a source electrode connected to a power supply terminal, a gate electrode, and a drain electrode connected to the reference output 103 to provide a bandgap reference voltage (V _BGV ). In addition, the voltage mode bandgap reference circuit includes an amplifier 804 having a first input coupled to a first terminal of a resistor 806 having a second terminal coupled to a reference output 103. The first terminal of resistor 806 is also coupled to a first terminal of resistor 808 having a second terminal coupled to a transmit electrode in PNP bipolar junction transistor 810. The transistor 810 includes a base electrode and a collector electrode connected to the ground.

The amplifier 804 also includes a second input coupled to a first terminal of the resistor 812 having a second terminal coupled to the reference output 103. A first terminal of resistor 812 is coupled to the emitter electrode of PNP bipolar junction transistor 814. The transistor 814 includes a base electrode and a collector electrode connected to the ground.

In the illustrated embodiment, the temperature coefficient of the reference voltage (V _BGV ) can be fine tuned using a digital signal from control circuit 110 to select an appropriate ratio for the resistor. In particular, the bandgap reference voltage (V _BGV ) on the reference output 103 is related to the base-emitter voltage (V _EB ) of the transistor 814 plus a temperature component, as indicated below in Equation 1.

In Equation 1, the variable (V _T ) represents the thermal voltage of the circuit. The bandgap voltage (V _BGV ) is related to the ratio of the thermal voltage (V _T ) to the resistor. The bandgap voltage (V _BGV ) can be selectively determined based on the base-emitter voltage (V _EB ) of the transistor 810 plus a temperature component, as indicated below in Equation 2:

The two sides of Equation 1 are derived to obtain Equation 3 below, which describes the partial derivative.

coefficient The thermal variation of the voltage drop across the emitter-base forward bias junction of PNP transistor 814 is shown. Therefore, Equation 3 indicates that the thermal compensation of the bandgap voltage reference (V _BGV ) can be adjusted by modifying the ratio of the resistor and the ratio of the emitter region of the bipolar transistor. Imagine that when the Kelvin temperature is T=300 degrees, there is Typical thermal changes and The thermal change can then select (or program) the resistance value of the resistors 806, 808, and 812 and the ratio n of the emitter region such that the bias of the bandgap voltage as a function of temperature is reduced to approximately zero, as follows Shown in Equation 4.

Thus, the programmable voltage reference circuit 102 is implemented as a bandgap voltage reference circuit as depicted in Figure 8, which achieves first order thermal compensation.

Although the resistance of the resistor can be adjusted or fixed during manufacturing, other techniques can use a programmable resistive network or a programmable floating gate transistor to program the impedance of the programmable voltage regulator circuit. Chemical. One possible example of a programmable resistive network is depicted in FIG. 9, which can be used with the programmable voltage reference circuit 102 of FIG.

9 is a schematic diagram of an embodiment of a resistive network 900 that can be used in place of resistor 812 in the voltage mode bandgap reference circuit of FIG. Resistive network 900 includes a plurality of resistors 902, 904, 906, and 908 connected in series. In addition, the resistive network 900 includes a plurality of switches 910, 912, 914, 916, 918, 920, and 922, each of which has a first current electrode coupled between the two of the resistors, and Connected to the second current electrode of the reference output 103. Each of the plurality of switches 910, 912, 914, 916, 918, 920, and 922 can be independently configured by the control circuit 110 to selectively pass the reference output 103 via the plurality of switches 910, 912, 914 At least one of 916, 918, 920, and 922 is coupled to the interconnect node between resistors 902, 904, 906, and 908, thus implementing a programmable mechanism for adjusting the reference voltage (V _REF ) as a function of temperature.

In general, when the temperature coefficient of the reference voltage is zero, the compensation temperature T _{C is} selected at the center of the operating temperature range in order to minimize variations in all actual temperatures. An example of reference voltage thermal compensation is shown in FIG. 10, which shows the operation of the first order thermal compensation provided by resistive network 900 at different temperatures and different reference voltages.

10 is a diagram 1000 depicting thermal compensation of reference voltages for different values of the voltage mode bandgap reference circuit of FIG. Graph 1000 shows a first line 1002 indicating a first order compensation of the reference voltage at approximately -40 degrees Celsius. The equation 1000 also depicts a second line 1004 indicating a first order compensation of the reference voltage at approximately 40 degrees Celsius. Line 1006 indicates the first order compensation of the reference voltage at approximately 120 degrees Celsius. As depicted in FIG. 10, thermal compensation can be adjusted by programming the resistive network depicted in FIG. 9, such that the programmable voltage reference circuit 102 produces a reference voltage having the desired voltage. The thermal coefficient, and at least in the first order, is compensated for the required operating parameters.

Although the embodiment of the programmable voltage reference circuit 102 depicted in FIG. 8 provides a voltage mode bandgap reference, it may sometimes be desirable to implement the programmable voltage reference circuit 102 as a current mode bandgap reference. The current mode bandgap reference structure maintains functional characteristics at a lower voltage supply level than the voltage supply level required for the voltage mode structure, and conveniently produces a low level reference voltage by providing a reference current across the resistor. A similar digital trimming technique can be applied to adjust the thermal coefficient of the reference voltage generated by the current mode bandgap reference. One possible example of such a current mode bandgap reference implementation of the programmable voltage reference circuit 102 is depicted in FIG.

11 is a schematic diagram of an embodiment of a current mode voltage reference circuit 1100, which is another possible implementation of the programmable voltage reference circuit 102 depicted in FIG. The current mode reference circuit 1100 includes PMOS transistors 1102, 1104, and 1106 having a common source electrode connected to a voltage supply terminal (V _DD ) and having a common gate electrode. The drain electrode of PMOS transistor 1102 is coupled to a first input of amplifier 804 and is coupled to ground via resistor 1110 and via resistor 1112 in series with PNP transistor 814. The drain electrode of PMOS transistor 1104 is coupled to the second input of amplifier 804 and is coupled to ground via resistor 1118 and via PNP transistor 810. The drain electrode of the PMOS transistor 1106 is connected to the reference output 103 and is connected to the ground via a resistor 1120.

In operation, when the first current (I ₁ ) on the germanium electrode of the PMOS transistor 1102 is equal to the second current (I ₂ ) on the germanium electrode of the PMOS transistor 1104, and when the resistors 1110 and 1118 are substantially equal The bandgap reference voltage (V _BGI ) generated by the source current (I ₃ ) on the resistor 1120 can be expressed according to Equation 5 below.

Furthermore, the two-sided derivative display of Equation 5 achieves the first-order temperature compensation as shown in Equation 6.

In an alternative embodiment, an additional resistor is provided to the amplifier The input of 804 is between the drains of PMOS transistors 1102 and 1104. In one example, the additional resistor can be part of an impedance network that responds to control signals from control circuit 10 to provide an adjustable impedance. Additionally, any or all of resistors 1110, 1112, 1118, and 1120 (or any other impedance, not shown) may be implemented as a switchable impedance network.

In some cases, it may be desirable to provide a fast start selection for quickly generating a reference voltage (V _REF ). In particular, by placing a capacitor on the V _REF output, sometimes a capacitor can be used to reduce output noise. In such a case, the capacitor should be quickly charged to prepare for a quick start selection. However, in low power environments, low current is preferred for operating the voltage reference and increasing the current provided at the output of the reference circuit, which can result in exceeding the maximum allowable current draw. It is also possible to provide this fast start function without changing the bias current of the current mode reference. An example of such a circuit is described below with respect to FIG.

12 is a schematic diagram of a second embodiment of current mode voltage reference circuit 1200, which is another possible implementation of programmable voltage reference circuit 102 depicted in FIG. Circuit 1200 is similar to circuit 1100 in FIG. 11 except that PMOS transistor 1106 and resistor 1120 are omitted. Circuit 1200 provides both a fast turn-on time and an increased output current capability.

Circuit 1200 includes PMOS transistors 1202 and 1204 having a common source and gate that are coupled to the source and gate of PMOS transistor 1104, respectively. The circuit 1200 also includes an amplifier 1206 having a positive input coupled to the drain of the transistor 1202, an amplifier output 103, and a connection to the amplifier output. Negative input of 103. The transistor 1204 includes a drain connected to the amplifier output 103 and to the first terminal of the resistor 1210, the resistor 1210 having a second terminal. The circuit 1200 also includes a resistor 1208 having a first terminal connected to the positive input of the amplifier 1206, and a second terminal connected to the resistor 1210 and a second terminal connected to the first terminal of the resistor 1212, the resistor The 1212 has a second terminal connected to the ground. The value of resistor 1208 is more or less less than the value of resistor 1210 such that the operating voltage across resistor 1208 plus the input voltage offset of amplifier 1206 is less than the operating voltage across resistor 1210. In this example, the operating voltage is the steady state voltage after power up. In this example, resistor 1212 has an impedance that is much lower than resistors 1208 and 1210. In particular, the impedance of resistor 1212 is only a fraction of the impedance of resistors 1208 and 1210. In addition, amplifier 1206 provides current but does not sink current.

In contrast to circuit 1100, circuit 1200 has two current branches on the output stage that correspond to transistors 1202 and 1204. Based on the determination of the dimensions of transistors 1202 and 1204 relative to each other and relative to transistors 1102 and 1104, the current flowing through transistors 1202 and 1204 is controllable. Operating amplifier 1206 drives the voltage on amplifier output 103 to provide a quick start selection. Once the reference voltage (V _BGI ) on the amplifier output 103 matches the voltage on the positive input of the amplifier 1206, the amplifier 1206 no longer provides a fast start current. In addition, amplifier 1206 cooperates with transistors 1202 and 1204, and resistors 1208, 1210, and 1212 to adjust the reference voltage (V _REF ) without changing the temperature coefficient.

In the embodiment of Figures 11 and 12, and in Equations 5 and 6, the impedance of resistors 1110 and 1118 can be selected to achieve first order thermal compensation. In addition, in fact In an embodiment, resistors 1110 and 1118 can be implemented as a resistive network. In addition, resistors 1210 and 1212 in FIG. 12 can also be implemented as a resistive network, providing a means for quickly adjusting the voltage without incurring a change in the temperature coefficient of the voltage reference circuit. One possible example of many possible implementations from such a resistive network is shown below with respect to Figure 13, which can be programmed to achieve the desired resistance.

13 is a schematic diagram of an embodiment of a trimming circuit 1300 that can be used in place of one or both of the resistors 1110 and 1118 in accordance with an embodiment of the current mode voltage reference circuit of FIG. 11, or instead of including FIG. The current mode voltage reference circuit is any one of the resistors of the resistors 1208, 1210, and 1212. The trimming circuit 1300 includes a plurality of resistors 1302, 1304, and 1306 (and possibly other resistive elements therebetween, which are not shown in FIG. 13), the plurality of resistors being connected in series at the first terminal (H) is between the second terminal (L). The trimming circuit 1300 also includes an associated plurality of switches 1312, 1314, 1316, and 1318 (and possibly other switches therebetween, which are not shown in Figure 12), wherein each switch has a second connection a first current electrode of the terminal (L), a control electrode for receiving a digital signal from the control circuit 110, and a second current electrode connected to a node between two of the resistors.

In operation, each of the plurality of switches 1312, 1314, 1316, and 1318 can be independently controlled based on a digital signal from the control circuit 110 for adjusting the resistance of the trimming circuit. Replacing the resistor 1110 with a trimming circuit and also replacing the resistor 1118 makes it possible to digitally adjust the resistance of the current mode programmable voltage reference circuit 102 to provide thermal compensation. Similarly, instead of resistor 1212, a trimming circuit is implemented, which may fine tune the current mode bandgap reference voltage by digitally adjusting the values of resistor 1212 and/or other resistors in circuit 1200.

In this regard, the programmability of the programmable voltage reference circuit 102, the error amplifier 104, and the programmable feedback circuit 108 has been discussed. However, LDO regulator circuit 100 also allows for programming of transfer device 106. In a particular example, by implementing the transfer device 106 as the transistor network 1400 as depicted in FIG. 14, it is possible to adjust the DC performance and transient response of the programmable transfer device 106.

14 is a schematic diagram of an embodiment of a transistor network 1400 that can be used to implement the transfer device 106 in accordance with an embodiment of the LDO regulator circuit 100 of FIG. The transistor network 1400 includes a plurality of PMOS transistors 1402, 1404, and 1406 having a common source electrode coupled to the voltage terminal (V _IN ) and a common gate electrode coupled to the output 120 of the error amplifier 104. PMOS transistor 1402 includes a drain electrode of a source electrode of PMOS transistor 1408, the PMOS transistor 1408 includes a gate electrode that is selectively coupled to a voltage terminal (V _IN ) via switch 1410 or to ground via switch 1412 end. Additionally, PMOS transistor 1408 includes a germanium electrode coupled to voltage output 114.

The PMOS transistor 1404 includes a germanium electrode coupled to the source electrode of the PMOS transistor 1414, the PMOS transistor 1414 including a gate electrode that is selectively coupled to the voltage terminal (V _IN ) via the switch 1416 or via a switch 1418 To the ground. PMOS transistor 1414 also includes a germanium electrode that is coupled to voltage output 114.

PMOS transistor 1406 includes a germanium electrode connected to the source electrode of PMOS transistor 1420, which includes a gate electrode that is selectively coupled to voltage terminal (V _IN ) via switch 1422 or via switch 1424 To the ground. PMOS transistor 1420 also includes a germanium electrode that is coupled to voltage output 114.

Thus, in the illustrated embodiment, the programmable transfer device 106 is designed with a plurality of modules (a first module represented by a current path including transistors 1402 and 1408; a second module A current path representation of transistors 1404 and 1414 is included; and a third module, represented by current paths including transistors 1406 and 1420, are connected in parallel. By selectively applying control signals to switches 1410, 1412, 1416, 1418, 1422, and 1424, one or more of the current paths are disabled by interrupting the connection of the signal paths. This control signal is provided by control circuit 110 via transfer device control input 126. When a particular circuit application does not require a large current load, the transient response of the programmable voltage reference circuit 102 can be improved by disabling one or more modules, thereby reducing parasitic capacitance at the output and changing The transient response of the device 106 is passed.

Although the above discussion has provided examples of programmable voltage reference circuit 102, programmable transfer device 106, and programmable feedback circuit 108, it is contemplated that various possible implementations can be used to implement programmable error amplifier 104. . A possible example is described below with respect to Figure 15.

15 is a schematic diagram of an embodiment of one of many possible implementations of programmable error amplifier 104. The programmable error amplifier includes PMOS transistors 1502 and 1504 including a source electrode connected to a voltage supply terminal (V _DD ) and a gate electrode connected to a common node. The transistor 1502 includes a germanium electrode connected to the gate electrode of the transistor 1502 and to the germanium electrodes of the NMOS transistors 1506 and 1510 having a common gate electrode to which the gate electrode is connected A positive input terminal (INP) is coupled to the feedback output 105 to receive a feedback signal (V _F ) from the programmable feedback circuit 108 depicted in FIG. The NMOS transistor 1506 also includes a source electrode coupled to the drain electrode of the NMOS transistor 1508, the NMOS transistor 1508 including a control electrode coupled to the first control input (OC1), and a source coupled to the bias current source 1520 electrode. NMOS transistor 1510 includes a source electrode that is coupled to bias current source 1520.

PMOS transistor 1504 includes a germanium electrode coupled to amplifier output 120 and to germanium electrodes of NMOS transistors 1518 and 1512 having gate electrodes connected to a negative input terminal (INN), A negative input terminal (INN) is coupled to voltage reference input 103 to receive a reference voltage (V _REF ) from the programmable voltage reference circuit 102 depicted in FIG. NMOS transistor 1518 includes a source electrode that is coupled to bias current source 1520. The NMOS transistor 1512 includes a source electrode coupled to the drain electrode of the NMOS transistor 1514, the NMOS transistor 1514 including a gate electrode coupled to the second control input (OC2) and including a source electrode coupled to the bias current source 1520 . First and second control inputs (OC1 and OC2) are coupled to amplifier control input 124 to receive an amplifier control signal from control circuit 110.

In operation, the reference voltage (VREF) on the negative input (INN) and the feedback voltage (VF) on the positive input (INP) enable the transistors 1510 and 1518 to allow current to flow to produce an amplifier output signal on the amplifier output 120, Its table The difference between VREF and VF is shown. Transistors 1508 and 1514 are responsive to control signals on amplifier control input 124 to enable or disable current paths through transistors 1506 and 1512, thereby adjusting the current flowing through one or both of the current paths. Thus, control circuit 110 selectively activates transistors 1506 and 1512 using control signals to facilitate the gain of the differential inputs, turning transistors 1508 and 1514 on or off as needed.

It will be appreciated that the LDO regulator circuit discussed above with respect to Figures 1-15 can be configured to be part of a test process implemented by the manufacturer where the input voltage is applied to the input of the LDO regulator and configured Data is provided to the LDO regulator via serial interface 112, which is stored in non-volatile memory such as non-volatile registers 204. The configuration data can be decoded using control logic 206 to generate control signals for configuring adjustment functions for any or all of programmable voltage reference circuit 102, amplifier 104, transfer device 106, and programmable feedback circuit 108. .

In addition, the serial interface 112 can be accessed via the host system and control circuitry to update and replace all or a portion of the configuration data at any time. In an embodiment, the control logic 206 decodes the configuration data to generate a control signal upon receipt of the configuration data into the configuration register or after the configuration data is stored in the non-volatile memory, and Applying control signals to any or all of the programmable voltage reference circuit 102, the amplifier 104, the transfer device 106, and the programmable feedback circuit 108 to immediately adjust the adjustment function (eg, output voltage level, frequency parameter, static) Current limit, or other parameters of the output voltage). In another embodiment, the control logic 206 decodes the configuration data at startup and until the next startup event, the configuration data Any changes are stored in non-volatile memory. In still another embodiment, control logic 206 decodes the configuration data in response to commands received via serial interface 112.

In conjunction with the embodiments disclosed above with respect to Figures 1-15, a programmable LDO regulator 100 is disclosed that includes a programmable voltage reference circuit 102, a programmable error amplifier 104, a programmable transfer device 106, and a programmable feedback Circuit 108. In addition, the programmable LDO regulator 100 includes a serial interface 112 and a control circuit 110 that makes it possible to program the programmable LDO regulator 100 multiple times to adjust a number of parameters to control the output voltage (V _OUT ) DC And AC two parameters. The settings for the programmable voltage reference circuit 102, the programmable error amplifier 104, the programmable transfer device 106, and the programmable feedback circuit 108 can be stored in the non-volatile registers 204. Thus, the programmable LDO regulator can be configured to provide an output voltage having the desired level and having the desired DC and AC characteristics. Furthermore, by providing a serial interface, the LDO regulator circuit can be programmed digitally, multiple times, during manufacturing and testing, and during operation, the serial interface configurable to receive digital configuration including Control information for data (such as binary sequences).

According to one aspect, an LDO regulator circuit includes an error amplifier having first, second, third, fourth, fifth, and sixth transistors, and first and second switches. The first transistor includes a source coupled to the power supply terminal, a gate, and a drain coupled to the control electrode. The second transistor includes a source coupled to the power supply terminal, a gate coupled to the control terminal of the first transistor, and a drain coupled to the error amplifier output. The third transistor includes: a drain coupled to the drain of the first transistor; a gate coupled And to a feedback output terminal; and a source coupled to the bias current source. The fourth transistor includes a drain coupled to the drain of the second transistor, a gate coupled to the reference output, and a source coupled to the bias current source. The fifth transistor includes a drain coupled to the drain of the third transistor, a gate coupled to the feedback output terminal, and a source. The sixth transistor includes a drain coupled to the drain of the fourth transistor, a gate coupled to the reference output, and a source. A first switch is coupled between the source of the fifth transistor and the bias current source and includes a control terminal coupled to the control circuit. A second switch is coupled between the source of the sixth transistor and the bias current source and includes a control terminal coupled to the control circuit.

In another aspect, the LDO circuit includes a voltage reference including first, second, and third resistive elements, first and second diode connected devices, control circuitry, amplifiers, and PMOS transistors. The PMOS transistor includes a first electrode coupled to a voltage input, a second electrode coupled to a reference output, and a control electrode. The first resistive element includes a first terminal coupled to the reference output and a second terminal. The second resistive element includes a first terminal coupled to the reference output and a second terminal. The amplifier includes a first amplifier input coupled to the second terminal of the first resistive element, a second amplifier input coupled to the second terminal of the second resistive element, and an amplifier output coupled to the PMOS control electrode. The third resistive element includes a first terminal coupled to the first amplifier input and a second terminal. The first diode connection device includes a first terminal coupled to the second terminal of the third resistive network and a second terminal coupled to the power supply terminal. The second diode connection device includes: a first terminal coupled to the second amplifier An input; and a second terminal coupled to the power supply terminal. The control circuit is configurable to program the resistance associated with at least one of the first, second, and third resistive elements to control the thermal or nominal level of the reference voltage.

In another aspect, an LDO regulator includes a voltage reference including first and second PMOS transistors, first, second, and third resistive elements, an amplifier, and a control circuit. Each of the first and second PMOS transistors includes a first electrode coupled to the voltage input, a control electrode coupled to the common node, and a second electrode. The amplifier includes a positive input coupled to the second electrode of the first PMOS transistor, a negative input, and an output coupled to the second electrode of the second PMOS transistor. The first resistive element includes a first terminal coupled to the positive input and a second electrode of the first PMOS transistor and including a second terminal. The second resistive element includes a first terminal coupled to the second terminal of the first resistive element and a second terminal coupled to the ground. The third resistive element includes a first terminal coupled to the output of the amplifier and a second terminal coupled to the first terminal of the second resistive element. The control circuit can be configured to program a resistor associated with at least one of the first, second, and third resistive elements to control a nominal level of the reference voltage at the output of the amplifier.

Still on the other hand, LDO regulators include: voltage regulators, transfer devices, feedback circuits, and error amplifiers. The LDO regulator also includes a control circuit with: non-volatile memory configurable to store configuration data; and logic configured to decode the configuration data into control signals for Digitally stylizing at least one of a voltage regulator, a transfer device, a feedback circuit, and an error amplifier to control the voltage The adjustment function on the output.

In certain instances, the LDO regulator includes a programmable reference circuit that is responsive to at least a first control signal. The first control signal includes one or more first reference control signals and one or more second reference control signals. The programmable reference circuit includes a transistor including: a first current electrode coupled to the voltage input; a second current electrode; and a control electrode. The programmable reference circuit also includes an amplifier, and first and second resistor networks. The amplifier includes a first amplifier input, a second amplifier input, and an amplifier output coupled to the control electrode of the transistor. A first resistor network is coupled to the first amplifier input and responsive to the one or more first reference control signals to provide a first resistance. A second resistor network is coupled to the second amplifier input and responsive to the one or more second reference control signals to provide a second resistor.

In another specific case, the LDO regulator includes a feedback circuit that includes at least one programmable impedance network. The programmable impedance network responds to the fourth control signal to adjust the impedance. In a particular case, the programmable impedance network includes: a plurality of resistors coupled in a series configuration; a plurality of capacitors coupled in a series configuration and interconnected with a plurality of resistors; A plurality of switches responsive to the fourth control signal to change a complex impedance associated with the at least one programmable impedance network. Moreover, in some cases, the LDO regulator includes a programmable transfer device that provides current at the voltage output terminals. The control circuit is configured to selectively enable the adaptive biasing feature to configure the critical level of the overcurrent protection associated with the voltage output and to configure the error amplifier to adjust the amplifier offset.

In still another aspect, the LDO regulator includes a serial interface that can be grouped The state is coupled to the serial connector and is adapted to send and receive data and commands to the external device via the serial connector. The LDO regulator further includes a control circuit coupled to the serial interface to receive configuration data and adapted to configure a programmable reference circuit, a programmable error amplifier, and a programmable transfer based on the configuration data Devices, and programmable feedback circuits.

In another particular aspect, a method of providing an output voltage using a programmable low dropout (LDO) regulator includes receiving configuration data from a control circuit via a serial interface of an LDO regulator and storing the configuration data Into non-volatile memory. The method also includes decoding configuration data using a control logic of an LDO regulator control circuit to configure a programmable reference circuit, a programmable error amplifier, a programmable transfer device, and a programmable feedback circuit An adjustment function of at least one of the ones to generate an output voltage.

In one case, the control signal includes at least a first control signal, at least a second control signal, at least a third control signal, and at least a fourth control signal. In a specific case, after decoding the configuration data, the method further comprises: receiving a voltage input signal at an input of the LDO regulator; generating a reference voltage using a programmable reference circuit configured according to the at least one first control signal And adjusting the voltage input signal using a serial transfer device coupled to the input and configured in accordance with the at least one second control signal to produce an output voltage at the output terminal. Additionally, the method includes: sampling the output voltage using a programmable feedback circuit configured in accordance with the at least one third control signal to generate a feedback voltage; and using a programmable error amplifier configured in accordance with the at least one fourth control signal To carry out the feedback voltage and the reference voltage In comparison, an error signal is generated at the amplifier output of the error amplifier, the amplifier output being coupled to the tandem transfer device to adjust the output voltage.

In another special case, the method includes: receiving the second configuration data via the serial interface; storing the second configuration data in non-volatile memory; and decoding the second configuration data using the control logic To generate a second control signal. The second control signal is applied to adjust an adjustment function of at least one of the programmable reference circuit, the programmable error amplifier, the programmable transfer device, and the programmable feedback circuit to generate an output voltage.

Although the present invention has been described in terms of the preferred embodiments, it will be understood by those skilled in the art that

100‧‧‧ Low dropout (LDO) regulator circuit

102‧‧‧Programmable voltage reference circuit

103‧‧‧Output terminal

104‧‧‧Programmable error amplifier

105‧‧‧Feedback output

106‧‧‧Programmable transfer device

108‧‧‧Programmable feedback circuit

110‧‧‧Control circuit

112‧‧‧Serial interface

114‧‧‧Output terminal

116‧‧‧load

120‧‧‧Amplifier output

122‧‧‧Reference control input

124‧‧‧Amplifier Control Input

126‧‧‧Transfer device control input

128‧‧‧Feedback control input

130‧‧‧Control Information

132‧‧‧Information

200‧‧‧LDO regulator circuit

202‧‧‧Volatile configuration register

204‧‧‧Non-volatile register

206‧‧‧Control logic

302‧‧‧First impedance network (or input stage)

304‧‧‧Second impedance network (or output stage)

306‧‧‧ Third impedance network (or output stage)

312‧‧‧ Terminal

314‧‧‧Feedback output (V _OUTF )

316‧‧‧ terminals

322‧‧‧First feedback control input

324‧‧‧Second feedback control input

326‧‧‧ Third feedback control input

400‧‧‧First impedance network

402‧‧‧First impedance

404‧‧‧second impedance

406‧‧‧ third impedance

412‧‧‧Feedback control switch

414‧‧‧Feedback control switch

416‧‧‧Feedback control switch

501‧‧‧First impedance network

502‧‧‧Resistors

503‧‧‧ nodes

504‧‧‧Resistors

506‧‧‧Resistors

508‧‧‧Resistors

510‧‧‧Resistors

512‧‧‧Resistors

514‧‧‧Resistors

516‧‧‧Resistors

518‧‧‧ capacitor

520‧‧‧ capacitor

522‧‧‧ capacitor

524‧‧‧ capacitor

526‧‧‧ switch

528‧‧‧Switch

530‧‧‧Switch

532‧‧‧ switch

534‧‧‧Switch

536‧‧‧ switch

538‧‧‧Switch

540‧‧‧ switch

542‧‧‧ Impedance

544‧‧‧ Impedance

546‧‧‧ Impedance

548‧‧‧ Impedance

550‧‧‧ switch

552‧‧‧Switch

554‧‧‧Switch

556‧‧‧Switch

558‧‧‧Switch

560‧‧‧ switch

562‧‧‧ switch

570‧‧‧ Impedance

572‧‧‧ Impedance

574‧‧‧ Impedance

576‧‧‧ Impedance

578‧‧‧Switch

580‧‧‧Switch

582‧‧‧Switch

584‧‧‧ switch

600‧‧‧ Schematic diagram of the output voltage of a large number of tested parts before fine-tuning using the LDO regulator circuit

700‧‧‧A diagram of the output voltage of a large number of tested parts after fine-tuning using the LDO regulator circuit

800‧‧‧Voltage mode bandgap reference circuit

802‧‧‧ PMOS transistor

804‧‧‧Amplifier

806‧‧‧Resistors

808‧‧‧Resistors

810‧‧‧PNP bipolar junction transistor

812‧‧‧Resistors

814‧‧‧PNP bipolar junction transistor

900‧‧‧Resistive network

902‧‧‧Resistors

904‧‧‧Resistors

906‧‧‧Resistors

908‧‧‧Resistors

910‧‧‧ switch

912‧‧‧ switch

914‧‧‧ switch

916‧‧‧ switch

918‧‧‧Switch

920‧‧‧ switch

922‧‧‧ switch

1000‧‧‧A diagram of the thermal compensation of the reference voltage for different values of the voltage mode bandgap reference circuit in Figure 8.

1002‧‧‧ First-order compensation of reference voltage at approximately -40 degrees Celsius

1004‧‧‧ First-order compensation of reference voltage at approximately 40 degrees Celsius

1006‧‧‧First-order compensation of reference voltage at approximately 120 degrees Celsius

1100‧‧‧ Current mode voltage reference circuit

1102‧‧‧ PMOS transistor

1104‧‧‧ PMOS transistor

1106‧‧‧ PMOS transistor

1110‧‧‧Resistors

1112‧‧‧Resistors

1118‧‧‧Resistors

1120‧‧‧Resistors

1200‧‧‧current mode voltage reference circuit

1202‧‧‧ PMOS transistor

1204‧‧‧ PMOS transistor

1206‧‧Amplifier

1208‧‧‧Resistors

1210‧‧‧Resistors

1212‧‧‧Resistors

1300‧‧‧ trimming circuit

1302‧‧‧Resistors

1304‧‧‧Resistors

1306‧‧‧Resistors

1312‧‧‧Switch

1314‧‧‧Switch

1316‧‧‧ switch

1318‧‧‧Switch

1400‧‧‧Crystal network

1402‧‧‧ PMOS transistor

1404‧‧‧ PMOS transistor

1406‧‧‧ PMOS transistor

1408‧‧‧ PMOS transistor

1410‧‧‧Switch

1412‧‧‧Switch

1414‧‧‧ PMOS transistor

1416‧‧‧ switch

1418‧‧‧Switch

1420‧‧‧ PMOS transistor

1422‧‧‧Switch

1424‧‧‧Switch

1502‧‧‧ PMOS transistor

1504‧‧‧ PMOS transistor

1506‧‧‧NMOS transistor

1508‧‧‧NMOS transistor

1510‧‧‧NMOS transistor

1512‧‧‧NMOS transistor

1514‧‧‧NMOS transistor

1518‧‧‧NMOS transistor

1520‧‧‧ bias current source

1 is a partial schematic and partial block diagram of an embodiment of a programmable low dropout (LDO) regulator circuit; FIG. 2 is a partial schematic and partial block diagram of the programmable LDO regulator circuit of FIG. An expanded view of an embodiment of a control block; FIG. 3 is a block diagram of an embodiment of a feedback circuit of the LDO regulator of FIG. 1; and FIG. 4 is a portion of an embodiment of a first impedance network of the feedback circuit depicted in FIG. Schematic and partial block diagrams; FIG. 5 is a schematic diagram of a second embodiment of a first impedance network of the feedback circuit depicted in FIG. 3 and a second and third impedance network embodiment; FIG. A pattern of output voltages of several tested portions prior to trimming using an LDO regulator circuit such as the LDO regulator circuit depicted in FIG. 1; 7 is a diagram depicting output voltages of several tested portions after trimming using an LDO regulator circuit, such as the LDO regulator circuit depicted in FIG. 1; FIG. 8 is an implementation of a voltage mode bandgap reference circuit Example of an example of a possible implementation of the programmable voltage reference circuit depicted in FIG. 1; FIG. 9 is an embodiment of a programmable resistive network for the voltage mode bandgap reference circuit of FIG. Schematic diagram of FIG. 10 is a diagram illustrating thermal compensation of a reference voltage, the thermal compensation of which is the various resistance values of the resistors used in the voltage mode bandgap reference circuit of FIG. 8; A schematic diagram of an embodiment of a mode voltage reference circuit, which is a possible implementation of the programmable voltage reference circuit depicted in FIG. 1; FIG. 12 is a schematic diagram of a second embodiment of a current mode voltage reference circuit, which is FIG. Another possible implementation of the programmable voltage reference circuit depicted in FIG. 13 is an embodiment of a trimming circuit (programmable resistive network) in accordance with an embodiment of the current mode voltage reference circuit of FIGS. 11 and 12. Figure 14 is a schematic diagram of an embodiment of a programmable transfer device in accordance with an embodiment of the LDO regulator circuit of Figure 1; Figure 15 is a programmable error amplifier in accordance with an embodiment of the LDO regulator circuit of Figure 1. Schematic diagram of an embodiment; and in the following description, the same reference numerals are used in the different figures to indicate similar or identical items.

100‧‧‧ Low dropout (LDO) regulator circuit

102‧‧‧Programmable voltage reference circuit

103‧‧‧Output terminal

104‧‧‧Programmable error amplifier

105‧‧‧Feedback output

106‧‧‧Programmable transfer device

108‧‧‧Programmable feedback circuit

110‧‧‧Control circuit

112‧‧‧Serial interface

114‧‧‧Output terminal

116‧‧‧load

120‧‧‧Amplifier output

122‧‧‧Reference control input

124‧‧‧Amplifier Control Input

126‧‧‧Transfer device control input

128‧‧‧Feedback control input

130‧‧‧Control Information

132‧‧‧Information

Claims (10)

A low dropout (LDO) regulator comprising: a voltage reference circuit comprising a reference output for providing a reference voltage; a transfer device comprising an input terminal coupled to a voltage input for providing a a voltage output output terminal, and a control input; a feedback circuit including a feedback input terminal coupled to the output terminal, and a feedback output terminal; an error amplifier including one coupled to the reference output An error amplifier input, a second error amplifier input coupled to the feedback output terminal, and an error amplifier output coupled to the control input of the transfer device; and a control circuit configurable to selectively and independently Adjusting a first performance parameter associated with the voltage reference circuit, a second performance parameter associated with the transfer device, a third performance parameter associated with the feedback circuit, and a fourth associated with the error amplifier a performance parameter to programmatically program an adjustment function at the voltage output, wherein the first performance parameter includes an output Test voltage, wherein the second performance parameter comprises a transient response, wherein the performance parameter comprises a third feedback transfer function, and wherein the performance parameter comprises a fourth gain. The LDO regulator of claim 1, further comprising: a serial interface adapted to be coupled to an external source and configured to transmit data and control information to the external source and to receive data from the external source and Control information. The LDO regulator of claim 1, wherein the control circuit comprises: a configuration register that stores configuration data related to the voltage reference circuit, the transfer device, the feedback circuit, and the error amplifier; and a combination Logic for decoding the configuration data into a plurality of control signals, the control signals configuring the voltage reference circuit, the transfer device, the feedback circuit, and the error amplifier. The LDO regulator of claim 1, wherein the control circuit comprises: a non-volatile storage device configured to store configuration data related to the voltage reference circuit, the transfer device, the feedback circuit, and the error amplifier . The LDO regulator of claim 1, wherein the feedback circuit comprises at least one impedance network; and wherein the control circuit is configured to selectively adjust an impedance associated with the at least one impedance network. The LDO regulator of claim 1, wherein the transfer device comprises a transistor network; and wherein the control circuit enables a plurality of devices within the transistor network of the transfer device to adjust DC characteristics and a transient response. The LDO regulator of claim 1, wherein the control circuit is configured to selectively enable an adaptive biasing feature to control a quiescent current associated with the error amplifier. The LDO regulator of claim 1, wherein the control circuit is configured to selectively configure a threshold level for overcurrent protection associated with the voltage output. A low dropout (LDO) regulator comprising: a programmable reference circuit including a reference output and a control input configurable to generate a reference voltage at the reference output, and Adjusting a thermal coefficient or a nominal value of the reference voltage in response to the at least one first control signal at the control input; a programmable error amplifier comprising a first input coupled to the reference output, a first a two-input, an amplifier output, and a control input for receiving at least one second control signal to adjust at least one of an adaptive bias parameter, a short circuit protection parameter, and an offset parameter; a programmable transfer a device comprising a first terminal coupled to a voltage input, a second terminal coupled to the amplifier output, a control input configurable to receive at least a third control signal to adjust a load current, and Providing a voltage output output terminal; and a programmable feedback circuit including a first input coupled to the output terminal of the programmable transfer device, coupled The second one of the programmable feedback input terminal of the error amplifier, and can be configured to receive at least a fourth control signal to configure a feedback transfer function of one of the control input. A method for providing an output voltage using a programmable integrated circuit low dropout (LDO) regulator, the method comprising: receiving configuration data from a control circuit via a serial interface of the LDO regulator; The state data is stored in a non-volatile memory; and the control logic of one of the LDO regulators is used to decode the configuration data to generate a plurality of control signals for independent configuration and a first performance parameter associated with the stylized reference circuit, a second performance parameter associated with a programmable error amplifier, a third performance parameter associated with a programmable transfer device, and a programmable a fourth performance parameter associated with the feedback circuit to generate the output voltage, wherein the first performance parameter includes an output reference voltage, wherein the second performance parameter includes a gain, wherein the third performance parameter includes a transient response, and The fourth performance parameter includes a feedback transfer function.