CN101093401A - Bandgap Voltage Reference Circuit - Google Patents
Bandgap Voltage Reference Circuit Download PDFInfo
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Abstract
Description
技术领域technical field
本发明有关于参考电路,特别有关一种能带隙电压参考电路,能够提供不受开关元件的有限导通电阻(finite turn-on resistance)与温度系数影响的参考电压。The present invention relates to a reference circuit, in particular to a bandgap voltage reference circuit capable of providing a reference voltage not affected by finite turn-on resistance and temperature coefficient of switching elements.
背景技术Background technique
一般而言,电压参考电路与电流参考电路广泛地使用于模拟电路中,此类参考电路是以直流电压或电流为主,受电源与制程参数的影响不大,而且对温度变化会有符合一预定的相依性。举例而言,能带隙电压参考电路是最常用的高效率电压参考电路,其使用具有正温度系数与负温度系数特性的元件,再将这些元件产生的电压或电流依照一既定比例予以加总,以便产生与温度无关的输出作为一参考电流或电流。Generally speaking, voltage reference circuits and current reference circuits are widely used in analog circuits. This type of reference circuit is mainly based on DC voltage or current, which is not greatly affected by power supply and process parameters, and will be consistent with temperature changes. predetermined dependencies. For example, the bandgap voltage reference circuit is the most commonly used high-efficiency voltage reference circuit, which uses elements with positive temperature coefficient and negative temperature coefficient characteristics, and then sums the voltage or current generated by these elements according to a predetermined ratio , in order to generate a temperature-independent output as a reference current or current.
发明内容Contents of the invention
本发明提供一种能带隙电压参考电路,包括一运算放大器具有一输出端以及第一、第二输入端;第一、第二二极管形式连接的晶体管耦接至运算放大器;一第一电阻耦接于运算放大器的输出端与第一二极管形式连接的晶体管之间;以及一第一电阻梯(resistor ladder)耦接于运算放大器的输出端与第二二极管形式连接的晶体管之间,而第一电阻梯包括串联地连接的复数第二电阻;以及复数开关元件,各具有一第一端耦接至运算放大器的第一输入端。The present invention provides a bandgap voltage reference circuit, comprising an operational amplifier having an output terminal and first and second input terminals; first and second diode-connected transistors coupled to the operational amplifier; a first a resistor coupled between the output terminal of the operational amplifier and the first diode-connected transistor; and a first resistor ladder (resistor ladder) coupled between the output terminal of the operational amplifier and the second diode-connected transistor between, and the first resistor ladder includes a plurality of second resistors connected in series; and a plurality of switching elements, each having a first end coupled to the first input end of the operational amplifier.
本发明还提供一种能带隙电压参考电路,包括一运算放大器具有一输出端以及第一、第二输入端;第一、第二二极管形式连接的晶体管分别耦接至运算放大器的第一、第二输入端;一第一电阻具有一第一端耦接于运算放大器的输出端,以及一第二端耦接第一二极管形式连接的晶体管与运算放大器的第一输入端;以及一第一电阻梯(resistor ladder),耦接于运算放大器的输出端与第二二极管形式连接的晶体管之间,而第一电阻梯包括串联地连接的复数第二电阻;以及复数开关元件,各具有一第一端耦接至一高阻抗路径,其中开关元件是由一第一组控制信号所控制,使得部分的第二电阻会形成一第一等效电阻,而剩余的第二电阻会形成一第二等效电阻。The present invention also provides a bandgap voltage reference circuit, comprising an operational amplifier having an output terminal and first and second input terminals; the first and second diode-connected transistors are respectively coupled to the first operational amplifier. 1. The second input terminal; a first resistor has a first terminal coupled to the output terminal of the operational amplifier, and a second terminal coupled to the first diode-connected transistor and the first input terminal of the operational amplifier; and a first resistor ladder (resistor ladder), coupled between the output terminal of the operational amplifier and the second diode-connected transistor, and the first resistor ladder includes a plurality of second resistors connected in series; and a plurality of switches elements, each having a first end coupled to a high impedance path, wherein the switch element is controlled by a first set of control signals, so that part of the second resistance will form a first equivalent resistance, and the remaining second The resistance forms a second equivalent resistance.
本发明还提供一种能带隙电压参考电路,包括一运算放大器具有一输出端以及第一、第二输入端;第一、第二晶体管耦接至运算放大器;一第一电阻耦接于运算放大器的输出端与第一晶体管之间;以及一第一电阻梯耦接于运算放大器的输出端与第二晶体管之间,而第一电阻梯包括串联地连接的复数第二电阻,以及复数开关元件各具有一第一端耦接至一高阻抗路径。The present invention also provides a bandgap voltage reference circuit, comprising an operational amplifier having an output terminal and first and second input terminals; the first and second transistors are coupled to the operational amplifier; a first resistor is coupled to the operational amplifier between the output terminal of the amplifier and the first transistor; and a first resistor ladder coupled between the output terminal of the operational amplifier and the second transistor, and the first resistor ladder includes a plurality of second resistors connected in series, and a plurality of switches Each element has a first end coupled to a high impedance path.
本发明提供的能带隙电压参考电路,能够提供不受开关元件的有限导通电阻(finite turn-on resistance)与温度系数影响的参考电压。The bandgap voltage reference circuit provided by the present invention can provide a reference voltage not affected by the finite turn-on resistance (finite turn-on resistance) and temperature coefficient of the switch element.
附图说明Description of drawings
图1为本发明中能带隙电压参考电路的一实施例。FIG. 1 is an embodiment of a bandgap voltage reference circuit in the present invention.
图2为本发明中电阻梯的一实施例。Fig. 2 is an embodiment of the resistance ladder in the present invention.
图3为本发明中能带隙电压参考电路的另一实施例。FIG. 3 is another embodiment of the bandgap voltage reference circuit in the present invention.
图4为本发明中能带隙电压参考电路的另一实施例。FIG. 4 is another embodiment of the bandgap voltage reference circuit in the present invention.
附图标号:Figure number:
10A、20、30:能带隙电压参考电路;10A, 20, 30: bandgap voltage reference circuit;
22、24:电阻梯;22, 24: resistance ladder;
OP:运算放大器;OP: operational amplifier;
Q1、Q2:双载子晶体管;Q1, Q2: bipolar transistors;
V1~V2:电压;V1~V2: Voltage;
GND:接地电压;GND: ground voltage;
I1、I2:电流;I1, I2: current;
Vbg、Vbg”:输出电压;Vbg, Vbg": output voltage;
ND20~ND2M、ND30~ND3Z:节点;ND20~ND2M, ND30~ND3Z: nodes;
R1~R3、R3 1~R3N、RX1~RXN、R41~R4Y:电阻;R1~R3, R3 1~R3N, RX1~RXN, R41~R4Y: resistance;
SW10~SW1A、SW20~SW2M、SW30~SW3Z:开关元件。SW10~SW1A, SW20~SW2M, SW30~SW3Z: switching elements.
具体实施方式Detailed ways
为了让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举一较佳实施例,并配合附图,作详细说明如下:In order to make the above-mentioned and other objects, features, and advantages of the present invention more obvious and understandable, a preferred embodiment is specifically cited below, together with the accompanying drawings, and is described in detail as follows:
图1为显示本发明中能带隙电压参考电路的一实施例。如图所示,能带隙电压参考电路10A包括运算放大器OP、双载子晶体管(BJTs)Q1与Q2,以及电阻R1~R3。举例而言,电阻R1与R2具有相同的电阻值,而晶体管Q2的射极的面积是N倍于晶体管Q1的射极的面积,N大于1。FIG. 1 shows an embodiment of a bandgap voltage reference circuit in the present invention. As shown in the figure, the bandgap
若忽略基极电流,顺向导通的二极管的射-基极电压VEB可表示成:If the base current is neglected, the emitter-base voltage VEB of a forward-conducting diode can be expressed as:
其中k为波兹曼常数(1.38×10-23J/K),q为电荷电量(1.6×10-29C),T为温度,IC为集极电流,而IS为饱和电流。Where k is Boltzmann's constant (1.38×10 -23 J/K), q is charge quantity (1.6×10 -29 C), T is temperature, I C is collector current, and I S is saturation current.
当运算放大器OP的输入电压V1与V2相互匹配且晶体管Q2的尺寸为晶体管Q1的N倍,晶体管Q1与Q2的射-基极电压差ΔVEB可表示成:When the input voltages V1 and V2 of the operational amplifier OP match each other and the size of the transistor Q2 is N times that of the transistor Q1, the emitter-base voltage difference ΔV EB between the transistors Q1 and Q2 can be expressed as:
其中VEB1为晶体管Q1的射-基极电压,而VEB2为晶体管Q2的射-基极电压。Where V EB1 is the emitter-base voltage of transistor Q1, and V EB2 is the emitter-base voltage of transistor Q2.
由于输入电压V1与V2因为运算放大器OP而相互匹配(虚短路),因此输入电压V1与V2可表示成:Since the input voltages V1 and V2 match each other due to the operational amplifier OP (virtual short circuit), the input voltages V1 and V2 can be expressed as:
V1=V2=VEB1=VEB2+I2×R3V1=V2=V EB1 =V EB2 +I2×R3
因此,通过电阻R2与R3的电流I2可表示成:Therefore, the current I2 through the resistors R2 and R3 can be expressed as:
由于电阻R1与R2具有相同的阻值而且输入电压V1与V2因为运算放大器OP而相互匹配(虚短路),因此电流I2会与电流I1相等。Since the resistors R1 and R2 have the same resistance and the input voltages V1 and V2 are matched by the operational amplifier OP (virtual short circuit), the current I2 will be equal to the current I1.
于是,
因此,电压Vbg也可表示成:Therefore, the voltage Vbg can also be expressed as:
由于晶体管的射-基极电压VEB具有-2mV/℃的负温度系数,因此若适当地选择电阻R1~R3的电阻值的比例,电流Vbg将可以具有近乎零的温度系数并且与较不受温度变化的影响。Since the emitter-base voltage V EB of the transistor has a negative temperature coefficient of -2mV/°C, if the ratio of the resistance values of the resistors R1 to R3 is properly selected, the current Vbg will have a nearly zero temperature coefficient and is less affected by Effects of temperature changes.
于某些实施例中,电阻R3是由一电阻梯来实现。图2为一电阻梯的实施例。电阻R3是耦接于电阻R2与晶体管Q2之间,且包括串联连接的N个电阻R31~R3N,以及串联连接的N个开关元件SWl~SWlA。除了电阻R31与R3N之外,每个开关元件SWl~SWlA是并联于一个对应的电阻。举例而言,开关元件SW10的两端是耦接至电阻R32的两端,开关元件SW11的两端是耦接至电阻R33的两端,依此类推。开关元件SW10~SW1N是可通过MOS晶体管来实现。In some embodiments, the resistor R3 is realized by a resistor ladder. Fig. 2 is an embodiment of a resistance ladder. The resistor R3 is coupled between the resistor R2 and the transistor Q2, and includes N resistors R31-R3N connected in series, and N switch elements SW1-SW1A connected in series. Except for the resistors R31 and R3N, each switch element SW1˜SW1A is connected in parallel with a corresponding resistor. For example, the two ends of the switch element SW10 are coupled to the two ends of the resistor R32, the two ends of the switch element SW11 are coupled to the two ends of the resistor R33, and so on. Switching elements SW10-SW1N can be realized by MOS transistors.
由于开关元件SW10~SW1A是设置于电流I2的路径中,使得非理想的开关效应(例如温度系数、finite导通电阻)会影响能带隙参考电路的参数。举例而言,当开关元件SW10导通时,电流I2会流经电阻R31、开关元件SW10与电阻R33~R3N,所以开关元件SW10上的非理想效应会影响能带隙参考电路的参数。再者,假设开关元件SW10~SW1N是由PMOS晶体管来实现,耦接电源电压的N井区也会退化能带隙参考电路的电源拒斥比(power supply rejectionratio)的效能。在取得开关元件数组(SW10~SW1M)的最佳设定值后,当考虑电源拒斥比时,这些开关元件就会由硬件线路来实现。由于开关元件与硬件线路在特性上的不同,能带隙参考电路的参数将会产生漂移。Since the switching elements SW10 - SW1A are disposed in the path of the current I2 , non-ideal switching effects (such as temperature coefficient, finite on-resistance) will affect the parameters of the bandgap reference circuit. For example, when the switch element SW10 is turned on, the current I2 will flow through the resistor R31, the switch element SW10 and the resistors R33-R3N, so the non-ideal effect on the switch element SW10 will affect the parameters of the bandgap reference circuit. Furthermore, assuming that the switching elements SW10˜SW1N are implemented by PMOS transistors, the N-well region coupled to the power supply voltage will also degrade the performance of the power supply rejection ratio of the bandgap reference circuit. After obtaining the optimum setting value of the switching element array (SW10-SW1M), these switching elements will be implemented by hardware circuits when considering the power supply rejection ratio. Due to the difference in characteristics between switching elements and hardware circuits, the parameters of the energy bandgap reference circuit will drift.
避免开关元件的有限导通电阻(finite turning on resistance)与温度系数的最好方法是将它们设置在一高阻抗路径上,并且在一个运算放大器式的能带隙电压参考电路中,高阻抗路径是存在于运算放大器的输入端上。因此,本发明还提供一种不受开关元件的有限导通电阻与温度系数影响的能带隙电压参考电路。The best way to avoid the finite turning on resistance and temperature coefficient of the switching elements is to place them on a high impedance path, and in an operational amplifier type bandgap voltage reference circuit, the high impedance path is present at the input of the operational amplifier. Therefore, the present invention also provides a bandgap voltage reference circuit that is not affected by the finite on-resistance and temperature coefficient of the switching element.
图3为能带隙电压参考电路的另一实施例。如图所示,能带隙电压参考电路20除了电阻梯22是与图1中所示的能带隙电压参考电路10A相似。能带隙电压参考电路20包括双载子晶体管Q1与Q2、运算放大器OP、电阻R1以及电阻梯22。FIG. 3 is another embodiment of a bandgap voltage reference circuit. As shown, the bandgap voltage reference circuit 20 is similar to the bandgap
晶体管Q1包括一射极耦接至运算放大器OP的正输入端以及耦接至接地电压GND的一基极与一集极。晶体管Q2包括一射极耦接至电阻梯22以及耦接至接地电压GND的一基极与一集极。换言之,晶体管Q1与Q2为二极管方式连接的晶体管。电阻R1耦接于运算放大器OP的正输入端与其输出端之间,电阻梯22耦接晶体管Q2的射极以及运算放大器OP的负输入端与输出端之间。The transistor Q1 includes an emitter coupled to the positive input terminal of the operational amplifier OP, a base and a collector coupled to the ground voltage GND. The transistor Q2 includes an emitter coupled to the resistor ladder 22 and a base and a collector coupled to the ground voltage GND. In other words, the transistors Q1 and Q2 are diode-connected transistors. The resistor R1 is coupled between the positive input terminal and the output terminal of the operational amplifier OP, and the resistor ladder 22 is coupled between the emitter of the transistor Q2 and the negative input terminal and the output terminal of the operational amplifier OP.
电阻梯22包括串联连接的复数电阻RX1~RXN以及复数开关元件SW21~SW22。电阻RX1耦接于运算放大器OP的输出端与节点ND20之间,电阻RX2耦接于节点ND20与节点ND21之间,依此类推,而电阻RXN耦接于节点ND2M与晶体管Q2的射极之间。每个开关元件SW20~SW2M皆具有一第一端耦接至一对应的节点,以及一第二端耦接运算放大器OP的负输入端。举例而言,开关元件SW20耦接于运算放大器OP的负输入端与节点ND20之间,开关元件SW21耦接于运算放大器OP的负输入端与节点ND21之间,依此类推。开关元件SW2M耦接于运算放大器OP的负输入端与节点ND21之间。The resistance ladder 22 includes a plurality of resistors RX1 to RXN and a plurality of switching elements SW21 to SW22 connected in series. The resistor RX1 is coupled between the output terminal of the operational amplifier OP and the node ND20, the resistor RX2 is coupled between the node ND20 and the node ND21, and so on, and the resistor RXN is coupled between the node ND2M and the emitter of the transistor Q2 . Each switch element SW20˜SW2M has a first terminal coupled to a corresponding node, and a second terminal coupled to the negative input terminal of the operational amplifier OP. For example, the switch element SW20 is coupled between the negative input terminal of the operational amplifier OP and the node ND20 , the switch element SW21 is coupled between the negative input terminal of the operational amplifier OP and the node ND21 , and so on. The switch element SW2M is coupled between the negative input terminal of the operational amplifier OP and the node ND21.
包含电阻RX1~RXN的电阻串(即电阻梯22)会具有一个固定的总电阻值,并且图1所中示电阻R2与R3可以由开关元件SW21~SW2M进行调整。举例而言,当开关元件SW20导通而开关元件SW21~SW2M截止时,电阻RX1是作为一第一等效电阻(如图1所示的电阻R2),而电阻串中剩余的电阻RX2~RXN是作为一第二等效电阻(如图1所示的电阻R3)。于另一例子中,当开关元件SW21导通而开关元件SW20与SW22~SW2M截止时,包含电阻RX1~RX2的电阻串是作为第一等效电阻(如图1所示的R2),而包含电阻RX3~RXN的电阻串是作为第二等效电阻(如图1所示的R3)。当开关元件SW22导通而开关元件SW20~SW21与SW23~SW2M截止时,包含电阻RX1~RX3的电阻串是作为第一等效电阻(如图1所示的R2),而包含电阻RX4~RXN的电阻串是作为第二等效电阻(如图1所示的R3),依此类推。通过导通开关元件中的一个,即可调整第一、第二等效电阻(如图1中所示的R2与R3)的比例。由于运算放大器OP的输入端为高阻抗,因此不会有电流通过开关元件SW21~SW2M流入运算放大器OP,电流I2只会流经电阻RX1~RXN以及晶体管Q2。The resistor string (ie, the resistor ladder 22 ) including the resistors RX1 - RXN has a fixed total resistance, and the resistors R2 and R3 shown in FIG. 1 can be adjusted by the switch elements SW21 - SW2M. For example, when the switch element SW20 is turned on and the switch elements SW21˜SW2M are turned off, the resistor RX1 acts as a first equivalent resistor (resistor R2 shown in FIG. 1 ), and the remaining resistors RX2˜RXN in the resistor string is used as a second equivalent resistor (resistor R3 shown in FIG. 1). In another example, when the switch element SW21 is turned on and the switch elements SW20 and SW22-SW2M are turned off, the resistor string including resistors RX1-RX2 is used as the first equivalent resistor (R2 shown in FIG. 1 ), and includes The resistor string of resistors RX3 - RXN is used as the second equivalent resistor (R3 as shown in FIG. 1 ). When the switch element SW22 is turned on and the switch elements SW20~SW21 and SW23~SW2M are turned off, the resistor string including resistors RX1~RX3 is used as the first equivalent resistor (R2 shown in Figure 1), and includes resistors RX4~RXN The resistor string is used as the second equivalent resistor (R3 shown in Figure 1), and so on. By turning on one of the switch elements, the ratio of the first and second equivalent resistors (R2 and R3 shown in FIG. 1 ) can be adjusted. Since the input terminal of the operational amplifier OP is high impedance, no current flows into the operational amplifier OP through the switching elements SW21 - SW2M, and the current I2 only flows through the resistors RX1 - RXN and the transistor Q2.
因此,如果能适当地选择电阻R1~R3的电阻值比例,能带隙电压参考电路20的输出电压Vbg’也会具有近似于零的温度系数并且对温度较不敏感。于某些实施例中,晶体管SW20~SW2M是由来自一外部控制装置的一组控制信号所控制,使得电阻R2~R3可以被调整,而得到想要的输出电压Vbg’。Therefore, if the ratio of the resistance values of the resistors R1-R3 can be properly selected, the output voltage Vbg' of the bandgap voltage reference circuit 20 will also have a temperature coefficient close to zero and be less sensitive to temperature. In some embodiments, the transistors SW20-SW2M are controlled by a set of control signals from an external control device, so that the resistors R2-R3 can be adjusted to obtain the desired output voltage Vbg'.
图4为能带隙电压参考电路的另一实施例。如图所示,能带隙电压参考电路30除了电阻梯24之外,是与图3中所示的能带隙电压参考电路20相似。电阻梯24耦接于运算放大器OP的输出端与接地电压GND之间,并且包括串联连接的复数电阻R41~R4Y以及复数开关元件SW30~SW3Z。电阻R41耦接于运算放大器OP的输出端与节点ND30之间,电阻R42耦接于节点ND30与节点ND31之间,依此类推,电阻R4Y耦接于节点ND3Z与接地电压GND之间。开关元件SW30~SW3Z各具有一第一端耦接至一对应的节点,以及一第二端接至一输出端。FIG. 4 is another embodiment of a bandgap voltage reference circuit. As shown, the bandgap
举例而言,开关SW30耦接于输出端与节点ND30之间,开关SW31耦接于输出端与节点ND31之间,依此类推,开关SW3Z耦接于输出端与节点ND3Z之间。电阻梯24是通过导通开关元件SW30~SW3Z中的一个,用以对输出电压Vbg’进行分压,使得输出电压Vbg”能低于输出电压Vbg’,以便能操作于一低电压环境中。于某些实施例中,开关元件SW30与SW3Z可由来自外部控制装置的另一阻控制信号所控制,使得输出电压Vbg”能被操作于一低电压环境中。For example, the switch SW30 is coupled between the output terminal and the node ND30 , the switch SW31 is coupled between the output terminal and the node ND31 , and so on, the switch SW3Z is coupled between the output terminal and the node ND3Z. The
当开关元件SW20~SW2M各具有一端耦接至运算放大器OP的一输入端(即高阻抗路径),所以不会有任何电流流经开关元件SW20~SW2M至运算放大器OP,因此开关元件SW20~SW2M(晶体管)不会影响能带隙电压参考电路的参数。由于没有电流流经开关元件(晶体管),因此,即使在考虑电源拒斥比的情况下,开关元件与硬件线路不同的特性的影响,且开关元件是于取得最佳设定值后由硬件线路取代,能带隙电压参考电路的参数将仍然不会受到影响。When the switching elements SW20-SW2M each have one end coupled to an input end of the operational amplifier OP (ie, a high-impedance path), so no current flows through the switching elements SW20-SW2M to the operational amplifier OP, so the switching elements SW20-SW2M (transistor) does not affect the parameters of the bandgap voltage reference circuit. Since no current flows through the switching element (transistor), even when considering the power rejection ratio, the influence of the characteristics of the switching element and the hardware circuit is different, and the switching element is controlled by the hardware circuit after obtaining the optimum setting value. Instead, the parameters of the bandgap voltage reference circuit will remain unaffected.
能带隙电压参考电路10A、20与30是可扮演混合模式集成电路或模拟集成电路的操作中的必要功能区块,例如数据转换器(data converter)、锁相回路(PLL)、振荡器、电源管理电路、动态随机存取存储器(DRAM)、闪存(FLASH)…等等。举例而言,能带隙电压参考电路30是提供输出电压Vbg”至一核心电路,以便核心电路执行其功能。The bandgap
虽然本发明已以较佳实施例揭示如上,然其并非用以限定本发明,任何熟知技艺者,在不脱离本发明的精神和范围内,当可作些许更动与润饰,因此本发明的保护范围当视权利要求所界定者为准。Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any skilled person may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be determined by what is defined in the claims.
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