CN112327992A

CN112327992A - Voltage bias circuit with adjustable output, chip and communication terminal

Info

Publication number: CN112327992A
Application number: CN202011314855.3A
Authority: CN
Inventors: 高晨阳; 林升
Original assignee: Vanchip Tianjin Electronic Technology Co Ltd
Current assignee: Vanchip Tianjin Electronic Technology Co Ltd
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2021-02-05
Also published as: WO2022105890A1; EP4250054A1; EP4250054A4

Abstract

The invention provides a voltage bias circuit with adjustable output, a chip and a communication terminal. The bias circuit comprises a band gap voltage reference unit, a low-voltage difference linear voltage stabilizing unit, a first transmission gate switch unit, a logic coding control unit and a second transmission gate switch unit. The bias circuit is correspondingly provided with a resistance voltage dividing network and a feedback resistance network in a band gap voltage reference unit and a low voltage difference linear voltage stabilizing unit so as to generate a plurality of voltages with different temperature coefficients and different numerical values and different gain coefficients; the logic coding control unit is used for controlling the corresponding transmission gate switch unit to select the input reference voltage with the required value and the temperature coefficient and the required gain coefficient so as to output the voltage with the required value and the temperature coefficient and provide a proper bias state for the radio frequency front end module, so that the radio frequency front end module realizes better performance and the communication terminal has better flexibility and adaptability in a complex environment.

Description

Voltage bias circuit with adjustable output, chip and communication terminal

Technical Field

The invention relates to a voltage bias circuit with adjustable output, an integrated circuit chip comprising the voltage bias circuit and a corresponding communication terminal, and belongs to the technical field of integrated circuits.

Background

With the development of communication technology, higher requirements are put on the performance of communication terminals. There is a need for integrated circuit chips with greater flexibility and greater flexibility. The bias circuit responsible for providing a direct current operating point for the radio frequency front end module is the first to come, and particularly, the bias circuit is a Heterojunction Bipolar Transistor (HBT) radio frequency bias circuit. Because the performance of the rf front-end module is closely related to the operating state of the bias circuit, and considering that the rf front-end module needs to be repeatedly debugged in research, development and application, and the portable communication terminals (mainly mobile phones and tablet computers) are large in scale and complex in application environment, it is important to provide a high-flexibility dc operating point for the rf front-end module, otherwise the development of the new-generation communication technology is greatly limited.

A bandgap voltage reference circuit (also referred to as "bandgap") and a low dropout regulator (also referred to as "LDO") are commonly used as typical voltage bias circuits, and the flexibility of the output voltage determines the flexibility of the rf front-end module (mainly including the power amplifier). It can be said that the more flexible the output voltages of the bandgap voltage reference circuit and the low dropout regulator are, the easier the rf front-end module can achieve better performance, and the more adaptable the communication terminal can adapt to complex application environments. However, the existing bandgap voltage reference circuit and the low dropout regulator have single output voltage, and cannot realize output voltage with any temperature coefficient and any numerical value on the same circuit module, and the low flexibility thereof causes the radio frequency front end module to face limitations in research, development and debugging and communication terminal application.

Disclosure of Invention

The invention provides a voltage bias circuit with adjustable output.

Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the voltage bias circuit and a corresponding communication terminal.

In order to achieve the purpose, the invention adopts the following technical scheme:

according to a first aspect of the embodiments of the present invention, there is provided an output-adjustable voltage bias circuit, including a bandgap voltage reference unit, a low dropout regulator unit, a first transmission gate switch unit, a logic encoding control unit, and a second transmission gate switch unit; the band gap voltage reference unit is connected with the low-dropout linear voltage stabilizing unit through the first transmission gate switch unit, the low-dropout linear voltage stabilizing unit is connected with the second transmission gate switch unit, and the logic coding control unit is connected with the first transmission gate switch unit and the second transmission gate switch unit;

the logic coding control unit is used for controlling the first transmission gate switch unit to select voltages with required values and temperature coefficients from the voltages with different temperature coefficients and different values generated by the band gap voltage reference unit, and the voltages are output to the low-dropout linear voltage stabilizing unit to be used as input reference voltages of the low-dropout linear voltage stabilizing unit; meanwhile, the logic coding control unit controls the second transmission gate switch unit to select a corresponding required gain coefficient from a plurality of gain coefficients of the low-dropout linear voltage regulator unit, and a negative feedback closed-loop system is formed by the low-dropout linear voltage regulator unit, so that the voltage of a gain coefficient feedback node is approximately equal to the input reference voltage, and the voltage of a required value and a temperature coefficient is output.

Preferably, the band-gap voltage reference unit comprises an operational amplifier, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first resistor, a first bipolar transistor, a second bipolar transistor, a third bipolar transistor and a resistor voltage dividing network; the non-inverting input end of the operational amplifier is connected with the drain electrode of the first PMOS tube and one end of the first resistor, the other end of the first resistor is connected with the emitter electrode of the first bipolar transistor, the inverting input end of the operational amplifier is connected with the drain electrode of the second PMOS tube and the emitter electrode of the second bipolar transistor, the output end of the operational amplifier is connected with the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube, the drain electrode of the third PMOS tube is connected with one end of the resistance voltage division network, the other end of the resistance voltage division network is connected with the emitter electrode of the third bipolar transistor, the output end of the resistance voltage division network is connected with the first transmission gate switch unit, the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with a power supply voltage, and the first bipolar transistor, The collectors of the second bipolar transistor and the third bipolar transistor are grounded.

Preferably, the resistance voltage division network is formed by connecting a plurality of second resistors in series; and different resistance nodes of the resistance voltage division network correspondingly output voltages with different temperature coefficients and different values.

Preferably, the low-dropout linear voltage stabilizing unit comprises an error amplifier, a power tube and a feedback resistor network; the positive phase input end of the error amplifier is connected with the first transmission gate switch unit, the negative phase input end of the error amplifier is connected with the feedback resistance network through the second transmission gate switch unit, the output end of the error amplifier is connected with the grid electrode of the power tube, the drain electrode of the power tube is connected with one end of the feedback resistance network, the other end of the feedback resistance network is grounded, and the source electrode of the power tube is connected with power supply voltage.

Preferably, the feedback resistance network is formed by connecting a plurality of third resistors in series; and each resistance feedback node correspondingly outputs different gain coefficients.

Preferably, the logic coding control unit is a binary coding circuit composed of a not gate circuit and an and gate circuit.

Preferably, the first pass gate switch unit includes a plurality of first pass gate switches, each of the first pass gate switches includes a tenth PMOS transistor, a seventh NMOS transistor and a first inverter, and a source of the tenth PMOS transistor is connected to a drain of the seventh NMOS transistor and serves as an input terminal of the first pass gate switch, and is used for connecting a corresponding resistance node of the resistance voltage divider network; the drain electrode of the tenth PMOS tube is connected with the source electrode of the seventh NMOS tube to serve as the output end of the first transmission gate switch and is used for being connected with the positive phase input end of the error amplifier; the grid electrode of the seventh NMOS tube is connected with the output end corresponding to the logic coding control unit and the input end of the first phase inverter, and the output end of the first phase inverter is connected with the grid electrode of the tenth PMOS tube.

Preferably, the second transmission gate switch unit includes a plurality of second transmission gate switches, each second transmission gate switch includes an eleventh PMOS transistor, an eighth NMOS transistor, and a second inverter, and a source of the eleventh PMOS transistor is connected to a drain of the eighth NMOS transistor and serves as an input terminal of the second transmission gate switch, and is used for connecting to a corresponding resistance feedback node of the feedback resistance network; the drain electrode of the eleventh PMOS tube is connected with the source electrode of the eighth NMOS tube to serve as the output end of the second transmission gate switch and is used for being connected with the inverting input end of the error amplifier; the grid electrode of the eighth NMOS tube is connected with the output end corresponding to the logic coding control unit and the input end of the second phase inverter, and the output end of the second phase inverter is connected with the grid electrode of the eleventh PMOS tube.

According to a second aspect of embodiments of the present invention, there is provided an integrated circuit chip comprising the voltage bias circuit described above.

According to a third aspect of the embodiments of the present invention, there is provided a communication terminal including the above-described voltage bias circuit therein.

The output-adjustable voltage bias circuit provided by the invention generates a plurality of voltages with different temperature coefficients and different numerical values and different gain coefficients by correspondingly arranging the resistance voltage dividing network and the feedback resistance network in the bandgap voltage reference unit and the low-voltage difference linear voltage stabilizing unit; the logic coding control unit is used for controlling the corresponding transmission gate switch unit to select the input reference voltage with the required value and the temperature coefficient and the required gain coefficient so as to output the voltage with the required value and the temperature coefficient and provide a proper bias state for the radio frequency front end module, so that the radio frequency front end module realizes better performance and the communication terminal has better flexibility and adaptability in a complex environment.

Drawings

FIG. 1 is a schematic diagram of a typical voltage bias circuit;

FIG. 2 is a schematic diagram of a voltage bias circuit with adjustable output according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of a bandgap voltage reference unit in a voltage bias circuit with adjustable output according to an embodiment of the present invention;

fig. 4 is a schematic circuit diagram of an error amplifier in the output-adjustable voltage bias circuit according to the embodiment of the present invention;

fig. 5 is a schematic diagram of a 3-8 coding circuit in a logic coding control unit in the output adjustable voltage bias circuit provided in the embodiment of the present invention;

fig. 6 is a schematic circuit diagram of a first pass gate switch unit in the output-adjustable voltage bias circuit according to the embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a second pass-gate switch unit in the output-adjustable voltage bias circuit according to the embodiment of the present invention.

Detailed Description

The technical contents of the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, a typical voltage bias circuit is composed of a bandgap voltage reference unit 101 and a low dropout linear regulator unit 102. The function of the bandgap voltage reference unit is to generate a reference voltage Vref with zero temperature coefficient and without being affected by the power supply voltage, and then provide the reference voltage Vref to the low dropout linear regulator unit 102 as an input reference voltage.

The low dropout linear regulator unit 102 is composed of an error amplifier 201, a power tube 202 and a feedback resistance network 203. Feedback resistor network 203 is comprised of resistor Rf1 and resistor Rf 2. The output voltage Vout is expressed as

In the formula

Which may be referred to as a gain factor, is determined by the proportional relationship between resistance Rf1 and resistance Rf 2. The output voltage Vout is determined by the reference voltage Vref of the bandgap voltage reference unit 101 and the gain coefficient of the low dropout linear regulator unit 102.

In order to solve the problem that the output voltages of the band gap voltage reference circuit and the low dropout regulator are single and the output voltages with any temperature coefficient and any numerical value cannot be realized on the same circuit module and achieve the purposes that the radio frequency front end module realizes better performance and the communication terminal is better applied to a complex environment, the embodiment of the invention provides the voltage bias circuit with the adjustable output, which is used for providing voltages with different temperature coefficients and different numerical values for the radio frequency front end module. As shown in fig. 2, the voltage bias circuit includes a bandgap voltage reference unit 301, a low dropout linear regulator unit 302, a first pass gate switch unit 303, a logic encoding control unit 304 and a second pass gate switch unit 306; the bandgap voltage reference unit 301 and the low dropout linear regulator unit 302 are connected to a power supply voltage VDD, the bandgap voltage reference unit 301 is connected to the low dropout linear regulator unit 302 through a first pass gate switch unit 303, the low dropout linear regulator unit 302 is connected to a second pass gate switch unit 306, and the logic encoding control unit 304 is connected to the first pass gate switch unit 303 and the second pass gate switch unit 306.

The logic coding control unit 304 is used for controlling the first transmission gate switch unit 303 to select the voltage with the required value and the temperature coefficient from the voltages with different temperature coefficients and different values generated by the bandgap voltage reference unit 301, and the voltage is output to the low dropout linear voltage stabilizing unit 302 as the input reference voltage; meanwhile, the logic coding control unit 304 controls the second pass gate switch unit 306 to select a corresponding required gain coefficient from the multiple gain coefficients of the low dropout linear regulator unit 302, and forms a negative feedback closed loop system through the low dropout linear regulator unit 302, so that the voltage of the gain coefficient feedback node is approximately equal to the input reference voltage, thereby outputting the voltage of the required value and the temperature coefficient, and providing a proper bias state for the radio frequency front end module, so that the radio frequency front end module realizes better performance, and the communication terminal is better applied in a complex environment.

The bandgap voltage reference unit 301 is configured to generate a plurality of voltages with different temperature coefficients and different values. The number of voltages with different temperature coefficients and different values generated by the bandgap voltage reference unit 301 is adjusted according to the number actually required by the rf front-end module. As shown in fig. 3, the bandgap voltage reference unit 301 includes an operational amplifier a1, a first PMOS transistor 701, a second PMOS transistor 702, a third PMOS transistor 703, a first resistor R1, a first bipolar transistor 706, a second bipolar transistor 707, a third bipolar transistor 708, and a resistor divider network 709. The non-inverting input terminal of the operational amplifier a1 is connected to the drain of the first PMOS transistor 701 and one terminal of the first resistor R1, the other terminal of the first resistor R1 is connected to the emitter of the first bipolar transistor 706, the inverting input terminal of the operational amplifier a1 is connected to the drain of the second PMOS transistor 702 and the emitter of the second bipolar transistor 707, the output terminal of the operational amplifier a1 is connected to the gates of the first PMOS transistor 701, the second PMOS transistor 702 and the third PMOS transistor 703, the drain of the third PMOS transistor 703 is connected to one terminal of the resistor divider network 709, the other terminal of the resistor divider network 709 is connected to the emitter of the third bipolar transistor 708, the output terminal of the resistor divider network 709 is connected to the first pass-gate switch unit 303, the source terminals of the first PMOS transistor 701, the second PMOS transistor 702 and the third PMOS transistor 703 are connected to the supply voltage VDD, the first bipolar transistor 706, the collectors of the second bipolar transistor 707 and the third bipolar transistor 708 are grounded.

As shown in fig. 3, the resistor voltage divider network 709 is formed by serially connecting a plurality of second resistors (resistors R2_ A, R2_ B, R2_ C … … R2_ N); the resistor voltage divider is used to generate a plurality of voltages (Vref1, Vref2 … … Vrefn) with different temperature coefficients and different values, that is, the resistor voltage divider network 709 outputs voltages with different temperature coefficients and different values corresponding to different resistor nodes. The logic coding control unit 304 is used to control the on-off state of the first pass gate switch unit 303, so as to select the voltage with the required value and temperature coefficient from the voltages with different temperature coefficients and different values generated by the resistor voltage dividing network 709, and these different voltages are provided to the low dropout linear regulator unit 302 as the input reference voltage, so as to implement the diversity of the input reference voltages. The adjustable precision of the output voltage of the output adjustable voltage bias circuit is determined by the proportion of the second resistor in the resistor voltage divider network 709, and the resistor voltage divider network 709 with a proper proportion can be designed according to the precision of a voltage value and the precision of a voltage temperature coefficient required by application.

As shown in the figure3, the first PMOS transistor 701, the second PMOS transistor 702, and the third PMOS transistor 703 form a current mirror, and the width-to-length ratios of the first PMOS transistor 701 and the second PMOS transistor 702 are the same, so that the currents flowing through the first bipolar transistor 706 and the second bipolar transistor 707 are equal, and further, the difference Δ V between the base-emitter voltages of the first bipolar transistor 706 and the second bipolar transistor 707 is equal_BE＝Inn*V_TWhere n is the ratio of the number of

bipolar transistors

706 and 707 connected in parallel, V_TIs the thermal voltage of a bipolar transistor,

k is Boltzmann constant and q is an electronic charge, i.e.

The difference Δ V in the base-emitter voltages of the first and second

bipolar transistors

706 and 707_BEProportional to the absolute temperature T, i.e. the PTAT current. In addition, due to the presence of the operational amplifier a1, the non-inverting input terminal and the inverting input terminal have the same voltage, so the voltage drop across the first resistor R1 is the difference Δ V between the base-emitter voltages of the first bipolar transistor 706 and the second bipolar transistor 707_BEThe current flowing through the first PMOS transistor 701 and the second PMOS transistor 702

Assuming that the current mirror ratio of the third PMOS transistor 703 to the first PMOS transistor 701 and the second PMOS transistor 702 is M, the current flowing through the third PMOS transistor 703 is M

Then, a plurality of voltages (Vref1, Vref2 … …, Vrefn) with different temperature coefficients and different values are generated by the resistor voltage-dividing network 709₃The voltage generated by the corresponding resistor in the resistor divider network 709 plus the base-emitter voltage V of the third bipolar transistor 708_BEDetermining, e.g. Vref1 ═ I₃*(R2_A+R2_B+R2_C+……R2_N)+V_BE，Vref2＝I₃*(R2_B+R2_C+……R2_N)+V_BEThus, different resistance nodes of the resistance voltage divider network 709 can output voltages with different values and different temperature coefficients.

As shown in fig. 2, the low dropout linear regulator unit 302 includes an error amplifier 401, a power tube 402 and a feedback resistance network 403; the non-inverting input end of the error amplifier 401 is connected to the first pass gate switch unit 303, the inverting input end of the error amplifier 401 is connected to the feedback resistance network 403 through the second pass gate switch unit 306, the output end of the error amplifier 401 is connected to the gate of the power tube 402, the drain of the power tube 402 is connected to one end of the feedback resistance network 403, the other end of the feedback resistance network 403 is grounded, and the source of the power tube 402 is connected to the power supply voltage VDD.

As shown in fig. 2, the feedback resistor network 403 is composed of a plurality of third resistors (Rf2_ A, Rf2_ B, Rf2_ C … … Rf2_ H) connected in series; different resistive feedback nodes (Vfb _ A, Vfb _ B, Vfb _ C … … Vfb _ H) in the feedback resistive network 403 correspond to different gain coefficients. The error amplifier 401, the power tube 402 and the feedback resistor network 403 form a negative feedback closed loop system, so that the voltages of the non-inverting input terminal and the inverting input terminal of the error amplifier 401 are approximately equal, and further the clamping of the input reference voltage node and the resistor feedback node (i.e., the gain coefficient feedback node) of the error amplifier 401 is realized, that is, the voltage of the resistor feedback node is approximately equal to the input reference voltage. A resistance feedback node is arranged between adjacent third resistors in the feedback resistance network 403; each resistance feedback node corresponds to different voltages, and each resistance feedback node corresponds to different output gain coefficients so as to realize diversity of the gain coefficients. The third resistance ratio in the feedback resistance network 403 determines the adjustable precision of the output voltage gain coefficient of the output adjustable voltage bias circuit, and the feedback resistance network 403 with a proper ratio can be designed according to the gain coefficient of the voltage required by the application.

As shown in fig. 4, the error amplifier 401 includes a fourth PMOS transistor 601, a fifth PMOS transistor 602, a first NMOS transistor 603, a second NMOS transistor 604, a sixth PMOS transistor 605, a seventh PMOS transistor 606, a third NMOS transistor 607, a fourth NMOS transistor 608, a fifth NMOS transistor 609, a sixth NMOS transistor 610, an eighth PMOS transistor 611, and a ninth PMOS transistor 612; the gate of the fourth PMOS transistor 601 is used as the non-inverting input terminal of the error amplifier 401 and is connected to the first pass gate switch unit 303, the gate of the fifth PMOS transistor 602 is used as the inverting input terminal of the error amplifier 401 and is connected to the second pass gate switch unit 306, the drain of the fourth PMOS transistor 601 is connected to the gate and drain of the first NMOS transistor 603 and the gate of the second NMOS transistor 604, the drain of the second NMOS transistor 604 is connected to the gate and drain of the sixth PMOS transistor 605 and the gate of the seventh PMOS transistor 606, the drain of the seventh PMOS transistor 606 is used as the output terminal Vop of the error amplifier 401 and is connected to the gate of the power transistor 402 and the drain of the fourth NMOS transistor 608, the gate of the fourth NMOS transistor 608 is connected to the gate and drain of the third NMOS transistor 607 and the drain of the fifth PMOS transistor 602, the source of the fifth PMOS transistor 602 is connected to the source of the fourth PMOS transistor 601 and the drain of the ninth PMOS transistor 612, the gate of the ninth PMOS transistor 612 is connected to the gate and drain of the eighth PMOS transistor 611, The drain of the sixth NMOS transistor 610, the gate of the sixth NMOS transistor 610 is connected to the gate and the drain of the fifth NMOS transistor 609, the drain of the fifth NMOS transistor 609 is connected to an external bias voltage Ibias, the sources of the sixth PMOS transistor 605, the seventh PMOS transistor 606, the eighth PMOS transistor 611, and the ninth PMOS transistor 612 are all connected to the supply voltage VDD, and the sources of the first NMOS transistor 603, the second NMOS transistor 604, the third NMOS transistor 607, the fourth NMOS transistor 608, the fifth NMOS transistor 609, and the sixth NMOS transistor 610 are all grounded.

In the error amplifier 401 provided in the embodiment of the present invention, the fourth PMOS transistor 601 and the fifth PMOS transistor 602 are input amplifying pair transistors, and the first NMOS transistor 603 and the second NMOS transistor 604, the sixth PMOS transistor 605 and the seventh PMOS transistor 606, the third NMOS transistor 607 and the fourth NMOS transistor 608, the fifth NMOS transistor 609 and the sixth NMOS transistor 610, and the eighth PMOS transistor 611 and the ninth PMOS transistor 612 respectively form a mirror current mirror. The bias current Ibias is mirrored through the fifth and

sixth NMOS

609 and 610 and the eighth and

ninth PMOS

611 and 612 to provide current bias for the fourth and

fifth PMOS

601 and 602. The fourth PMOS transistor 601 receives the voltage with the required value and temperature coefficient provided by the bandgap voltage reference unit 301 and serves as the reference input voltage of the low dropout linear regulator unit, and the fifth PMOS transistor 602 receives the resistance feedback node corresponding to the required gain coefficient provided by the feedback resistance network 403 and mirrors the voltage with the first NMOS transistor 603 and the second NMOS transistor 604, the sixth PMOS transistor 605 and the seventh PMOS transistor 606, and the third NMOS transistor 607 and the fourth NMOS transistor 608. In essence, error amplifier 401 is an operational amplifier with a current mirror load. The error amplifier, the power tube and the feedback resistance network of the low-dropout linear voltage stabilizing unit form a negative feedback closed loop system, so that the voltages of the non-inverting input end and the inverting input end of the error amplifier are approximately equal, and further the clamping of an input reference voltage node and a resistance feedback node is realized, namely the voltage of the resistance feedback node is approximately equal to the input reference voltage.

The logic encoding control unit 304 uses a plurality of less logic control bits to generate a plurality of logic combinations, so as to control the first transmission gate switch unit 303 and the second transmission gate switch unit 306 to select different input reference voltages and different gain coefficients, thereby implementing a plurality of different voltage combinations. The logic encoding control unit 304 may be a binary encoding circuit composed of a not gate circuit and an and gate circuit; for example, the logic encoding control unit 304 may be a binary encoding circuit such as a 2-4 encoding circuit, a 3-8 encoding circuit, a 4-16 encoding circuit, or the like. The number of the logic control bits of the logic encoding control unit 304 is determined by the type of the voltage to be output and the logic encoding manner, and generally follows to use as few logic control bits as possible to implement as many voltage types as possible to meet more application requirements. That is, the number of control levels generated by the logic encoding control unit 304 is determined by the temperature coefficient required by the rf front-end module and the number of voltages of the values.

As shown in FIG. 5, for example, the logic encoding control unit 304 is a 3-8 encoding circuit, the logic control bits Reg0<2>, Reg0<1>, Reg0<0> first go through the inverter circuit in turn to obtain levels Reg0<2> _ Bar and Reg0<2> _ Buf, Reg0<1> _ Bar and Reg0<1> _ Buf, Reg0<0> _ Bar and Reg0<0> _ Buf, respectively. Then, the levels are logically combined and pass through a three-input AND gate circuit to obtain control levels, the logical combination of Reg0<2:0> corresponds to one control level, and Reg0<2:0> is 000; 001; … …, respectively; 111 sequentially corresponding to the output control level VC _ 0; VC _ 1; …, respectively; VC _ 7.

The first pass gate switch unit 303 includes a plurality of first pass gate switches, the number of the first pass gate switches is the same as the number of the voltages with different values and different temperature coefficients generated by the resistor voltage divider network 709, and the first pass gate switches correspond to one another. Different resistance nodes of the resistance voltage divider network 709 are correspondingly connected with the plurality of first transmission gate switches, so that each voltage with a fixed value and a fixed temperature coefficient output by the resistance voltage divider network 709 corresponds to one first transmission gate switch.

As shown in fig. 6, each first pass gate switch includes a tenth PMOS transistor, a seventh NMOS transistor, and a first inverter, where the source of the tenth PMOS transistor is connected to the drain of the seventh NMOS transistor as the input terminal of the first pass gate switch, and is used to connect to the corresponding resistance node of the resistance voltage divider network 709; the drain of the tenth PMOS transistor is connected to the source of the seventh NMOS transistor as the output terminal of the first pass-gate switch, and is connected to the positive input terminal of the error amplifier 401; the gate of the seventh NMOS transistor is connected to the output terminal corresponding to the logic encoding control unit 304 and the input terminal of the first inverter, and the output terminal of the first inverter is connected to the gate of the tenth PMOS transistor. The PMOS transistor M1, the NMOS transistor M2 and the first inverter J1, the PMOS transistor M5, the NMOS transistor M6 and the first inverter J2 … …, the PMOS transistor M30, the NMOS transistor M29 and the first inverter J15 respectively form a plurality of first pass gate switches as shown in fig. 6. The conduction and the cut-off of the MOS tube corresponding to the conduction and the cut-off of the control branch are utilized to realize the one-to-one correspondence between the logic combination and the voltage obtained by the resistance voltage division of the band gap voltage reference unit 301, so that the one-to-one correspondence between the logic combination and the output voltage is realized, and the condition that one logic corresponds to a voltage with a determined value and a determined temperature coefficient is ensured. The voltages Vref1, Vref2 … … Vrefn are controlled by the first pass gate switch unit 303 to output a voltage Vref, which determines a temperature coefficient, to the low dropout linear regulator unit 302 as its input reference voltage.

As shown in fig. 6, the control level VC _0 output by the logic encoding control unit 304; VC _ 1; …, respectively; VC _7 is used as an enabling signal to sequentially control the on and off of the corresponding first transmission gate switch. Taking the control level VC _0 as an example, when the control level VC _0 is a high level, the PMOS transistor M1 and the NMOS transistor M2 are turned on, so that the first pass gate switch is turned on, and the voltage Vref _1 is transmitted to the output terminal of the first pass gate switch, so that the output terminal outputs a voltage Vref with a fixed value and a fixed temperature coefficient to the low dropout linear regulator unit 302 as the input reference voltage thereof. When the control level VC _0 is low, the PMOS transistor M1 and the NMOS transistor M2 are turned off, so that the first pass gate switch is turned off, i.e., the output of the voltage Vref with a fixed value and a fixed temperature coefficient to the low dropout linear regulator unit 302 is stopped. Therefore, each logic combination corresponds to a control level, and each control level corresponds to a voltage for controlling a determined value and determining a temperature coefficient.

The second pass-gate switch unit 306 includes a plurality of second pass-gate switches, and the number of the second pass-gate switches is the same as the number of the voltages with different values and different temperature coefficients generated by the resistor voltage divider network 709. Different resistive feedback nodes in the feedback resistive network 403 are connected to a plurality of second pass gate switches, such that the voltage of each gain factor output by the feedback resistive network 403 corresponds to one second pass gate switch.

As shown in fig. 7, each second transmission gate switch includes an eleventh PMOS transistor, an eighth NMOS transistor, and a second inverter, where a source of the eleventh PMOS transistor is connected to a drain of the eighth NMOS transistor as an input terminal of the second transmission gate switch, and is used for connecting a resistance feedback node corresponding to the feedback resistance network 403; the drain electrode of the eleventh PMOS tube is connected with the source electrode of the eighth NMOS tube to serve as the output end of the second transmission gate switch and is used for being connected with the inverting input end of the error amplifier 401; the gate of the eighth NMOS transistor is connected to the output terminal corresponding to the logic encoding control unit 304 and the input terminal of the second inverter, and the output terminal of the second inverter is connected to the gate of the eleventh PMOS transistor. The PMOS transistor M3, the NMOS transistor M4 and the second inverter J16, the PMOS transistor M7, the NMOS transistor M8 and the second inverter J17 … …, the PMOS transistor M31, the NMOS transistor M32 and the second inverter J30 respectively form a plurality of second transmission gate switches as shown in fig. 7. The conduction and the cut-off of the corresponding control branch of the conduction and the cut-off of the MOS tube are utilized to realize the one-to-one correspondence between the logic combination and the gain coefficient obtained by the resistance of the feedback resistance network 403, further realize the one-to-one correspondence between the logic combination and the output voltage, and ensure that each logic corresponds to one fixed gain coefficient.

As shown in fig. 7, the control level VC _0 output by the logic encoding control unit 304; VC _ 1; …, respectively; VC _7 is used as an enabling signal to sequentially control the on and off of the corresponding second transmission gate switch. Taking the control level VC _0 as an example, when the control level VC _0 is a high level, the PMOS transistor M3 and the NMOS transistor M4 are turned on, so that the second transmission gate switch is turned on, and the voltage with a certain gain coefficient output by the resistance feedback node Vfb _ a is transmitted to the output terminal of the second transmission gate switch, so that the voltage Vfb with a fixed gain coefficient is output to the low dropout linear regulator unit 302. When the control level VC _0 is low, the PMOS transistor M3 and the NMOS transistor M4 are turned off, so that the second pass gate switch is turned off, i.e., the output of the voltage Vfb with a fixed gain factor to the low dropout linear regulator unit 302 is stopped. Therefore, each logic combination corresponds to a control level, and each control level corresponds to a voltage with a fixed value and a fixed temperature coefficient.

Therefore, the control level VC _0 output by the logic coding control unit 304 is determined according to the voltage of the temperature coefficient and the value required by the rf front-end module; VC _ 1; …, respectively; VC _7 correspondingly selects and controls a corresponding resistance node and a corresponding resistance feedback node to control the first transmission gate switch unit 303 to select a required input reference voltage, and simultaneously the control level also controls the second transmission gate switch unit 306 to select a required corresponding gain coefficient, and the two are combined together to output the voltage of a numerical value and a temperature coefficient required by the radio frequency front end module through the low-dropout linear voltage regulator unit 102. Different logical combinations correspond to voltages of different values and temperature coefficients.

In addition, the output-adjustable voltage bias circuit provided by the embodiment of the invention can be used in an integrated circuit chip. The specific structure of the output adjustable voltage bias circuit in the integrated circuit chip is not described in detail herein.

The output-adjustable voltage bias circuit can also be used in a communication terminal as an important component of a radio frequency integrated circuit. The communication terminal mentioned here refers to a computer device that can be used in a mobile environment and supports multiple communication systems such as GSM, EDGE, TD _ SCDMA, TDD _ LTE, FDD _ LTE, etc., and includes a mobile phone, a notebook computer, a tablet computer, a vehicle-mounted computer, etc. In addition, the technical scheme provided by the invention is also suitable for other radio frequency integrated circuit application occasions, such as a communication base station and the like.

The voltage bias circuit with adjustable output provided by the invention is correspondingly provided with the resistance voltage dividing network and the feedback resistance network in the bandgap voltage reference unit and the low-voltage difference linear voltage stabilizing unit so as to generate a plurality of voltages with different temperature coefficients and different numerical values and different gain coefficients; the logic coding control unit is used for controlling the corresponding transmission gate switch unit to select the input reference voltage with the required value and the temperature coefficient and the required gain coefficient so as to output the voltage with the required value and the temperature coefficient and provide a proper bias state for the radio frequency front end module, so that the radio frequency front end module realizes better performance and the communication terminal has better flexibility and adaptability in a complex environment.

The voltage bias circuit with adjustable output, the chip and the communication terminal provided by the invention are explained in detail above. Any insubstantial changes and substitutions made by those skilled in the art based on the present invention are intended to be covered by the claims.

Claims

1. A voltage bias circuit with adjustable output is characterized by comprising a band gap voltage reference unit, a low-dropout linear voltage stabilizing unit, a first transmission gate switch unit, a logic coding control unit and a second transmission gate switch unit; the band gap voltage reference unit is connected with the low-dropout linear voltage stabilizing unit through the first transmission gate switch unit, the low-dropout linear voltage stabilizing unit is connected with the second transmission gate switch unit, and the logic coding control unit is connected with the first transmission gate switch unit and the second transmission gate switch unit;

2. The output-tunable voltage bias circuit of claim 1, wherein:

the band-gap voltage reference unit comprises an operational amplifier, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first resistor, a first bipolar transistor, a second bipolar transistor, a third bipolar transistor and a resistor voltage division network; the non-inverting input end of the operational amplifier is connected with the drain electrode of the first PMOS tube and one end of the first resistor, the other end of the first resistor is connected with the emitter electrode of the first bipolar transistor, the inverting input end of the operational amplifier is connected with the drain electrode of the second PMOS tube and the emitter electrode of the second bipolar transistor, the output end of the operational amplifier is connected with the grid electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube, the drain electrode of the third PMOS tube is connected with one end of the resistance voltage division network, the other end of the resistance voltage division network is connected with the emitter electrode of the third bipolar transistor, the output end of the resistance voltage division network is connected with the first transmission gate switch unit, the source electrodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected with a power supply voltage, and the first bipolar transistor, The collectors of the second bipolar transistor and the third bipolar transistor are grounded.

3. The output-tunable voltage bias circuit of claim 2, wherein:

the resistance voltage division network is formed by connecting a plurality of second resistors in series; and different resistance nodes of the resistance voltage division network correspondingly output voltages with different temperature coefficients and different values.

4. The output-tunable voltage bias circuit of claim 2, wherein:

the low-voltage-difference linear voltage stabilizing unit comprises an error amplifier, a power tube and a feedback resistor network; the positive phase input end of the error amplifier is connected with the first transmission gate switch unit, the negative phase input end of the error amplifier is connected with the feedback resistance network through the second transmission gate switch unit, the output end of the error amplifier is connected with the grid electrode of the power tube, the drain electrode of the power tube is connected with one end of the feedback resistance network, the other end of the feedback resistance network is grounded, and the source electrode of the power tube is connected with power supply voltage.

5. The output-tunable voltage bias circuit of claim 4, wherein:

the feedback resistance network is formed by connecting a plurality of third resistors in series; and each resistance feedback node correspondingly outputs different gain coefficients.

6. The output-tunable voltage bias circuit of claim 1, wherein:

the logic coding control unit is a binary coding circuit consisting of a NOT gate circuit and an AND gate circuit.

7. The output-tunable voltage bias circuit of claim 4, wherein:

the first transmission gate switch unit comprises a plurality of first transmission gate switches, each first transmission gate switch comprises a tenth PMOS (P-channel metal oxide semiconductor) tube, a seventh NMOS (N-channel metal oxide semiconductor) tube and a first phase inverter, and the source electrode of the tenth PMOS tube is connected with the drain electrode of the seventh NMOS tube to serve as the input end of the first transmission gate switch and is used for being connected with the corresponding resistance node of the resistance voltage dividing network; the drain electrode of the tenth PMOS tube is connected with the source electrode of the seventh NMOS tube to serve as the output end of the first transmission gate switch and is used for being connected with the positive phase input end of the error amplifier; the grid electrode of the seventh NMOS tube is connected with the output end corresponding to the logic coding control unit and the input end of the first phase inverter, and the output end of the first phase inverter is connected with the grid electrode of the tenth PMOS tube.

8. The output-tunable voltage bias circuit of claim 4, wherein:

the second transmission gate switch unit comprises a plurality of second transmission gate switches, each second transmission gate switch comprises an eleventh PMOS (P-channel metal oxide semiconductor) transistor, an eighth NMOS (N-channel metal oxide semiconductor) transistor and a second phase inverter, and the source electrode of the eleventh PMOS transistor is connected with the drain electrode of the eighth NMOS transistor to serve as the input end of the second transmission gate switch and is used for being connected with the corresponding resistance feedback node of the feedback resistance network; the drain electrode of the eleventh PMOS tube is connected with the source electrode of the eighth NMOS tube to serve as the output end of the second transmission gate switch and is used for being connected with the inverting input end of the error amplifier; the grid electrode of the eighth NMOS tube is connected with the output end corresponding to the logic coding control unit and the input end of the second phase inverter, and the output end of the second phase inverter is connected with the grid electrode of the eleventh PMOS tube.

9. An integrated circuit chip comprising the output-adjustable voltage bias circuit of any one of claims 1 to 8.

10. A communication terminal, characterized by comprising the output-adjustable voltage bias circuit of any one of claims 1 to 8.