TWI469296B - Wafer level chip scale package device and manufacturing method thereof - Google Patents

Description

Wafer level wafer scale package component and method of manufacturing same

The present invention relates to a Wafer Level Chip Scale Package (WLCSP) component and a manufacturing method thereof, which can increase the stand-off height and size of an I/O contact of a package component, thereby Improve the reliability of package components.

The wafer level wafer scale package is a ball placement process to make the chip external I/O contacts. According to the Coffin-Mansion formula for predicting fatigue damage due to temperature cycling, it can be seen that the greater the standing height of the ball, the more the endurance cycle of the component package can be improved. Therefore, the prior art proposes some methods to increase the standing height of the I/O contact ball. The most straightforward way to increase the standing height of a ball is to use a single tin ball of larger diameter. However, if the same ball pitch is maintained when a large solder ball is used, it is easy to cause adjacent solder balls to be welded together in a subsequent reflow process to form a short circuit and be scrapped. In other words, if the ball pitch of the wafer is limited, the standing height of the single solder ball is also limited.

Figure 1 shows a schematic diagram of a prior art wafer level wafer scale package component in combination with a circuit board. Referring to FIG. 1, the I/O contacts 12 of the wafer level wafer scale package component 10 are stacked on the active surface of the chip 13 with double tin balls to increase by the double solder balls. Standing height H. The base of the solder ball directly connected to the wafer 13 is protected by an epoxy 14 and the epoxy 14 is exposed twice at each opening of the base solder ball. Ball mount, in order to form the I/O contacts 12 of the stacked balls. Another solder ball stacked on the base solder ball is soldered to the circuit board 11. Since the thermal expansion coefficients (CTE) of the wafer 13 and the circuit board 11 are largely different, materials of different thermal expansion coefficients may vary due to temperature changes. The amount of deformation, so the I / O contact 12 has different displacements at both ends to generate stress. In particular, when the size of the wafer 13 is large, the I/O contacts 12 located near the corners of the wafer 13 are subjected to greater stress. Although such an I/O contact 12 can have a large standing height H (the distance from the surface of the wafer 13 to the surface of the circuit board 11) to improve the reliability of the package component, and the resin 14 can act as a buffer layer for stress. However, the wafer level wafer scale package component 10 requires a secondary ball implantation process and uses less epoxy resin, so the process is complicated and costly, and there is a problem of stress and alignment.

Figure 2 shows a schematic of a wafer level wafer scale package component of prior art US 6930032. A plurality of pads 203 are formed around the wafer 201, and each pad 203 is connected to one of the redistribution pads 205 located in the middle by a redistribution layer (RDL). A buffer layer 211 is formed on the redistribution pad 205, and a recessed bump metallurgy (UBM) 215 is deposited. The solder balls 217 are soldered to the under bump metallization layer 215, thereby protecting the most fragile neck of the solder balls 217 by the special structure of the concave shape. There are also two dielectric layers 207 and 209 between each of the ball-bottom metal layers 215. Although the special design of the bottom metal layer 215 can make the solder ball 217 less likely to break in the neck, the mask needs to be modified, and the special process parameters are required, so the process is complicated and the cost is high.

In view of the above, the present invention is directed to the disadvantages of the prior art described above, and provides a wafer level wafer scale package component and a manufacturing method thereof, which can increase the standing height and size of the I/O contact of the package component, thereby improving the package component. Reliability.

One of the objects of the present invention is to provide a wafer level wafer scale package component.

Another object of the present invention is to provide a method of fabricating a wafer level wafer scale package component.

For one of the above purposes, the present invention provides a wafer level wafer scale package component comprising: a wafer including at least one pad; a ball bottom metal layer disposed on the pad; a solder layer disposed on the bottom metal layer; and a bump coupled to the pre-solder layer for bonding.

In one embodiment, the wafer level wafer scale package component further includes: a barrier layer disposed on the pad; and a crystal layer disposed on the barrier layer and on the bottom metal layer under.

In one embodiment, the bump is a solder ball. The material of the pre-solder layer is selected from the group consisting of tin, tin-lead alloy, tin-zinc alloy, tin-silver alloy, tin-copper alloy, or tin-silver-copper alloy.

In one embodiment, the material of the pre-weld layer is selected from a metal or alloy that the bumps can be fused to each other.

In one embodiment, the pre-solder layer and the bump combine to form an I/O contact, the size of the I/O contact being larger than the size of the bump.

In another aspect, the present invention provides a wafer level wafer scale package component comprising: a wafer including at least one pad; a ball bottom metal layer disposed on the pad; a first pre-solder layer, On the bottom metal layer; a second pre-solder layer is disposed on the first pre-solder layer, wherein a melting point of the first pre-solder layer is higher than a melting point of the second pre-solder layer; and a bump, Bonded to the second pre-solder layer.

In one embodiment, the material of the first pre-solder layer is selected from a solder having a higher melting point.

In another aspect, the present invention provides a method of fabricating a wafer level wafer scale package component, comprising: providing a wafer having at least one pad; forming a ball bottom metal layer on the pad; forming a pre-solder layer On the bottom metal layer; and welding a bump to the pre-solder layer.

In one embodiment, the method further comprises: forming a high melting point pre-solder layer between the ball bottom metal layer and the pre-solder layer, wherein the high melting point pre-solder layer has a higher melting point than the pre-solder layer Melting point.

In one embodiment, the method further includes: forming a barrier layer on the bonding pad; and forming a crystalline layer on the barrier layer and under the underlying metal layer.

The purpose, technical content, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments.

〔this invention〕

10‧‧‧ Wafer-level wafer scale package components

11‧‧‧ boards

12‧‧‧I/O contacts

13‧‧‧ wafer

14‧‧‧Resin

201‧‧‧ wafer

203‧‧‧ solder pads

205‧‧‧Redistribution pads

207, 209‧‧‧ redistribution pads

215‧‧‧ under bump metallization

217‧‧‧ solder balls

31‧‧‧ wafer

311‧‧‧Substrate

312‧‧‧ solder pads

313‧‧‧First passivation layer

314‧‧‧ openings

32‧‧‧Second passivation layer

33, 33' ‧ ‧ barrier layer

34, 34'‧‧‧ seed layer

35‧‧‧Bottom metal layer

36‧‧‧Pre-welded layer

37’‧‧‧Bumps

37, 47‧‧‧I/O contacts

38‧‧‧ Flux

39‧‧‧Photoresist layer

461‧‧‧First pre-welded layer

462‧‧‧Second pre-welded layer

Figure 1 shows a schematic diagram of a prior art wafer level wafer scale package component in combination with a circuit board.

Figure 2 shows a schematic of a prior art wafer level wafer scale package component.

3A through 3I are diagrams showing various manufacturing steps of a wafer level wafer scale package component in accordance with an embodiment of the present invention.

4A through 4D illustrate partial manufacturing steps of a wafer level wafer scale package component in accordance with another embodiment of the present invention.

The drawings in the present invention are schematic and are mainly intended to indicate the relationship between the layers in the structure, and the shapes, thicknesses, and widths are not drawn to scale.

Referring to Figures 3A through 3I, various manufacturing steps of an embodiment of the present invention are shown. As shown in Fig. 3A, a wafer 31 is provided. The wafer 31 includes a semiconductor substrate 311, at least one pad 312, and a first passivation layer 313. The pad 312 is disposed on the active surface of the substrate 311, and the first passivation layer 313. The circuit that protects the active surface (not shown). The first passivation layer 313 has at least one opening 314 that exposes the pad 312 for internal connection to the outside.

On the first passivation layer 313, a second passivation layer 32 is formed, as shown in FIG. 3B. The material of the second passivation layer 32 is formed by spin coating or chemical vapor deposition, and the material thereof may be cerium oxide, benzocyclobutene (BCB) or polybenzoxazole (PBO). . In this embodiment, the second passivation layer 32 covers a portion of the area around the periphery of the pad 312, but the scope of protection of the present invention is not limited thereto.

Referring to Figures 3C and 3D, a barrier layer 33' and a seed layer 34' are sequentially formed by sputtering or chemical deposition. The function of the barrier layer 33' is mainly to prevent rapid reaction between the subsequent pad and the bottom metal layer, and the material thereof is selected from the group consisting of titanium metal, titanium nitride, titanium tungsten alloy, base metal layer, chromium, chrome-copper alloy and tantalum nitride. One or at least one of the group consisting of. The seed layer 34' function is such that the subsequent ball-bottom metal layer has a preferred crystal growth direction, so that the same material as the film is selected.

A photoresist layer 39 is formed by a lithography process, and an under bump metallurgy (UBM) 35 is formed on the seed layer 34' as shown in FIG. 3E. The material of the ball bottom metal layer 35 may be Al/NiV/Cu, Ti/NiV/Cu, or Ti/Cu/Ni. Etc., but not limited to the materials exemplified in the previous opening. Using the same photoresist layer 39 as a mask, a pre-solder layer 36 is deposited on the ball-bottom metal layer 35 as shown in FIG. 3F. The pre-solder layer 36 can be selected to be a metal or alloy to which the subsequently bonded bumps can be fused to each other. When the bump is a solder ball, the pre-solder layer 36 is selected from the group consisting of tin, tin-lead alloy, tin-zinc alloy, tin-silver alloy, tin-copper alloy or tin-silver-copper alloy.

Referring to FIG. 3G, the photoresist layer 39, and the etch barrier layer 33' and the seed layer 34' are located in a portion of the outer portion of the pre-solder layer 36, and the barrier layer 33, the seed layer 34, and the ball-bottom metal layer 35 are removed. And a portion or all of the pre-solder layer 36 protrudes above the second passivation layer 32. Then, a flux 38 is applied to the bottom metal layer 35 by screen printing or the like, and the bump 37' is ball mounted on the pre-solder layer 36 as shown in Fig. 3H. By the reflow process, the bump 37' and the pre-solder layer 36 are fused to each other to form an I/O contact 37 which is larger than the original bump 37', as shown in Fig. 3I. Thus, the contacts 37 having a large I/O size are soldered to the pads of the board, which can produce a large standing height, and therefore have better reliability according to the aforementioned Coffin-Mansion formula.

If the larger size of the bump is directly selected, although a larger standing height can be obtained, it is easy to cause the adjacent bump to be welded in the subsequent reflow process as described above. In contrast, the pre-welded layer 36 with a fixed position in the present case can not only produce a large standing height, but also avoid a short circuit caused by the offset of a large-sized bump (or a solder ball) in the reflow process. Therefore, this case can not only increase the reliability of the package components, but also is suitable for electronic products with fine pitch and high I/O contact numbers; and still utilizes the original photomask and process, so compared with the previous case The advantage of low cost (or no increase in cost). Taking the current ball-making process as an example, if the pitch of the I/O contacts is 400um, the maximum solder ball of about 250um diameter can be implanted, and the ball height after reflow is about 200um (assuming the bottom metal The layer diameter is 240um). If the steps taught in the foregoing embodiments of the present invention are employed, it is assumed that a pre-solder layer having a thickness of about 55 um is plated over the metal layer of the ball bottom, and the strip of the same 250 um diameter is used. Under the condition, the height of the solder ball after reflow can reach 220um, that is, the standing height can be increased by about 10%, and the Coffin-Mansion equation formula is used to estimate the fatigue resistance cycle (representing reliability) which can be increased by about 20%.

4A to 4D illustrate partial manufacturing steps of another embodiment of the present invention. The manufacturing steps of this embodiment are connected to the third embodiment of the pre-opening embodiment, that is, the third embodiment to the third embodiment are the manufacturing steps of the embodiment, and then the fourth embodiment is connected. Referring to FIG. 4A, the same photoresist layer 39 is used as a mask, a first pre-weld layer 461 having a high melting point is deposited on the ball-metal layer 35, and then a second pre-solder layer 462 is deposited on the first pre-layer. Solder layer 461. The second pre-solder layer 462 can be selected from the metal or alloy to which the subsequently bonded bumps can be fused to each other, or the same material as the pre-solder layer 36 of the pre-opening embodiment. The material of the first pre-solder layer 461 may be selected from a solder having a higher melting point, such as a tin-gold (Sn/Au) alloy, a tin-zinc (Sn/Zn) alloy, or the like.

Referring to Figure 4B, the photoresist layer 39 is removed. And the etch barrier layer 33 ′ and the seed layer 34 ′ are located in a partial region on both sides of the pre-solder layer 36 , and then the barrier layer 33 , the seed layer 34 , the ball-bottom metal layer 35 , the first pre-solder layer 461 and the second layer Part or all of the pre-solder layer 462 protrudes above the second passivation layer 32. Then, the flux 38 is applied to the ball metal layer 35 by screen printing or the like, and the bump 37' is ball mounted on the second pre-solder layer 462 as shown in Fig. 4C. The bump 37' and the second pre-solder layer 462 are fused by the reflow process, but the high-melting first pre-solder layer 461 is not fused with the bump 37' and the second pre-solder layer 462. Thus, an I/O contact 47 which is larger in size than the original bump 37' is formed as shown in Fig. 4D. Thus, the first pre-soldering layer 461 having a high melting point can more effectively increase the standing height of the solder ball, and therefore has a better reliability according to the aforementioned Coffin-Mansion formula, but since the diameter of the solder ball is not greatly increased, it is adjacent to The solder balls are not welded together.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, the generation of the feedback signal in the control loop of the present invention is not limited to being processed by an error amplifier, or the subtractor can be subtracted from the reference voltage to generate a feedback signal for each stage. Therefore, the scope of the invention should be construed as covering the above and all other equivalents.

31‧‧‧ wafer

311‧‧‧Substrate

312‧‧‧ solder pads

313‧‧‧First passivation layer

32‧‧‧Second passivation layer

33‧‧‧Barrier layer

34‧‧‧ seed layer

35‧‧‧Bottom metal layer

37‧‧‧I/O contacts

Claims (12)

A wafer level wafer scale package component comprising: a wafer including at least one pad; a ball bottom metal layer disposed on the pad; a pre-solder layer disposed on the ball bottom metal layer; and a bump And welding with the pre-welded layer. The wafer level wafer scale package component of claim 1, further comprising: a barrier layer disposed on the pad; and a crystal layer disposed on the barrier layer and on the ball Under the bottom metal layer. The wafer level wafer scale package component of claim 1, wherein the bump is a solder ball. The wafer level wafer scale package component according to claim 3, wherein the material of the pre-solder layer is selected from the group consisting of tin, tin-lead alloy, tin-zinc alloy, tin-silver alloy, tin-copper alloy or tin-silver-copper alloy. One. The wafer level wafer scale package component of claim 1, wherein the material of the pre-solder layer is selected from a metal or alloy that the bumps can be fused to each other. The wafer level wafer scale package component of claim 1, wherein the pre-solder layer and the bump are combined to form an I/O contact, and the size of the I/O contact is larger than the size of the bump. . A method of fabricating a wafer level wafer scale package component, comprising: providing a wafer having at least one pad; forming a ball bottom metal layer on the pad; forming a pre-solder layer on the ball bottom metal layer; and fusing A bump is bonded to the pre-weld layer. Manufacturer of wafer level wafer scale package components as described in claim 7 The method further includes: forming a barrier layer on the bonding pad; and forming a crystalline layer on the barrier layer and under the underlying metal layer. The method of manufacturing a wafer level wafer scale package component according to claim 7, wherein the bump is a solder ball. The method for manufacturing a wafer level wafer scale package component according to claim 9, wherein the material of the pre-solder layer is tin, tin-lead alloy, tin-zinc alloy, tin-silver alloy, tin-copper alloy or tin-silver. One of the copper alloys. The method of fabricating a wafer level wafer scale package component according to claim 7, wherein the material of the pre-solder layer is selected from a metal or an alloy in which the bumps can be fused to each other. The method for manufacturing a wafer level wafer scale package component according to claim 7, wherein the pre-solder layer and the bump are combined to form an I/O contact, and the size of the I/O contact is larger than the convex The size of the block.