CN101221914A - Semiconductor device with conductive bump and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor device with conductive projection and its making method, mainly providing a semiconductor substrate with a welding pad and a protective layer on the surface, the welding pad is exposed out of the protective layer to form a first metal layer on the welding pad, and the first metal layer covers the welding pad and part of the protective layer around the welding pad, then the protective layer and the first metal layer are covered with a second covering layer, and the second covering layer is formed with an opening of the first metal layer exposed out, wherein the center of the opening deviates a distance from the center of the welding pad, so as to form a metal column on the first metal layer in the opening and a soldering material on the surface of the metal column, thereby the metal column and the soldering material deviate a distance from the center of the welding pad, and can be simultaneously loaded on the first metal layer and the protective layer with larger bearing area, and further provide better buffer effect, so as to avoid the delamination problem of the bottom metal layer of the solder bump formed on the solder pad due to the stress transferred by the metal pillar.

Description

Semiconductor device with conductive bumps and manufacturing method thereof

technical field

The invention relates to a semiconductor device and its manufacturing method, in particular to a semiconductor device with conductive bumps and its manufacturing method.

Background technique

The traditional flip chip (Flip Chip) semiconductor packaging technology is mainly to form solder bumps (Solder Bump) on the pads of the chip, and then directly electrically connect with the carrier such as the substrate (Substrate) through the solder bumps. In terms of wire bonding, flip-chip technology has a shorter circuit path and better electrical quality. At the same time, it can be designed as an exposed crystal back, which can also improve chip heat dissipation.

Before forming solder bumps on the chip with the flip-chip technology, it is necessary to form the Under Bump Metallurgy (UBM) on the chip pads as disclosed in US Patent Nos. 6,111,321, 6,107,180, and 6,586,323. , so that the solder bumps can be firmly adhered to the chip pads. However, when the solder bumps of the chip are directly electrically connected to the substrate through reflow operation, the solder bumps will melt and collapse when heated to a certain high temperature, that is, the phenomenon of wetting. , the result of such excessive collapse may cause bridging between adjacent solder bumps, resulting in electrical failure.

Please refer to FIG. 1A. For this reason, U.S. Patents US6,229,220, US5,656,858, US5,466,635, and US6,578,754 etc. disclose a copper column with a height of about 30-90 μm on the metal layer 14 at the bottom of the solder block of the chip 10 pad 11 15, and then form solder material 16 on the copper pillar 15, so that when the chip 10 is electrically connected to the substrate (not shown) in a flip-chip manner, the chip 10 can be effectively supported by the copper pillar 15 to avoid existing soldering Bump melting collapse problem.

Although the above-mentioned conductive bumps with high support can absorb large thermal stress (thermal stress) when the thermal expansion coefficient difference between the chip and the substrate is large, but when applied to larger-sized chips, such as 15*15mm or more , for the conductive bumps containing copper pillars formed at the corners of the chip, the thermal stress they suffer is relatively large because they are far away from the center of the chip, which leads to the fact that the metal layer at the bottom of the solder bumps still cannot The stress transmitted by the copper pillar is effectively absorbed, and the problem of cracking and delamination C of the metal layer at the bottom of the solder block is extremely prone to occur here, as shown in FIG. 1B .

Therefore, how to provide a semiconductor device with conductive bumps, which can be applied to large-sized chips with conductive bumps with copper pillars, so as to effectively absorb the stress transmitted from the copper pillars, without causing damage to the metal layer at the bottom of the solder bumps. Problems such as cracking or delamination are actually important issues that the industry needs to deal with urgently.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide a semiconductor device with conductive bumps and a manufacturing method thereof, which can effectively absorb the stress transmitted by the metal pillars in the conductive bumps with metal pillars.

Another object of the present invention is to provide a semiconductor device with conductive bumps and its manufacturing method, which can avoid cracking or delamination of the metal layer at the bottom of the solder bumps formed on the bonding pads of large-sized chips in the prior art.

In order to achieve the above object and other objects, the present invention provides a method for manufacturing a semiconductor device with conductive bumps, comprising: providing a semiconductor substrate with a solder pad and a protective layer on the surface, the protective layer covering the semiconductor substrate and the outer surface exposing the pad; forming a first metal layer on the pad so that the first metal layer covers the pad and a part of the protective layer around it; covering the protective layer and the first metal layer with a second covering layer , and the second covering layer is formed with an opening that exposes part of the first metal layer, wherein the center of the opening is offset by a certain distance from the center of the pad; the first metal layer exposing the opening of the second covering layer forming a metal column on the metal column, and electrically connecting the metal column to the first metal layer; and forming solder material on the outer surface of the metal column.

In the aforementioned method of manufacturing a semiconductor device with conductive bumps, a second metal layer can be formed on the first metal layer in the opening that exposes the second cover layer, so that the second metal layer is in contact with the first metal layer. A metal layer is electrically connected; then forming metal pillars and solder material on the second metal layer.

In addition, the first cover layer can also be covered on the solder pad and the protection layer of the semiconductor base material first, and the first cover layer is formed with an opening to expose the solder pad, and then the second cover layer is formed on the first cover layer. A metal layer is provided, and the first metal layer is electrically connected to the welding pad.

The offset distance between the center of the opening of the second cover layer and the center of the pad is less than half of the width of the pad, preferably, the offset distance is a quarter of the width of the pad. The semiconductor substrate can be a semiconductor chip or wafer. The semiconductor substrate can be a semiconductor chip or a wafer, the protective layer can be a polyimide (polyimide) or silicon nitride (SiN) layer, and the first covering layer can be selected from benzo-cyclobutene (Benzo-Cyclo- One of the dielectric layers of Butene; BCB) and polyimide (Polyimide), the second cover layer can be a dielectric layer or a solder resist layer, and the first and second metal layers are, for example, the metal layer at the bottom of the solder block ( UBM).

The present invention further discloses a semiconductor device with conductive bumps, which includes: a semiconductor substrate with a solder pad and a protective layer on the surface, the protective layer covers the semiconductor substrate and exposes the solder pad; a first metal layer, A part of the protective layer formed on the pad and covering its surroundings; a second covering layer covering the protective layer and the first metal layer, and forming an opening that exposes a part of the first metal layer, wherein the center of the opening is offset A certain distance from the center of the pad; a metal column formed on the first metal layer exposing the opening of the second covering layer and electrically connected to the first metal layer; and a solder material formed on the outer surface of the metal column .

In addition, the aforementioned semiconductor device with conductive bumps further includes a second metal layer formed on the first metal layer exposing the opening of the second covering layer, and the second metal layer is connected to the first metal layer Electrically connected to form metal pillars and solder material on the second metal layer. The first and second metal layers are, for example, under-bump metallization (UBM).

Furthermore, the semiconductor device with conductive bumps may also include a first covering layer covering the protection layer and the welding pad of the semiconductor substrate, and the first covering layer is formed with an opening to expose the welding pad, thereby A first metal layer is formed on the first covering layer, and the first metal layer is electrically connected to the welding pad exposed on the first covering layer.

Compared with the prior art, the semiconductor device with conductive bumps of the present invention and its manufacturing method are mainly between the conductive bumps with metal pillars and the first metal layer such as the bottom metal layer (UBM) of solder bumps. A cover layer, and the cover layer is formed with an opening that exposes part of the first metal layer, and the center of the opening is offset from the center of the welding pad by a certain distance, and the offset distance is less than half of the width of the welding pad, so that The metal column and the solder material subsequently formed on the first metal layer exposing the opening of the cover layer are offset by a certain distance from the center of the pad, so as to be simultaneously loaded on the first metal layer and the protection with a larger bearing area. Layer and cover layer, thereby providing a better buffering effect, avoiding the existing solder bump bottom metal layer (UBM) formed directly on the chip pad when the chip size is large, because it cannot withstand the excessive stress of the metal pillar. Problems such as cracking and delamination occur.

Description of drawings

FIG. 1A is a schematic diagram showing the formation of conductive bumps with copper pillars on the metal layer at the bottom of the solder bumps of the chip;

FIG. 1B is a schematic diagram showing the delamination of the metal layer at the bottom of the solder bump caused by the excessive stress transmitted by the copper pillar in the conventional conductive bump;

2A to 2E are schematic diagrams showing a first embodiment of a semiconductor device with conductive bumps and a manufacturing method thereof of the present invention;

3 is a schematic diagram showing a second embodiment of a semiconductor device with conductive bumps of the present invention;

4 is a schematic diagram showing a third embodiment of a semiconductor device with conductive bumps of the present invention; and

FIG. 5 is a schematic diagram showing a fourth embodiment of a semiconductor device with conductive bumps of the present invention.

Symbol Description

10 chips

11 pads

14 Solder bump bottom metal layer

15 copper pillars

16 solder material

20 Semiconductor substrate

201 pad

202 protective layer

232 Second Overlay

232a opening

241 first metal layer

242 second metal layer

281 Metal Post

282 solder material

30 Semiconductor substrate

301 welding pad

302 protective layer

331 First Overlay

332 Second Overlay

332a opening

341 first metal layer

381 Metal Column

382 solder material

40 Semiconductor substrate

401 pad

402 protective layer

432 Second Overlay

432a hole

441 first metal layer

442 Second metal layer

481 Metal Post

482 solder material

50 Semiconductor substrate

501 pad

502 protective layer

531 First Overlay

532 Second Overlay

532a opening

541 first metal layer

542 Second metal layer

581 Metal Post

582 solder material

C Delamination

S distance

L pad width

Detailed ways

The following examples are technical means of the present invention in further detail, but are not intended to limit the scope of the present invention.

first embodiment

Please refer to FIG. 2A to FIG. 2E , which are schematic cross-sectional views showing a first embodiment of the semiconductor device with conductive bumps and its manufacturing method of the present invention.

As shown in Figure 2A, first, a surface is provided with a plurality of solder pads 201 and a semiconductor substrate 20 of a protective layer (Passivation Layer) 202 (in this figure, only the area covered by a single solder pad 201 is illustrated) . The semiconductor substrate 20 is, for example, a semiconductor chip or a wafer including a plurality of chip units. The surface of the semiconductor substrate 20 is covered with a protective layer 202 , and the protective layer 202 is formed with holes to expose the pads 201 . The material of the protective layer 202 is, for example, polyimide (PI), which is used to protect the semiconductor substrate 20 .

As shown in FIG. 2B , the first metal layer 241 is directly formed on the semiconductor substrate 20 , and the first metal layer 241 is electrically connected to the pad 201 exposed on the protection layer 202 . The first metal layer 241 is, for example, an under-bump metal layer (UBM), which may be selected from a combination of metal aluminum, nickel-vanadium alloy, metal copper, and metal titanium.

As shown in FIG. 2C , the protective layer 202 and the first metal layer 241 are covered with a second covering layer 232 , and an opening 232 a exposing part of the first metal layer 241 is formed in the second covering layer 232 , And the center of the opening 232 a is offset by a distance S from the center of the solder pad 201 , and the offset distance S is less than half of the width L of the solder pad 201 . The distance S shown in the drawing is equal to a quarter of the width L of the welding pad 201, but it is not limited thereto. For example, any offset distance S that is less than half the width L of the welding pad 201 is a In a practicable range, preferably, the offset distance S is a quarter of the width of the pad 201 . The second covering layer 232 can be selected from one of a dielectric layer and a solder mask (Solder Mask), and the dielectric layer can be selected from benzocyclobutene (BCB) or polyimide (PI).

As shown in FIG. 2D , metal pillars 281 such as copper pillars are formed on the first metal layer 241 exposing the openings 232 a of the second covering layer by electroplating, so that the metal pillars 281 are electrically connected to the first metal layer 281 . Metal layer 24.

As shown in FIG. 2E , a cap-shaped solder material 282 is formed on the outer surface of the metal pillar 281 .

Through the aforementioned manufacturing method, the present invention further discloses a semiconductor device with conductive bumps, which includes a semiconductor substrate 20 with a solder pad 201 and a protective layer 202 on the surface. The protective layer 202 covers the semiconductor substrate 20 and the outer surface The pad 201 is exposed; the first metal layer 241 is formed on the pad 201 and covers part of the protective layer 202 around it; the second covering layer 232 covers the protective layer 202 and the first metal layer 241, and is formed with The opening 232a of the exposed part of the first metal layer 241, wherein the center of the opening 232a is offset by a certain distance from the center of the pad 201; the metal column 281 is formed on the first metal layer exposing the opening 232a of the second covering layer 241 and is electrically connected to the first metal layer 241 ; and a solder material 282 is formed on the outer surface of the metal pillar 281 .

That is to say, the semiconductor device with conductive bumps of the present invention and its manufacturing method are mainly to add a cover layer between the conductive bumps with metal pillars and the first metal layer such as the bottom metal layer (UBM) of solder bumps, and the The cover layer is formed with an opening that exposes a part of the first metal layer, and the center of the opening is offset from the center of the pad by a distance, the offset distance is less than half of the width of the pad, so that the subsequent formation on the outer The metal column and the solder material on the first metal layer exposing the opening of the cover layer are offset from the center of the pad by a certain distance, so as to be supported on the first metal layer and the protective layer and cover layer with a larger bearing area at the same time , thereby providing a better cushioning effect, and avoiding cracks and detachment of the solder bump bottom metal layer (UBM) formed directly on the chip pad when the chip size is large, because it cannot bear the excessive stress of the metal pillar. layers etc.

second embodiment

Please refer to FIG. 3 , which is a schematic cross-sectional view of a second embodiment of a semiconductor device with conductive bumps of the present invention. The semiconductor device with conductive bumps of this embodiment is substantially the same as the previous embodiment, and the main difference is when the semiconductor substrate When the material of the protective layer is, for example, nitride (such as silicon nitride), a first covering layer can be covered on the protective layer first, and then a first metal layer, a second covering layer, a metal layer, and a metal layer can be sequentially formed on the first covering layer. pillars and solder material.

The semiconductor device with conductive bumps includes a semiconductor substrate 30 with a solder pad 301 and a protective layer 302 on its surface; a first covering layer 331 covering the protective layer 302 and exposing the solder pad 301; a first metal layer 341, formed on the pad 301 and covering part of the first covering layer 331 around it; the second covering layer 332, covering the first covering layer 331 and the first metal layer 341, and forming an exposed part of the first The opening 332a of the metal layer 341, wherein the center of the opening 332a is offset by a certain distance from the center of the pad 301; the metal post 381 is formed on the first metal layer 341 exposing the opening 332a of the second covering layer; and solder The material 382 is, for example, a ball, and is formed on the outer surface of the metal post 381 .

The first cover layer 331 is selected from one of benzenecyclobutene and polyimide, the second cover layer 332 is selected from one of dielectric layer and solder resist layer, and the first metal layer 341 is, for example, solder The bottom block metal layer (UBM).

third embodiment

Please refer to FIG. 4 , which is a schematic cross-sectional view of a third embodiment of a semiconductor device with conductive bumps according to the present invention. The semiconductor device with conductive bumps in this embodiment is substantially the same as that of the first embodiment, with the main difference being the semiconductor substrate. The first metal layer 441 is directly formed on the solder pad 401 and the protective layer 402 on the surface of the 40, and the first metal layer 441 is electrically connected to the solder pad 401 exposed on the protective layer 402, and then the first metal layer 441 And the protective layer 402 is covered with the second cover layer 432, and the second cover layer 432 is formed with an opening 432a to expose part of the first metal layer 441, wherein the center of the opening 432a is offset from the center of the welding pad 401 by a certain distance, Then form a second metal layer 442 on the first metal layer 441 in the opening 432a exposing the second covering layer 432, so that the second metal layer 442 is electrically connected to the first metal layer 441, and then A metal post 481 and a cap-shaped solder material 482 are formed on the second metal layer 442 .

Fourth embodiment

Please refer to FIG. 5 , which is a schematic cross-sectional view of a fourth embodiment of a semiconductor device with conductive bumps according to the present invention. The semiconductor device with conductive bumps in this embodiment is substantially the same as the aforementioned second embodiment. The semiconductor device includes a semiconductor substrate 50 with a solder pad 501 and a protective layer 502 on its surface; a first covering layer 531 covering the protective layer 502 and exposing the solder pad 501; a first metal layer 541 formed on the Part of the first covering layer 531 on the pad 501 and covering its surroundings; the second covering layer 532 covers the first covering layer 531 and the first metal layer 541, and is formed with openings exposing part of the first metal layer 541 532a, wherein the center of the opening 532a is offset by a certain distance from the center of the pad 501; the second metal layer 542 is formed on the first metal layer 541 exposing the opening 532a of the second covering layer, and the second metal layer The layer 542 is electrically connected to the first metal layer 541 ; the metal post 581 is formed on the second metal layer 542 ; and the solder material 582 is formed on the outer surface of the metal post 581 such as a ball.

The first and second metal layers 541, 542 are, for example, UBM, so that the metal post 581 can be fully supported on the second metal layer (UBM) 542 to strengthen the bonding. Effect.

In this way, the conductive bump with the metal pillar and the solder material can be relatively offset by a certain distance from the center of the pad, so that it can be simultaneously loaded on the first metal layer and the protective layer and cover layer with a larger bearing area, and then Provide better cushioning effect.

However, the specific embodiments described above are only used to illustrate the characteristics and effects of the present invention, rather than to limit the scope of the present invention. Without departing from the spirit and technical scope of the present invention, any application of the present invention Equivalent changes and modifications accomplished by the disclosed content should still be covered by the scope of the claims of the present invention.

Claims (18)

1. A method for manufacturing a semiconductor device with conductive bumps, comprising: Provide a semiconductor substrate with a solder pad and a protective layer on its surface, the protective layer covers the semiconductor substrate and exposes the solder pad; forming a first metal layer on the pad, so that the first metal layer covers the pad and a part of the protective layer around it; Covering the protective layer and the first metal layer with a second covering layer, and forming an opening in the second covering layer exposing a part of the first metal layer, wherein the center of the opening is offset by a certain distance from the center of the pad; forming a metal post on the first metal layer exposing the opening of the second covering layer, and electrically connecting the metal post to the first metal layer; and Solder material is formed on the outer surface of the metal pillar. 2. The method for manufacturing a semiconductor device with conductive bumps according to claim 1, wherein the bonding pad and the protective layer of the semiconductor substrate are covered with a first covering layer, and the first covering layer exposing the welding pad, forming a first metal layer on the first covering layer, and electrically connecting the first metal layer to the welding pad, so as to successively form the second covering layer on the first metal layer , metal pillars and solder materials. 3. The method for manufacturing a semiconductor device with conductive bumps according to claim 2, wherein the protective layer is a silicon nitride layer, and the first covering layer is selected from one of benzocyclobutene and polyimide , the second covering layer is selected from one of the dielectric layer and the solder resist layer. 4. The method for manufacturing a semiconductor device with conductive bumps according to claim 1 or 2, wherein a second metal layer is formed on the first metal layer exposing the opening of the second cover layer, and the The second metal layer is electrically connected to the first metal layer to form the metal column and solder material on the second metal layer. 5. The method of manufacturing a semiconductor device with conductive bumps according to claim 4, wherein the first and second metal layers are solder bump bottom metal layers. 6 . The method for manufacturing a semiconductor device with conductive bumps according to claim 1 , wherein the protective layer is polyimide, and the second covering layer is selected from one of a dielectric layer and a solder resist layer. 7 . The method for manufacturing a semiconductor device with conductive bumps according to claim 1 , wherein the semiconductor substrate is one of a semiconductor chip and a wafer with a plurality of chip units. 8. The method for manufacturing a semiconductor device with conductive bumps according to claim 1, wherein the offset distance between the center of the opening of the second cover layer and the center of the pad is less than half of the width of the pad, Preferably it is a quarter. 9 . The method for manufacturing a semiconductor device with conductive bumps according to claim 1 , wherein the solder material is one of a cap shape and a ball shape. 10. A semiconductor device with conductive bumps, comprising: A semiconductor substrate with a solder pad and a protective layer on its surface, the protective layer covers the semiconductor substrate and exposes the solder pad; The first metal layer is formed on the pad and covers part of the protective layer around it; A second covering layer, covering the protection layer and the first metal layer, and forming an opening exposing a part of the first metal layer, wherein the center of the opening is offset by a certain distance from the center of the welding pad; a metal post formed on the first metal layer exposing the opening of the second covering layer; and The solder material is formed on the outer surface of the metal column. 11. The semiconductor device with conductive bumps according to claim 10, further comprising a first cover layer covering the solder pads and the protective layer of the semiconductor base material, and making the first cover layer expose the solder pads. pad, and then form a first metal layer on the first covering layer, and make the first metal layer electrically connected to the welding pad, so as to successively form the second covering layer, the metal column and the welding pad on the first metal layer. Solder material. 12. The semiconductor device with conductive bumps according to claim 11, wherein the protection layer is a silicon nitride layer, the first covering layer is selected from one of benzocyclobutene and polyimide, and the first covering layer is The two covering layers are selected from one of the dielectric layer and the solder repelling layer. 13. The semiconductor device with conductive bumps according to claim 10 or 11, further comprising a second metal layer formed on the first metal layer exposing the opening of the second covering layer, and making the second metal layer The metal layer is electrically connected to the first metal layer to form the metal column and solder material on the second metal layer. 14. The semiconductor device with conductive bumps according to claim 13, wherein the first and second metal layers are bottom metal layers of solder bumps. 15. The semiconductor device with conductive bumps according to claim 10, wherein the protection layer is polyimide, and the second covering layer is selected from one of a dielectric layer and a solder resist layer. 16. The semiconductor device with conductive bumps according to claim 10, wherein the semiconductor substrate is one of a semiconductor chip and a wafer with a plurality of chip units. 17. The semiconductor device with conductive bumps according to claim 10, wherein the offset distance between the center of the opening of the second covering layer and the center of the pad is less than half of the width of the pad, preferably a quarter. 18. The semiconductor device with conductive bumps according to claim 10, wherein the solder material is one of a cap shape and a ball shape.

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