TWI455281B - Ic封裝體、堆疊式ic封裝器件及製造方法 - Google Patents
Ic封裝體、堆疊式ic封裝器件及製造方法 Download PDFInfo
- Publication number
- TWI455281B TWI455281B TW096122032A TW96122032A TWI455281B TW I455281 B TWI455281 B TW I455281B TW 096122032 A TW096122032 A TW 096122032A TW 96122032 A TW96122032 A TW 96122032A TW I455281 B TWI455281 B TW I455281B
- Authority
- TW
- Taiwan
- Prior art keywords
- package
- die
- substrate
- sealing material
- interconnecting
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims description 92
- 239000003566 sealing material Substances 0.000 claims description 82
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 238000007789 sealing Methods 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 description 63
- 238000000034 method Methods 0.000 description 25
- 239000004033 plastic Substances 0.000 description 24
- 239000000463 material Substances 0.000 description 21
- 239000012778 molding material Substances 0.000 description 16
- 239000004020 conductor Substances 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000007769 metal material Substances 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 6
- 239000011162 core material Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 239000011135 tin Substances 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000010137 moulding (plastic) Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000012811 non-conductive material Substances 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- UHNRLQRZRNKOKU-UHFFFAOYSA-N CCN(CC1=NC2=C(N1)C1=CC=C(C=C1N=C2N)C1=NNC=C1)C(C)=O Chemical compound CCN(CC1=NC2=C(N1)C1=CC=C(C=C1N=C2N)C1=NNC=C1)C(C)=O UHNRLQRZRNKOKU-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000011258 core-shell material Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92127—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1076—Shape of the containers
- H01L2225/1088—Arrangements to limit the height of the assembly
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
本發明涉及積體電路(IC)器件封裝技術,更具體地說,涉及IC封裝中封裝體與封裝體之間的相互連接。
晶粒朝上塑膠球柵陣列封裝(PBGA)是由Motorola公司最早開發的,稱為整體模塑陣列載體(OMPAC)。參見Freyman和Pennisi著的“Overmolded Plastic Pad Array Carriers(OMPAC):A Low Cost,High Interconnect Density IC Packaging Solution for Consumer and Industrial Electronics”,Electronic Components and Technology Conference,IEEE,pp.176-182,(1991),此處全文引用其內容。
PBGA封裝中包括塑膠印刷電路板(基片),通常由BT(Bismaleimide Triazine)樹脂或FR4材料製成。圖1是傳統PBGA封裝體100的示意圖。積體電路(IC)晶粒102借助晶粒粘合材料106直接粘貼在基片110的上表面。焊線114將IC晶粒102的積體電路電連接至基片110的印刷電路。基片110的下表面安裝有焊球108矩陣。塑膠塑封材料112保護晶粒102和焊線114免受外界影響。塑封材料112將晶粒102和焊線114都密封起來,並覆蓋住基片110上表面的中部區域。基片110上表面的週邊部分裸露。圖2A-2B示出了PBGA封裝體100的俯視圖和側視圖。
傳統PBGA封裝體(如封裝體100)存在許多缺陷,包括(1)厚的頂部塑封(mold)層(例如塑封材料112)導致整體封裝高度過大;(2)由於塑封帽必須夾緊在封裝基片110上以便進行塑封,因而晶粒尺寸與封裝體的尺寸比很小;(3)整個封裝體尺寸大。
電子元件工業聯合會(JEDEC)針對PBGA封裝制定的塑封厚度標準為1.17mm。在塑封厚度為1.17mm的情況下,一般PBGA封裝體的整體高度介於1.5mm~2.5mm之間。然而,對於許多應用而言更希望採用厚度較薄的封裝體,諸如掌上型通信設備(如手機、全球定位設備、腕表式通信設備等)、移動多媒體(視頻/音頻)播放器、無線個人區域網設備(如藍牙耳麥)、快閃記憶體設備或存儲卡等應用。
在對JEDEC標準的PBGA封裝體進行塑封密封時,需使用帶有多個塑封帽(塑封空腔)的塑封模。PBGA封裝體的基片通常在基片條或基片板上成型。基片條或基片板上,每一個獨立的基片單元都帶有一個對應的用於進行塑封的塑封模的塑封帽。通常,要在每一個塑封帽中加入熱固型塑封環氧樹脂,且塑封模放置在基片條上。封裝完成後,每個基片上表面的外周都是裸露的(即未被塑封材料112覆蓋),如圖1、2A和2B所示。在使用塑封材料之前,IC晶粒和焊線都必須放置到塑封空腔內。另外,IC晶粒和焊線都必須與塑封空腔的內壁相隔一定距離,以便塑封材料流動及避免引線彎折(wire sweeping)。從而IC晶粒的尺寸受到塑封帽(即塑封空腔)尺寸的限制。因此對於PBGA封裝而言晶粒的最大尺寸必須小於基片尺寸。
如此使得PBGA封裝體通常為大於19mm X 19mm的大體積尺寸。對於移動應用而言不希望IC封裝尺寸過大,因為採用大體積的電子器件必將製造出大體積設備。
為減小封裝體尺寸,業界已開發出IC晶粒尺寸非常接近封裝體尺寸的晶片級封裝。圖3A和3B分別為精細間距球柵陣列(FBGA)封裝體300的剖面圖和截面圖。與上述PBGA封裝體100相似,晶粒102通過晶粒粘合材料106貼裝在基片110上。IC晶粒102通過多條焊線114電連接至導電體(例如迹線(trace)、鍵合手指等),如基片110上表面的導電迹線(trace)310。塑封材料112將晶粒102、焊線114和基片110的整個上表面密封住。FBGA封裝體300的焊球108可以小於PBGA封裝體100的焊球108,且FBGA封裝體300的焊球間距也較小。除焊球108尺寸和球間距較小外,塑封材料112的厚度也減小到0.25mm~0.7mm。塑封材料112覆蓋了FBGA封裝300體的整個上表面,使得與PBGA封裝100相比,FBGA封裝體300中晶粒102與基片110的尺寸比增大。
然而,在進行一些改進時,FBGA封裝體中還存在與上述PBGA有關的一些缺陷。因此,有必要開發出具有小尺寸並適用於大規模、複雜積體電路的IC封裝。
本發明涉及用於積體電路(IC)封裝的封裝垂直互連的方法、系統和裝置。本發明涉及多種IC封裝類型,包括球柵陣列(BGA)封裝。
根據本發明的一方面,改造後的第一IC封裝體外露出多個互連接觸焊盤(interconnect contact pads)。第一封裝體上堆疊有一個BGA封裝體。在一實施例中,安裝在BGA封裝體下表面的焊球連接到互連構件(interconnect members),該互連構件可觸及(accessible)第一IC封裝體的上表面。
根據本發明的一方面,IC封裝體包括帶有晶粒接觸焊盤的IC晶粒。IC晶粒封裝在密封材料如塑封材料中。IC封裝體還包括互連構件,該互連構件電連接於晶粒接觸焊盤上的IC晶粒,從而在IC封裝體的外表面形成互連接觸焊盤。
根據本發明的另一方面,IC封裝體包括安裝在基片第一表面的IC晶粒。IC封裝體還包括電連接於基片第一表面的互連構件。IC晶粒和互連構件密封在密封材料中。互連構件的頂部未被密封材料密封,從而在IC封裝體的外表面形成互連接觸焊盤。
根據本發明的再一方面,密封材料中形成一凹腔,在該凹腔處互連接觸焊盤外露。
根據本發明的一方面,第一IC封裝體包括晶粒、一個或多個互連接構件、基片、用於密封晶粒和互連構件的密封材料。第一IC封裝體通過互連構件電連接于第二IC封裝體。
根據本發明的一方面,一種IC封裝體的製造方法,包括以下步驟:將IC晶粒貼裝到基片上,將互連構件電連接至晶粒和/或基片,通過焊線鍵合工藝將晶粒電連接至基片,密封封裝體,且使至少一部分互連構件的至少一部分外露。
根據本發明的一方面,通過移除一整層密封材料使互連構件外露。另一方面,通過在密封材料中形成凹腔而使互連構件外露。
根據本發明的一方面,一種進行PoP(Package on Package)堆疊的方法。包括以下步驟:利用晶粒粘合材料將IC晶粒貼裝到基片的第一表面上。將互連構件電連接至晶粒和/或基片的第一表面。採用焊線鍵合工藝將晶粒電連接至基片。在本方法中,形成第一IC封裝體。將第一封裝體密封在密封材料中。使互連構件至少部分外露。將第二IC封裝體安裝到第一IC封裝體上。
根據本發明的一方面,提供一種積體電路(IC)封裝體,包括:帶有多個接觸焊盤的IC晶粒;連接於所述多個接觸焊盤的多個互連構件;密封所述IC晶粒和互連構件的密封材料,其使得每個互連構件的接觸面在密封材料的表面均可觸及(accessible)。
在本發明的IC封裝體中,所述每個互連構件都是截去頂部的焊球。
在本發明的IC封裝體中,所述密封材料的表面有一凹腔,在所述凹腔內每個互連構件的接觸表面均可觸及(accessible)。
在本發明的IC封裝體中,還包括:基片,其第一表面安裝有IC晶粒;第二組多個互連構件;其中所述基片的第一表面設有多個接觸焊盤;其中所述第二組互連構件中的每一個都與所述基片第一表面上的多個接觸焊盤中對應的一個接觸焊盤相連接;其中所述密封材料將第二組互連構件密封住,並使第二組互連構件中的每一個互連構件的接觸表面在密封材料的表面均可觸及(accessible)。
在本發明的IC封裝體中,所述多個互連構件中的每一個互連構件均包含金屬材料。
在本發明的IC封裝體中,所述金屬材料包括金、銅、鋁、銀、鎳、錫或金屬合金。
在本發明的IC封裝體中,所述多個互連構件中的每一個互連構件均包含導熱環氧材料。
在本發明的IC封裝體中,所述多個互連構件中的每一個互連構件均包含由鍵合材料(bonding material)包裹的內核材料。
在本發明的IC封裝體中,所述多個互連構件中的每一個互連構件均包含導電柱。
根據本發明的一方面,提供一種堆疊式IC封裝器件,包括第一IC封裝體,其包括:帶有多個接觸焊盤的IC晶粒;連接於所述多個接觸焊盤的多個互連構件;密封所述IC晶粒和互連構件的密封材料,其使得每個互連構件的接觸面在密封材料的表面均可觸及(accessible);及通過第一IC封裝體的多個互連構件連接到所述第一IC封裝體的第二IC封裝體。
在本發明的堆疊式IC封裝器件中,所述密封材料的表面有一凹腔,在所述凹腔內每個互連構件的接觸表面均可觸及(accessible);其中所述第二IC封裝體至少有一部分佈置在所述凹腔內。
在本發明的堆疊式IC封裝器件中,每一個互連構件均為截去頂部的焊球。
在本發明的堆疊式IC封裝器件中,第一IC封裝體還包括:基片,其第一表面安裝有IC晶粒;第二組多個互連構件;其中所述基片的第一表面設有多個接觸焊盤;其中所述第二組互連構件中的每一個都與所述基片第一表面上的多個接觸焊盤中對應的一個接觸焊盤相連接;其中所述密封材料將第二組互連構件密封住,並使第二組互連構件中的每一個互連構件的接觸表面在密封材料的表面均可觸及(accessible);其中所述第二IC封裝體通過第二組多個互連構件連接至第一IC封裝體。
在本發明的堆疊式IC封裝器件中,所述第二IC封裝體還包括貼裝在第二IC封裝體底部的多個焊球;其中,多個焊球中的每一個焊球都連接於所述多個互連構件中對應的一個互連構件的接觸表面。
在本發明的堆疊式IC封裝器件中,所述多個互連構件中的每一個互連構件均包含金屬材料。
在本發明的堆疊式IC封裝器件中,所述金屬材料包括金、銅、鋁、銀、鎳、錫或金屬合金。
在本發明的堆疊式IC封裝器件中,所述多個互連構件中的每一個互連構件均包含導熱環氧材料。
在本發明的堆疊式IC封裝器件中,所述多個互連構件中的每一個互連構件均包含由鍵合材料(bonding material)包裹的內核材料。
在本發明的堆疊式IC封裝器件中,所述多個互連構件中的每一個互連構件均包含導電柱。
根據本發明的一方面,提供一種製造IC封裝體的方法,包括:(a)將IC晶粒貼裝在基片的第一表面上,所述晶粒帶有多個接觸焊盤;(b)將多個互連構件連接至所述多個接觸焊盤;(c)使用至少一條焊線將晶粒連接於基片;(d)將晶粒和多個互連構件密封在密封材料中;(e)至少部分地裸露出多個互連構件以使每個互連構件的接觸面在密封材料的表面均可觸及(accessible)。
本發明的製造IC封裝體的方法還包括:(f)將多個焊球安裝於所述基片的第二表面。
本發明的製造IC封裝體的方法還包括:移除一層密封材料。
本發明的製造IC封裝體的方法還包括:在密封材料中形成一凹腔。
在本發明的製造IC封裝體的方法中:先執行步驟(c),再執行步驟(b)。
在本發明的製造IC封裝體的方法中:先執行步驟(b),再執行步驟(c)。
根據本發明的一方面,提供一種製造堆疊式IC封裝器件的方法,包括:(a)製造第一封裝體,包括:(1)將IC晶粒貼裝在基片的第一表面上,所述晶粒帶有多個接觸焊盤;(2)將多個互連構件連接至所述多個接觸焊盤;(3)使用至少一條焊線將晶粒連接到基片上;(4)將晶粒和互連構件密封在密封材料中;(5)至少部分裸露出多個互連構件以使每個互連構件的接觸面在密封材料的表面均可觸及(accessible);(b)通過第一IC封裝體的多個互連構件將第二IC封裝體連接至第一IC封裝體上。
本發明的製造堆疊式IC封裝器件的方法還包括:(6)將多個焊球安裝於所述基片的第二表面。
在本發明的製造堆疊式IC封裝器件的方法中,步驟(a)(5)還包括:移除一層密封材料。
在本發明的製造堆疊式IC封裝器件的方法中,步驟(a)(5)還包括:在密封材料中形成一凹腔。
在本發明的製造堆疊式IC封裝器件的方法中,先執行步驟(a)(3),再執行步驟(a)(2)。
在本發明的製造堆疊式IC封裝器件的方法中,先執行步驟(a)(2),再執行步驟(a)(3)。
在本發明的製造堆疊式IC封裝器件的方法中,第二封裝體具有貼裝在第二IC封裝體底面的多個焊球,其中步驟(b)包括:將多個焊球中的每一個焊球都連接至所述多個互連構件中對應的一個互連構件的接觸表面。
根據本發明的一方面,提供一種IC封裝體,包括:基片,其第一表面設置有多個接觸焊盤;安裝在所述基片第一表面的IC晶粒;連接於所述多個接觸焊盤的多個互連構件;密封所述IC晶粒和互連構件的密封材料,其使得每個互連構件的接觸面在密封材料的表面均可觸及(accessible)。
在本發明的IC封裝體中,所述每個互連構件都是截去頂部的焊球。
在本發明的IC封裝體中,所述多個互連構件中的每一個互連構件均包含金屬材料。
在本發明的IC封裝體中,所述金屬材料包括金、銅、鋁、銀、鎳、錫或金屬合金。
在本發明的IC封裝體中,所述多個互連構件中的每一個互連構件均包含導熱環氧材料。
在本發明的IC封裝體中,所述多個互連構件中的每一個互連構件均包含由鍵合材料(bonding material)包裹的內核材料。
根據本發明的一方面,提供一種製造IC封裝體的方法,包括:(a)將IC晶粒貼裝在基片的第一表面上,所述基片的第一表面帶有多個接觸焊盤;(b)將多個互連構件連接至所述多個接觸焊盤;(c)使用至少一條焊線將晶粒連接到基片;(d)將晶粒和多個互連構件密封在密封材料中;(e)至少部分地裸露出多個互連構件以使每個互連構件的接觸面在密封材料的表面均可觸及(accessible)。
在下面將要進行的對本發明的詳細描述中,上述和其他部件、優勢和特徵將變得更加明顯。應注意的是,發明內容和摘要部分可能使用一個或多個實施例,但並未列出發明人可能補充的有關本發明的全部示範性實施例
本文描述了有關IC器件封裝技術的方法、系統和裝置。更具體地說,描述了在IC封裝中有關封裝體與封裝體互連的方法、系統和裝置,以改進IC封裝。
本說明書中提及的“一個實施例”、“實施例”、“示例性實施例”等等指的是所描述的實施例可能包括某特定特徵、結構或特點,但是並不是每一個實施例都必定包括該特定特徵、結構或特點。此外,這些短語不一定指的是同一個實施例。還有,當結合某一實施例描述某特定特徵、結構或特點時,無論是否明確說明,可以認為本領域的技術人員能夠將這些特定特徵、結構或特點結合到其他實施例中。
本說明書公開了結合有本發明特徵的一個或多個實施例。所公開的實施例僅僅是對本發明的舉例,本發明的範圍不局限於所公開的實施例,而由本申請的權利要求來定義。
此外,需要理解的是,本文中所使用的與空間方位有關的描述(例如“上面”、“下面”、“左邊”、“右邊”、“向上”、“向下”、“頂部”、“底部”等)僅僅是出於舉例解釋的目的,本申請中所介紹的結構的實際實現可以具有各種不同的方位或方式。
在一實施例中,封裝體與封裝體互連結構為第一封裝體的晶粒提供了透過第一IC封裝體的密封材料實現與第二IC封裝體電連接的扭帶。互連結構提供了互連接觸焊盤以連接第二IC封裝體的焊球。用於連接第二IC封裝體底部焊球陣列的第一IC封裝的互聯構件陣列為一個互聯接觸焊盤陣列。第一IC封裝體的這種互連構件陣列在第一IC封裝體與第二IC封裝體的電接線端之間提供了較短的互連路徑。第一和第二IC封裝體組合起來構成了具有可容納至少兩個IC晶粒的結構緊湊的第三IC封裝體。
傳統IC晶粒的密封工藝如圍堰填充(dam and fill)(球形頂部glob top)、塑封帽注入塑封(轉移塑封)、以及基片條或板過塑封(塑封材料覆蓋住封裝體基片的邊緣)等都可用於第一和第二封裝體。本發明的實施例可應用于許多現有封裝技術,包括球柵陣列(BGA)封裝(例如精細間距BGA(FBGA)、塑膠BGA(PBGA))、柵格陣列(LGA)封裝、和導線架式封裝。此外,不同封裝類型都可進行堆疊以構成改進型IC封裝,包括將導線架式封裝體堆疊在BGA封裝體上、將BGA封裝體堆疊在導線架式封裝體上、及其它各種組合方式。雖然說明書的詳細描述中採用了第一和第二封裝體這種術語,但本領域的技術人員應當知曉,第二封裝體可能是另一個“第二封裝體”的“第一封裝體”等。如此,在實施例中,堆疊可以包括兩個或多個IC封裝體在內的若干個堆疊的IC封裝體。
PBGA和FBGA封裝都是傳統IC封裝的例子。PoP(Package on Package)堆疊式IC封裝亦稱為“封裝體可堆疊式超薄精細間距球柵陣列(PSvFBGA)”。參見Dreiza等人所著“Implement Stacked Package-on-Package Designs”(http://www.eetasia.com/ARTICLES/2005OCT/B/2005OCT17_EDA_MFG_A.pdf)(下文簡稱Dreiza),此處全文引用其內容。圖4A-4B所示為堆疊式PSvFBGA封裝的示意圖。圖4A示出了堆疊式IC封裝體400的示意圖。如圖4A所示,堆疊式封裝體400包括封裝體與封裝體互連結構,其是將在上BGA封裝體430安裝到下BGA封裝體440的基片410上而構成的。上、下BGA封裝體430、440是超精細間距BGA封裝體。
下封裝體440基片110的上表面外露有平面焊盤420,以便為上BGA封裝體430下表面的焊球108提供接觸面。外露的平面焊盤420位於基片110上表面的週邊,其圍繞著下封裝體440上表面的塑封材料112。可以採用傳統的回流焊表面安裝工藝將上封裝體430貼裝到下封裝體440上。
圖4B所示的堆疊式封裝體450包括封裝體與封裝體互連結構,其是將在上BGA封裝體480安裝到下BGA封裝體490的基片410上而構成的。上、下BGA封裝體480、490是超精細間距BGA封裝。由於下封裝體490的IC晶粒406處於穿透封裝體490基片410所開設的一個窗口內,因而堆疊式IC封裝450的整體封裝堆疊高度減小。
然而在這種配置中,下封裝體490的晶粒406尺寸受到限制。如圖4A所示,上封裝體430和下封裝體440之間的互連是通過下封裝體440基片410的週邊區域(塑封材料112外部)實現的。下封裝體440的IC晶粒406和焊線114必須採用塑封材料112密封住。這樣,塑封帽的尺寸必須精心設計,以防止塑封材料112覆蓋或污染外露的平面焊盤420。塑封帽的空腔必須小於基片410。這樣,下IC封裝體440必須與PBGA(如圖2A-2B)相似,而不能是基片410的週邊被塑封材料112覆蓋那樣的過度塑封類型(例如圖3A-3B的FBGA封裝體300)。這樣下封裝體440的晶粒406的尺寸受到限制,以使晶粒406和焊線114都置於塑封材料112中,而塑封材料112的尺寸必須使基片410的外周裸露。
此外,在一些情形下,通過為上封裝體和下封裝體選用相同尺寸和類型的封裝(即完全相同的結構、晶粒尺寸、基片和/或晶粒託盤結構等)而使上封裝體和下封裝體之間的機械應力最小化是有益的。在這種配置情況下,上、下封裝體是PBGA封裝或類似的封裝類型,晶粒尺寸與基片尺寸之比很小(poor)。傳統堆疊式IC封裝缺少一種對於給定的下封裝體尺寸能使晶粒尺寸最大化的互連結構。將在下一節描述的本發明的實施例,能夠使堆疊中的下封裝體的晶粒尺寸增大。
FBGA封裝(如以上所討論,例如圖3A-3B所示的封裝體300)具有更好的晶粒與基片尺寸比及更薄的塑封模。這樣,堆疊式FBGA封裝可以減小整體佔用面積(footprint)和整體堆疊高度(或在給定的高度下堆疊更多的封裝體)。因此,期望有一種堆疊FBGA封裝的方法。將在下一節描述的本發明的實施例,能夠對FBGA封裝進行堆疊。
另外,許多應用需要在IC晶片之間進行高速和高帶寬信令傳輸(例如集成了高速語音、資料和視頻功能的3G無線通信)。為支援這些應用,需要降低堆疊的封裝體之間的互連電阻抗。因而,期望在PoP堆疊結構中使晶粒與封裝體的互連更加直接。將在下一節描述的本發明的實施例,能夠使堆疊中的晶粒與封裝體更直接地互連。
過度塑封區域陣列封裝(諸如FBGA和平面柵(LGA)封裝)在封裝體的上表面沒有電信號互連端子。某些類型的導線架式封裝也存在相同的問題,諸如方形扁平無引線封裝(QFN)(也稱為微引線架封裝(MLP、MLF)、塑膠無引線晶片託盤(PLCC)封裝、及纖薄陣列塑膠(TAPP)封裝。因而,這些封裝類型的上面不能夠堆疊其他封裝體。因此,需要一種堆疊過度塑封封裝體的方法。將在下一節描述的本發明的實施例,能夠進行這種堆疊。
在一個實施例中,多個互連構件使能實現PoP互連,以將第二IC封裝體堆疊在第一封裝體上面。互連構件可以是導電球體(例如焊球)、塊、結、或其他規則和/或不規則體/材料,以透過第一IC封裝體的密封材料進行電連接。
附圖中,互連構件都採用球形來表示,如焊球。但是,互連構件的這種表示法只是出於舉例說明的目的,本發明不限於此。在本發明的不同實施例中,任意形狀的任意導電材料都可以當作互連構件。例如,作為一種選擇,互連構件可以是導電柱和/或針。該導電柱和/或針可以在加注密封材料之前或之後形成。例如,如果在加注密封材料之後形成,要在密封材料上打孔,再將金屬或其他導電材料(液態、氣態或固態形式)插入孔中,以形成導電柱和/或針。另外,除焊球以外,互連構件還可以是由其他金屬材料(如銅、鋁、金、鎳、錫、銀或金屬混合物/合金)製成的球狀體。
此外,在一個實施例中,球體的內核可由第一種材料製成,而外殼由第二種材料製成。例如,內核-外殼結構的球體可以是銅質內核,外殼由焊料製成。在一個實施例中,互連構件是在一種內核材料外面覆蓋鍵合(bonding)材料,諸如可將熱互連構件與接觸焊盤機械鍵合到一起的焊料、金、銀、環氧、或其他連接材料。
在實施例中,互連構件透過密封材料伸出。在一個實施例中,互連構件是被切去頂端的。例如,密封材料的上面一層(或上面一層的一部分)被從下IC封裝體上移除,此過程中互連構件的頂部也被切除。用這種方式,互連構件得以外露,在封裝體的外表面形成相對一致的互連接觸焊盤的陣列。這些互連接觸焊盤可用於與第二IC封裝體進行互連。在一個實施例中,多個互連構件安裝在IC晶粒的上表面。在另一實施例中,多個互連構件安裝在封裝體基片的上表面。
以下將詳細描述本發明的示例性實施例。
圖5A-5D示出了根據本發明實施例的IC封裝體示意圖。圖5A為FBGA封裝體500切掉一部分後的透視圖。在封裝體500中,IC晶粒102由多個焊線114電連接到基片110上表面的導電體(例如迹線(trace)、鍵合手指等)。基片110上表面的導電體通過基片110(例如通過一個或多個導電和/或非導電層)電耦合到基片110下表面的焊球焊盤(solder ball pads)上。此外,基片110的上和/或下表面可能部分地被非導電材料(如防焊材料)覆蓋,以防止上和/或下表面的所選擇導電物發生短路等。基片110上表面與焊線114連接的導電體未被非導電材料覆蓋。焊球108與焊球焊盤相連接,且與電路板(如印刷電路板(PBC)或印刷線路板,圖5A-5D中未示出)相連。
如圖5A所示,晶粒102的上表面具有多個接觸焊盤502。圖5B為FBGA封裝體500切掉一部分後的透視圖,可見互連構件508。在圖5B中,互連構件508貼裝在相應的接觸焊盤502上。在一個實施例中,晶粒102可能有任意數量的接觸焊盤502,每一個都用於連接一個互連構件508。接觸焊盤502電連接於晶粒102的電信號,包括輸入/輸出信號、電源信號、接地信號等。密封材料512將封裝體500密封起來。在圖5B-5D所示的實施例中,互連構件508完全被密封材料512覆蓋。密封材料512可以是用於IC封裝的任意類型的密封材料,如本文中其他部分所描述或已知的密封材料包括環氧、塑封混合物等。
圖5C和5D分別示出了FBGA封裝體550切掉一部分後的透視圖和FBGA封裝體550的透視圖。除了密封材料512未將互連構件508的上表面504密封住之外,封裝體550與封裝體500相似。在一個實施例中,密封材料512的上面一層被移除以使互連構件508的上表面504外露。在該實施例中,互連構件508的頂部被切掉,以形成平坦外露的互連構件508表面504,並且表面504與密封材料512的上表面平齊。表面504也可稱為“電接觸焊盤”或“互連接觸焊盤”。封裝體550的外露表面504可使封裝體550外的器件電連接(例如信號、接地或電源)到晶粒102。有各種方法可將嵌在封裝體密封材料內的球狀體截去頂部(truncate),包括下面將討論的方法。圖5D示出了完整封裝體550的外觀圖。在密封材料512的外表面可見互連接觸焊盤504。
在一個實施例中,封裝體550的外露表面504可用于封裝體-封裝體的電互連,以形成堆疊的IC封裝。包括IC封裝體、電感、電容、電阻、三極管、二極體等在內的許多電子元器件都能夠通過表面(接觸焊盤)504電連接到封裝體550。
在一個實施例中,互連構件508被截去頂部。可使用各種工藝在移除一層密封材料512的同時截去互連構件508的頂部,諸如打磨(grinding)、刳刨(routing)、其他表面加工方法和化學刻蝕工藝。
圖6A-6C是根據本發明實施例的IC封裝體。圖6A所示的封裝體600中,互連構件508貼裝在晶粒102的上表面。密封材料512將基片110的上表面、晶粒102和焊線114密封住。此外,互連構件508被密封材料512完全密封。圖6B示出了封裝體650,其中密封材料512的頂層被移除,且互連構件508的頂部也被截掉。從而在密封材料512的上表面形成表面(互連接觸焊盤)504。
圖6C示出了封裝體660,其中密封材料512的上面一層662只被部分移除,在密封材料512中形成了一個凹腔(cavity)664。在封裝體660中,凹腔664在密封材料512的上表面的中部形成,在密封材料512中互連構件508的頂部所處的區域。由於凹腔664的形成,互連構件508被截去頂部(頂部被移除)。互連構件508的頂部被截掉使得在凹腔664內,密封材料512的表面上形成表面(互連接觸焊盤)504。
在另一實施例中,密封材料512中,在互連構件508上面可以形成任意數量的凹腔664,以使表面504外露。
圖6D示出了根據本發明實施例的封裝體670。在封裝體670中,多個互連構件508安裝到基片110上表面602的導電體604(例如接觸焊盤、鍵合手指、迹線等)上。互連構件508被截去頂部(頂部被移除)。互連構件508的頂部被截掉使得密封材料512的表面上形成表面(互連接觸焊盤)504。在一種配置中,互連構件508可在基片110上表面602上佈置成一定的形狀,包括規則陣列、在上表面602的晶粒102周圍形成一圈或多圈互連構件508,或互連構件508的任意不規則配置,也就是說上表面602上可按需要佈置任意數量的互連構件508。例如,如圖6所示,上表面602上晶粒102的左側有一個互連構件508,而右側有兩個互連構件508。
圖7A-7D所示為堆疊式FBGA封裝的實施例。圖7A所示的堆疊式IC封裝體700包括安裝在第一IC封裝體740上的第二封裝體730。第二封裝體730的結構與圖3B所示的封裝體300相似。第一封裝體740的結構與圖6B所示的封裝體650相似。第二封裝體730基片110下表面上的焊球108,在第一封裝體740密封材料112上表面702處,與多個互連構件508電連接。具體地說,焊球108貼裝在互連構件508的表面504上。
在圖7A所示的實施例中,第二封裝體730上的每一個焊球108都連接到第一封裝體740上相應的互連構件508上。如圖7B-7C所示,在實施例中,第二封裝體730上的焊球108無需全部與互連構件508電連接。例如,在圖7B中,焊球708未與互連構件508電連接,而焊球108與互連構件508電連接。在圖7B中,焊球708是第二封裝體730下表面704的焊球陣列中週邊的焊球。焊球108是第二封裝體730下表面704的焊球陣列中內部的焊球。例如,焊球708可圍成環繞焊球108的一圈或多圈焊球。圖7C中,第二封裝體730下表面704的焊球708和焊球108之間有一個沒安裝焊球的環形間隔區706(即少一圈或多圈焊球)。
在一個實施例中,焊球708能夠接入第二封裝體730晶粒102的測試信號,以對第二封裝體730進行測試。在另一實施例中,焊球708通過與第一封裝體740的密封材料512上表面702相接觸,在第二封裝體730的週邊區域為位於第一封裝體740上面的第二封裝體730提供機械支撐。在又一實施例中,焊球708的設置沒有特殊目的或組合目的。
如上所述,在實施例中,第一和第二封裝體740和730可以是相同尺寸和/或結構,也可以是不同尺寸和/或結構。例如,圖7D所示的實施例中,第二封裝體730的尺寸小於第一封裝體740的尺寸(例如,第二封裝體730基片110的面積小於第一封裝體740基片的面積)。在一個實施例中,第二封裝體730的基片110寬度(和/或面積)等於或小於第一封裝體740晶粒102的寬度(和/或面積)。
如本文中所描述,在一實施例中,密封材料512中有一凹腔664。例如,圖8A-8B示出堆疊式IC封裝體800的實施例,包括安裝在第一FBGA封裝體840上的第二FBGA封裝體830。圖8A中,第一封裝體840的密封材料512中有一凹腔664。互連構件508具有露出凹腔664底面802的表面504。第二封裝體830下表面704上的焊球108在表面504處與互連構件508電連接。
在圖8B所示的實施例中,第二封裝體830完全位於凹腔664內。在另一實施例中,如圖8A所示,第二封裝體830只有焊球部分或全部位於凹腔664內。第二封裝體830的任意部分可以部分或全部位於凹腔664內。
此外,圖8B所示的實施例中,第一封裝體840的晶粒102的尺寸比凹腔664大。這種尺寸配合使第二封裝體830與第一封裝體840的晶粒102靠的很近,允許採用很短的互連構件508,因而信號路徑短,同時使得第一封裝體840的焊線114保持在密封材料512中以得到保護。另一個好處在於堆疊式封裝體850的總體高度可以降低。
互連構件508不限於將第一IC封裝體的晶粒電連接到第二IC封裝體基片的下表面。例如,圖9A所示的堆疊式IC封裝體900中,第二封裝體930安裝在第一封裝體940上面。第一封裝體940與圖6D所示的封裝體670相似。在堆疊式IC封裝體900中,第一組互連構件508連接在第一封裝體940的晶粒102與第二封裝體930的焊球108之間,第二組互連構件508電連接在第一封裝體940基片110上表面902與第二封裝體930的焊球108之間。這樣,如圖9A所示,互連構件508可安裝在基片110上表面902的導電體904(例如接觸焊盤、鍵合手指、迹線等)上,以透過密封材料512連接至第二封裝體930的焊球108。
圖9B是根據本發明一實施例的堆疊式IC封裝體950的示意圖。封裝體950包括安裝在第一封裝體970上的第二封裝體960。除了第一封裝體970的晶粒102與第二封裝體960的焊球108之間沒有互連構件外,第一封裝體970與圖9A中的封裝體940相似,第二封裝體960與圖9A中的第二封裝體930相似。圖9B中,互連構件508安裝在基片110上表面902的導電體904(例如接觸焊盤、鍵合手指、迹線等)上,以透過密封材料512連接至第二封裝體960的焊球108。
上述實施例不限於FBGA封裝或類似的IC封裝。本領域的技術人員應當知曉,本發明的實施例可以應用到當前或將來的許多IC封裝結構中或結構組合中。
圖10、11A-11H所示為製造堆疊式IC封裝的相關實施例。雖然圖11A-11H所示的IC封裝是BGA封裝,此處所描述的製造工藝示例也可應用於當前或將來的其他IC封裝結構和技術。
圖10示出了堆疊式IC封裝製造工藝的流程圖1000。流程圖1000結合圖11A-11H進行描述,圖11A-11H中示出了各裝配階段的FBGA封裝體的示意圖。流程圖1000從步驟1002-1012,形成帶有多個互連接觸焊盤的第一IC封裝體。步驟1014將第二IC封裝體堆疊到第一IC封裝體上,形成堆疊式IC封裝體。需要注意的是,流程圖1000的步驟不一定非得按照圖中所示的順序進行。以下對流程圖1000進行詳細描述。
在步驟1002中,將晶粒安裝到基片上。例如,使用晶粒粘合材料106將晶粒102貼裝到基片110上,如圖11A所示。例如,晶粒粘合材料106可以是傳統的晶粒粘合材料,如環氧和/或薄膜粘膠。
在步驟1004中,將一個或多個封裝體互連構件安裝到IC晶粒的上表面。例如,如圖11B所示,多個互連構件508被安裝到晶粒102上。在一個實施例中,互連構件508被安裝到IC晶粒上表面的接觸焊盤502上,如圖5A所示。在另一實施例中,互連構件508也可連接到基片110的上表面902,如圖9A和9B所示。
在步驟1006,用焊線將IC晶粒與基片連接起來。例如,如圖11C所示,通過焊線鍵合工藝用焊線114將IC晶粒102連接到基片110。
在步驟1008,加注密封材料。例如,如圖11D所示,密封材料512被加注到基片110的上表面902,以將晶粒102、焊線114和互連構件508密封起來。
在步驟1010中,至少將密封材料512的上面一層移除一部分。在一個實施例中,互連構件508被截去頂部,其中互連構件508的頂部與密封材料512上面一層中的部分或全部一起移除。步驟1010a和1010b為實施步驟1010的兩個示例性選擇方式。例如,在可選步驟1010a中,移除完整一層密封材料512。如圖11E所示,採用打磨工具1102將密封材料512上面一層打磨掉,以截去並外露互連構件508的頂部。在可選步驟1010b中,在密封材料512中形成一個凹腔。例如,如圖11F所示,採用刳刨(routing)工具1104在密封材料512的上面一層662中刳刨出一凹腔664,以截去並外露互連構件508的頂部。在步驟1010中,也可以採用其他的材料移除方法,諸如化學、機械或鐳射加工方法,以移除部分密封材料512從而截去並外露互連構件508的頂部。作為另一選擇,也可以採用模塑方法在密封材料512中形成凹腔664,如在向基片110上加注密封材料512時形成。
在步驟1012中,將焊球安裝到基片下表面。例如,如圖11G所示,焊球108在基片110下表面1110上形成。焊球可採用傳統的球安裝方法進行安裝。圖11G示出了第一封裝1180,其是通過步驟1002-1012產生的。
在步驟1014中,將第二IC封裝體安裝到上述所形成的第一封裝體上。例如,如圖11H所示,第二IC封裝體1130安裝在第一IC封裝體1180上。第二IC封裝體1130下表面704的焊球108貼裝到互連構件508上,如通過回流焊、導電粘膠和/或其他方式。
在另一實施例中,第二IC封裝體1130上面安裝有互連構件508,且另一個IC封裝體可安裝到第二IC封裝體上。這一過程可以重復進行,以堆疊成所期望層數的多層封裝體。
如上所述,流程圖1000中的步驟可以不同的順序進行。例如在另一實施例中,焊線鍵合工序(例如步驟1006)可以在將互連構件貼裝到晶粒上(例如步驟1004)之前進行。再有,例如將焊球安裝到第一封裝體這一步驟(例如步驟1012)可以在將第二封裝體安裝到第一封裝體(例如步驟1014)進行。本領域技術人員從本發明的教導中可知,流程圖1000的步驟可以各種方式改變。
對於上述實施例,焊球只是作為封裝互連構件的一個實例。也可以採用其他導電材料或結構在塑封頂部(mold top)形成封裝體-封裝體的互連接觸結構,這是通過穿過密封材料延伸區域陣列封裝體(area array package,如BGA、LGA、PGA等)基片頂部的電接觸件來實現的,在塑封上表面(mold top surface)露出電接觸端子。例如可將金屬導電柱貼裝在基片上面的接觸焊盤上並露出塑封頂部表面。
本發明是通過一些實施例進行描述的,應當理解,其目的僅在於舉例說明,而沒有限制性。本領域的技術人員知悉,在不脫離本發明的精神和範圍情況下,在形式上和細節上還可做各種改變。因此,本發明的保護範圍不應當僅局限於以上描述的任一實施例,而應該依照權利要求及其等同來限定。
晶粒朝上塑膠球柵陣列封裝(PBGA)封裝體...100
積體電路(IC)晶粒...102
晶粒粘合材料...106
焊球...108
基片...110
塑膠塑封材料...112
焊線...114
精細間距球柵陣列(FBGA)封裝體...300
導電跡線(trace)...310
堆疊式IC封裝體...400
積體電路(IC)晶粒...406
基片...410
平面焊盤...420
上BGA封裝體...430
下BGA封裝體...440
堆疊式封裝體...450
上BGA封裝體...480
下BGA封裝體...490
精細間距球柵陣列(FBGA)封裝體...500
接觸焊盤...502
上表面...504
互連構件...508
密封材料...512
精細間距球柵陣列(FBGA)封裝體...550
封裝體...600
表面...602
導電體...604
封裝體...650
封裝體...660
上面一層...662
凹腔(cavity)...664
封裝體...670
堆疊式IC封裝體...700
上表面...702
下表面...704
環形間隔區...706
焊球...708
第二封裝體...730
第一IC封裝體...740
堆疊式IC封裝體...800
底面...802
第二FBGA封裝體...830
第一FBGA封裝體...840
堆疊式封裝體...850
堆疊式IC封裝體...900
上表面...902
導電體...904
第二封裝體...930
第一封裝體...940
堆疊式IC封裝體...950
第二封裝體...960
第一封裝體...970
打磨工具...1102
刳刨(routing)工具...1104
下表面...1110
第二IC封裝體...1130
第一IC封裝體...1180
圖1所示為傳統塑膠球柵陣列(PBGA)封裝的示意圖;圖2A和2B分別是圖1所示PBGAIC封裝的俯視圖和側視圖;圖3A和3B分別是傳統密間距球柵陣列(FBGA)IC封裝的剖面圖和截面圖;圖4A和4B為傳統PoP(Package on Package)堆疊式IC器件的截面圖;圖5A-5D是根據本發明實施例的帶有互連構件的FBGA IC封裝體的示意圖;圖6A-6D是根據本發明實施例的帶有互連構件的FBGA IC封裝體的截面示意圖;圖7A-7D是根據本發明實施例的PoP堆疊式IC封裝體的截面示意圖;圖8A和8B是根據本發明實施例的PoP堆疊式IC封裝體的截面示意圖;圖9A和9B是根據本發明實施例的PoP堆疊式IC封裝體的截面示意圖;圖10是根據本發明實施例製造IC封裝體流程的示意圖;圖11A-11H根據本發明實施例,在各個製造階段的IC封裝體的示意圖。
焊球...108
上表面...504
互連構件...508
密封材料...512
堆疊式IC封裝體...800
第二FBGA封裝體...830
第一FBGA封裝體...840
Claims (2)
- 一種堆疊式IC封裝器件,其特徵在於,包括第一IC封裝體,其包括:帶有多個接觸焊盤的IC晶粒;連接於所述多個接觸焊盤的多個互連構件;密封所述IC晶粒和互連構件的密封材料,其使得每個互連構件的接觸面在密封材料的表面均可觸及(accessible);及通過第一IC封裝體的多個互連構件連接到所述第一IC封裝體的第二IC封裝體;其中,所述密封材料的表面有一凹腔,在所述凹腔內每個互連構件的接觸表面均可觸及(accessible);所述第二IC封裝體完全佈置在所述凹腔內,所述第二IC封裝體的高度小於或者等於所述凹腔的深度。
- 一種製造堆疊式IC封裝器件的方法,其特徵在於,包括:(a)製造第一封裝體,包括:(I)將IC晶粒貼裝在基片的第一表面上,所述晶粒帶有多個接觸焊盤;(2)將多個互連構件連接至所述多個接觸焊盤;(3)使用至少一條焊線將晶粒連接到基片上; (4)將晶粒和互連構件密封在密封材料中;(5)在密封材料中形成一凹腔,至少部分裸露出多個互連構件以使在所述凹腔內每個互連構件的接觸面在密封材料的表面均可觸及(accessible);(b)通過第一IC封裝體的多個互連構件將第二IC封裝體連接至第一IC封裝體上,所述第二IC封裝體完全佈置在所述凹腔內,所述第二IC封裝體的高度小於或者等於所述凹腔的深度。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US81487506P | 2006-06-20 | 2006-06-20 | |
US11/589,120 US8581381B2 (en) | 2006-06-20 | 2006-10-30 | Integrated circuit (IC) package stacking and IC packages formed by same |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200818455A TW200818455A (en) | 2008-04-16 |
TWI455281B true TWI455281B (zh) | 2014-10-01 |
Family
ID=37667357
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096122032A TWI455281B (zh) | 2006-06-20 | 2007-06-20 | Ic封裝體、堆疊式ic封裝器件及製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8581381B2 (zh) |
EP (1) | EP1870932B1 (zh) |
KR (1) | KR100884172B1 (zh) |
CN (1) | CN101127344B (zh) |
TW (1) | TWI455281B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11362057B2 (en) | 2019-10-22 | 2022-06-14 | Unimicron Technology Corp. | Chip package structure and manufacturing method thereof |
Families Citing this family (177)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6930256B1 (en) | 2002-05-01 | 2005-08-16 | Amkor Technology, Inc. | Integrated circuit substrate having laser-embedded conductive patterns and method therefor |
US7548430B1 (en) | 2002-05-01 | 2009-06-16 | Amkor Technology, Inc. | Buildup dielectric and metallization process and semiconductor package |
US9691635B1 (en) | 2002-05-01 | 2017-06-27 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
US7670962B2 (en) * | 2002-05-01 | 2010-03-02 | Amkor Technology, Inc. | Substrate having stiffener fabrication method |
US7633765B1 (en) | 2004-03-23 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package including a top-surface metal layer for implementing circuit features |
US7723210B2 (en) * | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US11081370B2 (en) | 2004-03-23 | 2021-08-03 | Amkor Technology Singapore Holding Pte. Ltd. | Methods of manufacturing an encapsulated semiconductor device |
US10811277B2 (en) | 2004-03-23 | 2020-10-20 | Amkor Technology, Inc. | Encapsulated semiconductor package |
JP2005317861A (ja) * | 2004-04-30 | 2005-11-10 | Toshiba Corp | 半導体装置およびその製造方法 |
US7271479B2 (en) * | 2004-11-03 | 2007-09-18 | Broadcom Corporation | Flip chip package including a non-planar heat spreader and method of making the same |
US8826531B1 (en) | 2005-04-05 | 2014-09-09 | Amkor Technology, Inc. | Method for making an integrated circuit substrate having laminated laser-embedded circuit layers |
US7582951B2 (en) | 2005-10-20 | 2009-09-01 | Broadcom Corporation | Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US7714453B2 (en) | 2006-05-12 | 2010-05-11 | Broadcom Corporation | Interconnect structure and formation for package stacking of molded plastic area array package |
US8183680B2 (en) | 2006-05-16 | 2012-05-22 | Broadcom Corporation | No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement |
US9299634B2 (en) * | 2006-05-16 | 2016-03-29 | Broadcom Corporation | Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US20070273023A1 (en) * | 2006-05-26 | 2007-11-29 | Broadcom Corporation | Integrated circuit package having exposed thermally conducting body |
US7808087B2 (en) | 2006-06-01 | 2010-10-05 | Broadcom Corporation | Leadframe IC packages having top and bottom integrated heat spreaders |
US9013035B2 (en) * | 2006-06-20 | 2015-04-21 | Broadcom Corporation | Thermal improvement for hotspots on dies in integrated circuit packages |
US8581381B2 (en) | 2006-06-20 | 2013-11-12 | Broadcom Corporation | Integrated circuit (IC) package stacking and IC packages formed by same |
US7755164B1 (en) | 2006-06-21 | 2010-07-13 | Amkor Technology, Inc. | Capacitor and resistor having anodic metal and anodic metal oxide structure |
TWI336502B (en) * | 2006-09-27 | 2011-01-21 | Advanced Semiconductor Eng | Semiconductor package and semiconductor device and the method of making the same |
US7589398B1 (en) | 2006-10-04 | 2009-09-15 | Amkor Technology, Inc. | Embedded metal features structure |
US8169067B2 (en) * | 2006-10-20 | 2012-05-01 | Broadcom Corporation | Low profile ball grid array (BGA) package with exposed die and method of making same |
US7898093B1 (en) | 2006-11-02 | 2011-03-01 | Amkor Technology, Inc. | Exposed die overmolded flip chip package and fabrication method |
US7550857B1 (en) | 2006-11-16 | 2009-06-23 | Amkor Technology, Inc. | Stacked redistribution layer (RDL) die assembly package |
US20080128890A1 (en) * | 2006-11-30 | 2008-06-05 | Advanced Semiconductor Engineering, Inc. | Chip package and fabricating process thereof |
US7750250B1 (en) | 2006-12-22 | 2010-07-06 | Amkor Technology, Inc. | Blind via capture pad structure |
US7752752B1 (en) | 2007-01-09 | 2010-07-13 | Amkor Technology, Inc. | Method of fabricating an embedded circuit pattern |
US7656031B2 (en) * | 2007-02-05 | 2010-02-02 | Bridge Semiconductor Corporation | Stackable semiconductor package having metal pin within through hole of package |
US8183687B2 (en) | 2007-02-16 | 2012-05-22 | Broadcom Corporation | Interposer for die stacking in semiconductor packages and the method of making the same |
TWI335070B (en) * | 2007-03-23 | 2010-12-21 | Advanced Semiconductor Eng | Semiconductor package and the method of making the same |
US7872335B2 (en) * | 2007-06-08 | 2011-01-18 | Broadcom Corporation | Lead frame-BGA package with enhanced thermal performance and I/O counts |
US7923645B1 (en) | 2007-06-20 | 2011-04-12 | Amkor Technology, Inc. | Metal etch stop fabrication method and structure |
US7951697B1 (en) | 2007-06-20 | 2011-05-31 | Amkor Technology, Inc. | Embedded die metal etch stop fabrication method and structure |
US8323771B1 (en) | 2007-08-15 | 2012-12-04 | Amkor Technology, Inc. | Straight conductor blind via capture pad structure and fabrication method |
US7777351B1 (en) * | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US7632753B1 (en) | 2007-10-04 | 2009-12-15 | Amkor Technology, Inc. | Wafer level package utilizing laser-activated dielectric material |
US7958626B1 (en) | 2007-10-25 | 2011-06-14 | Amkor Technology, Inc. | Embedded passive component network substrate fabrication method |
JP5081578B2 (ja) * | 2007-10-25 | 2012-11-28 | ローム株式会社 | 樹脂封止型半導体装置 |
US8017436B1 (en) | 2007-12-10 | 2011-09-13 | Amkor Technology, Inc. | Thin substrate fabrication method and structure |
SG153762A1 (en) * | 2007-12-12 | 2009-07-29 | United Test & Assembly Ct Ltd | Package-on-package semiconductor structure |
US7832097B1 (en) | 2008-01-23 | 2010-11-16 | Amkor Technology, Inc. | Shielded trace structure and fabrication method |
US7932170B1 (en) | 2008-06-23 | 2011-04-26 | Amkor Technology, Inc. | Flip chip bump structure and fabrication method |
TWI473553B (zh) | 2008-07-03 | 2015-02-11 | Advanced Semiconductor Eng | 晶片封裝結構 |
US8270176B2 (en) | 2008-08-08 | 2012-09-18 | Stats Chippac Ltd. | Exposed interconnect for a package on package system |
US7901988B2 (en) * | 2008-08-08 | 2011-03-08 | Eems Asia Pte Ltd | Method for forming a package-on-package structure |
US7989950B2 (en) * | 2008-08-14 | 2011-08-02 | Stats Chippac Ltd. | Integrated circuit packaging system having a cavity |
US8823160B2 (en) * | 2008-08-22 | 2014-09-02 | Stats Chippac Ltd. | Integrated circuit package system having cavity |
US7842541B1 (en) | 2008-09-24 | 2010-11-30 | Amkor Technology, Inc. | Ultra thin package and fabrication method |
JP5543094B2 (ja) * | 2008-10-10 | 2014-07-09 | ピーエスフォー ルクスコ エスエイアールエル | 低ノイズ半導体パッケージ |
US8472199B2 (en) * | 2008-11-13 | 2013-06-25 | Mosaid Technologies Incorporated | System including a plurality of encapsulated semiconductor chips |
US8022538B2 (en) * | 2008-11-17 | 2011-09-20 | Stats Chippac Ltd. | Base package system for integrated circuit package stacking and method of manufacture thereof |
US8183677B2 (en) * | 2008-11-26 | 2012-05-22 | Infineon Technologies Ag | Device including a semiconductor chip |
US8176628B1 (en) | 2008-12-23 | 2012-05-15 | Amkor Technology, Inc. | Protruding post substrate package structure and method |
US8012797B2 (en) * | 2009-01-07 | 2011-09-06 | Advanced Semiconductor Engineering, Inc. | Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries |
TWI499024B (zh) * | 2009-01-07 | 2015-09-01 | Advanced Semiconductor Eng | 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法 |
US20100171206A1 (en) * | 2009-01-07 | 2010-07-08 | Chi-Chih Chu | Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same |
US8872329B1 (en) | 2009-01-09 | 2014-10-28 | Amkor Technology, Inc. | Extended landing pad substrate package structure and method |
US7960827B1 (en) | 2009-04-09 | 2011-06-14 | Amkor Technology, Inc. | Thermal via heat spreader package and method |
US8623753B1 (en) | 2009-05-28 | 2014-01-07 | Amkor Technology, Inc. | Stackable protruding via package and method |
US9355962B2 (en) * | 2009-06-12 | 2016-05-31 | Stats Chippac Ltd. | Integrated circuit package stacking system with redistribution and method of manufacture thereof |
US8222538B1 (en) | 2009-06-12 | 2012-07-17 | Amkor Technology, Inc. | Stackable via package and method |
US8471154B1 (en) | 2009-08-06 | 2013-06-25 | Amkor Technology, Inc. | Stackable variable height via package and method |
US8169058B2 (en) * | 2009-08-21 | 2012-05-01 | Stats Chippac, Ltd. | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars |
USRE48111E1 (en) | 2009-08-21 | 2020-07-21 | JCET Semiconductor (Shaoxing) Co. Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US8383457B2 (en) | 2010-09-03 | 2013-02-26 | Stats Chippac, Ltd. | Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect |
US8222722B2 (en) * | 2009-09-11 | 2012-07-17 | St-Ericsson Sa | Integrated circuit package and device |
US8035235B2 (en) * | 2009-09-15 | 2011-10-11 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
US8749040B2 (en) * | 2009-09-21 | 2014-06-10 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
KR101624973B1 (ko) | 2009-09-23 | 2016-05-30 | 삼성전자주식회사 | 패키지 온 패키지 타입의 반도체 패키지 및 그 제조방법 |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
KR20110044077A (ko) * | 2009-10-22 | 2011-04-28 | 삼성전자주식회사 | 반도체 패키지 구조물 |
US8198131B2 (en) | 2009-11-18 | 2012-06-12 | Advanced Semiconductor Engineering, Inc. | Stackable semiconductor device packages |
TWI392069B (zh) * | 2009-11-24 | 2013-04-01 | Advanced Semiconductor Eng | 封裝結構及其封裝製程 |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8508954B2 (en) * | 2009-12-17 | 2013-08-13 | Samsung Electronics Co., Ltd. | Systems employing a stacked semiconductor package |
KR20110076604A (ko) * | 2009-12-29 | 2011-07-06 | 하나 마이크론(주) | Pop 패키지 및 그 제조 방법 |
TWI408785B (zh) | 2009-12-31 | 2013-09-11 | Advanced Semiconductor Eng | 半導體封裝結構 |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8536462B1 (en) | 2010-01-22 | 2013-09-17 | Amkor Technology, Inc. | Flex circuit package and method |
TWI419283B (zh) | 2010-02-10 | 2013-12-11 | Advanced Semiconductor Eng | 封裝結構 |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
KR101078743B1 (ko) * | 2010-04-14 | 2011-11-02 | 주식회사 하이닉스반도체 | 스택 패키지 |
US8300423B1 (en) | 2010-05-25 | 2012-10-30 | Amkor Technology, Inc. | Stackable treated via package and method |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US9484279B2 (en) | 2010-06-02 | 2016-11-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die |
US8338229B1 (en) | 2010-07-30 | 2012-12-25 | Amkor Technology, Inc. | Stackable plasma cleaned via package and method |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8717775B1 (en) | 2010-08-02 | 2014-05-06 | Amkor Technology, Inc. | Fingerprint sensor package and method |
TWI426587B (zh) * | 2010-08-12 | 2014-02-11 | 矽品精密工業股份有限公司 | 晶片尺寸封裝件及其製法 |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
CN102446907A (zh) * | 2010-10-13 | 2012-05-09 | 环旭电子股份有限公司 | 立体封装结构及其制作方法 |
US8337657B1 (en) | 2010-10-27 | 2012-12-25 | Amkor Technology, Inc. | Mechanical tape separation package and method |
TWI451546B (zh) | 2010-10-29 | 2014-09-01 | Advanced Semiconductor Eng | 堆疊式封裝結構、其封裝結構及封裝結構之製造方法 |
US8482134B1 (en) | 2010-11-01 | 2013-07-09 | Amkor Technology, Inc. | Stackable package and method |
US9748154B1 (en) | 2010-11-04 | 2017-08-29 | Amkor Technology, Inc. | Wafer level fan out semiconductor device and manufacturing method thereof |
US8525318B1 (en) | 2010-11-10 | 2013-09-03 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8557629B1 (en) | 2010-12-03 | 2013-10-15 | Amkor Technology, Inc. | Semiconductor device having overlapped via apertures |
US8535961B1 (en) | 2010-12-09 | 2013-09-17 | Amkor Technology, Inc. | Light emitting diode (LED) package and method |
US8502387B2 (en) * | 2010-12-09 | 2013-08-06 | Stats Chippac Ltd. | Integrated circuit packaging system with vertical interconnection and method of manufacture thereof |
US9059160B1 (en) * | 2010-12-23 | 2015-06-16 | Marvell International Ltd. | Semiconductor package assembly |
TWI445155B (zh) | 2011-01-06 | 2014-07-11 | Advanced Semiconductor Eng | 堆疊式封裝結構及其製造方法 |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US9721872B1 (en) | 2011-02-18 | 2017-08-01 | Amkor Technology, Inc. | Methods and structures for increasing the allowable die size in TMV packages |
US9171792B2 (en) | 2011-02-28 | 2015-10-27 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages having a side-by-side device arrangement and stacking functionality |
US9064781B2 (en) | 2011-03-03 | 2015-06-23 | Broadcom Corporation | Package 3D interconnection and method of making same |
US8508045B2 (en) | 2011-03-03 | 2013-08-13 | Broadcom Corporation | Package 3D interconnection and method of making same |
US9013011B1 (en) | 2011-03-11 | 2015-04-21 | Amkor Technology, Inc. | Stacked and staggered die MEMS package and method |
KR101140113B1 (ko) | 2011-04-26 | 2012-04-30 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 |
US8389329B2 (en) | 2011-05-31 | 2013-03-05 | Stats Chippac Ltd. | Integrated circuit packaging system with package stacking and method of manufacture thereof |
US8530277B2 (en) | 2011-06-16 | 2013-09-10 | Stats Chippac Ltd. | Integrated circuit packaging system with package on package support and method of manufacture thereof |
US9209163B2 (en) * | 2011-08-19 | 2015-12-08 | Marvell World Trade Ltd. | Package-on-package structures |
US8748231B2 (en) * | 2011-08-23 | 2014-06-10 | Amphenol Thermometrics, Inc. | Component assembly using a temporary attach material |
US8653674B1 (en) | 2011-09-15 | 2014-02-18 | Amkor Technology, Inc. | Electronic component package fabrication method and structure |
US8633598B1 (en) | 2011-09-20 | 2014-01-21 | Amkor Technology, Inc. | Underfill contacting stacking balls package fabrication method and structure |
US8718550B2 (en) | 2011-09-28 | 2014-05-06 | Broadcom Corporation | Interposer package structure for wireless communication element, thermal enhancement, and EMI shielding |
US9029962B1 (en) | 2011-10-12 | 2015-05-12 | Amkor Technology, Inc. | Molded cavity substrate MEMS package fabrication method and structure |
US8922013B2 (en) * | 2011-11-08 | 2014-12-30 | Stmicroelectronics Pte Ltd. | Through via package |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US20130154106A1 (en) | 2011-12-14 | 2013-06-20 | Broadcom Corporation | Stacked Packaging Using Reconstituted Wafers |
US9576873B2 (en) * | 2011-12-14 | 2017-02-21 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with routable trace and method of manufacture thereof |
US8994192B2 (en) * | 2011-12-15 | 2015-03-31 | Stats Chippac Ltd. | Integrated circuit packaging system with perimeter antiwarpage structure and method of manufacture thereof |
WO2013095546A1 (en) * | 2011-12-22 | 2013-06-27 | Intel Corporation | 3d integrated circuit package with through-mold first level interconnects |
US9548251B2 (en) | 2012-01-12 | 2017-01-17 | Broadcom Corporation | Semiconductor interposer having a cavity for intra-interposer die |
US20130187284A1 (en) | 2012-01-24 | 2013-07-25 | Broadcom Corporation | Low Cost and High Performance Flip Chip Package |
KR20130089473A (ko) * | 2012-02-02 | 2013-08-12 | 삼성전자주식회사 | 반도체 패키지 |
US8587132B2 (en) | 2012-02-21 | 2013-11-19 | Broadcom Corporation | Semiconductor package including an organic substrate and interposer having through-semiconductor vias |
US8558395B2 (en) | 2012-02-21 | 2013-10-15 | Broadcom Corporation | Organic interface substrate having interposer with through-semiconductor vias |
US9275976B2 (en) | 2012-02-24 | 2016-03-01 | Broadcom Corporation | System-in-package with integrated socket |
US8872321B2 (en) | 2012-02-24 | 2014-10-28 | Broadcom Corporation | Semiconductor packages with integrated heat spreaders |
US8749072B2 (en) | 2012-02-24 | 2014-06-10 | Broadcom Corporation | Semiconductor package with integrated selectively conductive film interposer |
US8928128B2 (en) | 2012-02-27 | 2015-01-06 | Broadcom Corporation | Semiconductor package with integrated electromagnetic shielding |
KR20130105175A (ko) * | 2012-03-16 | 2013-09-25 | 삼성전자주식회사 | 보호 층을 갖는 반도체 패키지 및 그 형성 방법 |
US9082780B2 (en) * | 2012-03-23 | 2015-07-14 | Stats Chippac, Ltd. | Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
KR101947722B1 (ko) * | 2012-06-07 | 2019-04-25 | 삼성전자주식회사 | 적층 반도체 패키지 및 이의 제조방법 |
US8889486B2 (en) | 2012-09-05 | 2014-11-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for package on package structures |
US8963311B2 (en) * | 2012-09-26 | 2015-02-24 | Apple Inc. | PoP structure with electrically insulating material between packages |
KR101419597B1 (ko) * | 2012-11-06 | 2014-07-14 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US9799592B2 (en) | 2013-11-19 | 2017-10-24 | Amkor Technology, Inc. | Semicondutor device with through-silicon via-less deep wells |
KR101366461B1 (ko) | 2012-11-20 | 2014-02-26 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
KR101488590B1 (ko) | 2013-03-29 | 2015-01-30 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
TWI533421B (zh) | 2013-06-14 | 2016-05-11 | 日月光半導體製造股份有限公司 | 半導體封裝結構及半導體製程 |
US9659891B2 (en) * | 2013-09-09 | 2017-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a boundary structure, a package on package structure, and a method of making |
KR101607981B1 (ko) | 2013-11-04 | 2016-03-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지 |
FR3018630A1 (fr) * | 2014-03-11 | 2015-09-18 | St Microelectronics Grenoble 2 | Boitier electronique perfore et procede de fabrication |
US10032704B2 (en) * | 2015-02-13 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing cracking by adjusting opening size in pop packages |
US10236123B2 (en) | 2015-07-19 | 2019-03-19 | Vq Research, Inc. | Methods and systems to minimize delamination of multilayer ceramic capacitors |
US10431508B2 (en) | 2015-07-19 | 2019-10-01 | Vq Research, Inc. | Methods and systems to improve printed electrical components and for integration in circuits |
US10128047B2 (en) | 2015-07-19 | 2018-11-13 | Vq Research, Inc. | Methods and systems for increasing surface area of multilayer ceramic capacitors |
US10332684B2 (en) | 2015-07-19 | 2019-06-25 | Vq Research, Inc. | Methods and systems for material cladding of multilayer ceramic capacitors |
US10242803B2 (en) | 2015-07-19 | 2019-03-26 | Vq Research, Inc. | Methods and systems for geometric optimization of multilayer ceramic capacitors |
US10790426B2 (en) * | 2016-04-01 | 2020-09-29 | Nichia Corporation | Method of manufacturing light emitting element mounting base member, method of manufacturing light emitting device using the light emitting element mounting base member, light emitting element mounting base member, and light emitting device using the light emitting element mounting base member |
US11272618B2 (en) | 2016-04-26 | 2022-03-08 | Analog Devices International Unlimited Company | Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits |
US10008474B2 (en) | 2016-07-11 | 2018-06-26 | International Business Machines Corporation | Dense assembly of laterally soldered, overmolded chip packages |
US9960328B2 (en) | 2016-09-06 | 2018-05-01 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US9991206B1 (en) * | 2017-04-05 | 2018-06-05 | Powertech Technology Inc. | Package method including forming electrical paths through a mold layer |
US10497635B2 (en) | 2018-03-27 | 2019-12-03 | Linear Technology Holding Llc | Stacked circuit package with molded base having laser drilled openings for upper package |
US10515936B1 (en) * | 2018-06-25 | 2019-12-24 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
US11450606B2 (en) | 2018-09-14 | 2022-09-20 | Mediatek Inc. | Chip scale package structure and method of forming the same |
US20200312732A1 (en) | 2018-09-14 | 2020-10-01 | Mediatek Inc. | Chip scale package structure and method of forming the same |
US11410977B2 (en) | 2018-11-13 | 2022-08-09 | Analog Devices International Unlimited Company | Electronic module for high power applications |
CN113039052B (zh) | 2018-11-16 | 2023-09-05 | 惠普发展公司,有限责任合伙企业 | 引线框架装配件及引线框架的两步模制成型方法 |
US11018056B1 (en) * | 2019-11-01 | 2021-05-25 | Micron Technology, Inc. | Encapsulated solder TSV insertion interconnect |
US10998271B1 (en) | 2019-11-01 | 2021-05-04 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
US11088114B2 (en) | 2019-11-01 | 2021-08-10 | Micron Technology, Inc. | High density pillar interconnect conversion with stack to substrate connection |
KR20210126228A (ko) | 2020-04-10 | 2021-10-20 | 삼성전자주식회사 | 반도체 패키지 |
US11844178B2 (en) | 2020-06-02 | 2023-12-12 | Analog Devices International Unlimited Company | Electronic component |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020197769A1 (en) * | 2001-06-26 | 2002-12-26 | Choi Ill Heung | Semiconductor package with semiconductor chips stacked therein and method of making the package |
US20040178499A1 (en) * | 2003-03-10 | 2004-09-16 | Mistry Addi B. | Semiconductor package with multiple sides having package contacts |
TW200423322A (en) * | 2003-04-18 | 2004-11-01 | Advanced Semiconductor Eng | Stacked chip package structure |
Family Cites Families (116)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4480262A (en) | 1982-07-15 | 1984-10-30 | Olin Corporation | Semiconductor casing |
US4680613A (en) | 1983-12-01 | 1987-07-14 | Fairchild Semiconductor Corporation | Low impedance package for integrated circuit die |
US4560826A (en) | 1983-12-29 | 1985-12-24 | Amp Incorporated | Hermetically sealed chip carrier |
DE3623419A1 (de) | 1986-07-11 | 1988-01-21 | Junghans Uhren Gmbh | Verfahren zum bestuecken eines leiterbahnen-netzwerkes fuer den schaltungstraeger eines elektromechanischen uhrwerks und teilbestuecktes leiterbahnen-netzwerk eines uhrwerks-schaltungstraegers |
US5105260A (en) | 1989-10-31 | 1992-04-14 | Sgs-Thomson Microelectronics, Inc. | Rf transistor package with nickel oxide barrier |
US5153379A (en) | 1990-10-09 | 1992-10-06 | Motorola, Inc. | Shielded low-profile electronic component assembly |
US5376756A (en) | 1991-12-20 | 1994-12-27 | Vlsi Technology, Inc. | Wire support and guide |
DE4212948A1 (de) | 1992-04-18 | 1993-10-21 | Telefunken Microelectron | Halbleiterbaugruppe, insbesondere Fernsteuer-Empfangsmodul |
JPH06163794A (ja) | 1992-11-19 | 1994-06-10 | Shinko Electric Ind Co Ltd | メタルコアタイプの多層リードフレーム |
US5497032A (en) | 1993-03-17 | 1996-03-05 | Fujitsu Limited | Semiconductor device and lead frame therefore |
JPH06268101A (ja) | 1993-03-17 | 1994-09-22 | Hitachi Ltd | 半導体装置及びその製造方法、電子装置、リ−ドフレ−ム並びに実装基板 |
US5294826A (en) | 1993-04-16 | 1994-03-15 | Northern Telecom Limited | Integrated circuit package and assembly thereof for thermal and EMI management |
US5825042A (en) | 1993-06-18 | 1998-10-20 | Space Electronics, Inc. | Radiation shielding of plastic integrated circuits |
JPH0766331A (ja) | 1993-08-02 | 1995-03-10 | Motorola Inc | 半導体デバイス・パッケージの製造方法 |
US5642261A (en) | 1993-12-20 | 1997-06-24 | Sgs-Thomson Microelectronics, Inc. | Ball-grid-array integrated circuit package with solder-connected thermal conductor |
US6720493B1 (en) | 1994-04-01 | 2004-04-13 | Space Electronics, Inc. | Radiation shielding of integrated circuits and multi-chip modules in ceramic and metal packages |
AU2371795A (en) | 1994-05-17 | 1995-12-05 | Olin Corporation | Electronic packages with improved electrical performance |
US5486720A (en) | 1994-05-26 | 1996-01-23 | Analog Devices, Inc. | EMF shielding of an integrated circuit package |
JP2565300B2 (ja) | 1994-05-31 | 1996-12-18 | 日本電気株式会社 | 半導体装置 |
US5677566A (en) | 1995-05-08 | 1997-10-14 | Micron Technology, Inc. | Semiconductor chip package |
US5650659A (en) | 1995-08-04 | 1997-07-22 | National Semiconductor Corporation | Semiconductor component package assembly including an integral RF/EMI shield |
US5986340A (en) | 1996-05-02 | 1999-11-16 | National Semiconductor Corporation | Ball grid array package with enhanced thermal and electrical characteristics and electronic device incorporating same |
JP2933036B2 (ja) | 1996-11-29 | 1999-08-09 | 日本電気株式会社 | 中空パッケージ |
US5977636A (en) | 1997-01-17 | 1999-11-02 | Micron Technology, Inc. | Method of forming an electrically conductive contact plug, method of forming a reactive or diffusion barrier layer over a substrate, integrated circuitry, and method of forming a layer of titanium boride |
US6395582B1 (en) | 1997-07-14 | 2002-05-28 | Signetics | Methods for forming ground vias in semiconductor packages |
JP3479898B2 (ja) * | 1997-08-27 | 2003-12-15 | 株式会社アライドマテリアル | 半導体パッケージ |
KR100260997B1 (ko) | 1998-04-08 | 2000-07-01 | 마이클 디. 오브라이언 | 반도체패키지 |
US5977626A (en) | 1998-08-12 | 1999-11-02 | Industrial Technology Research Institute | Thermally and electrically enhanced PBGA package |
US6092281A (en) | 1998-08-28 | 2000-07-25 | Amkor Technology, Inc. | Electromagnetic interference shield driver and method |
TW418511B (en) | 1998-10-12 | 2001-01-11 | Siliconware Precision Industries Co Ltd | Packaged device of exposed heat sink |
US6411396B1 (en) * | 1999-02-24 | 2002-06-25 | Adobe Systems Incorporated | Imposition in a raster image processor |
JP3416737B2 (ja) | 1999-05-20 | 2003-06-16 | アムコー テクノロジー コリア インコーポレーティド | 半導体パッケージの製造方法 |
US6229702B1 (en) | 1999-06-02 | 2001-05-08 | Advanced Semiconductor Engineering, Inc. | Ball grid array semiconductor package having improved heat dissipation efficiency, overall electrical performance and enhanced bonding capability |
US6707140B1 (en) * | 2000-05-09 | 2004-03-16 | National Semiconductor Corporation | Arrayable, scaleable, and stackable molded package configuration |
JP2001326238A (ja) | 2000-05-17 | 2001-11-22 | Toshiba Corp | 半導体装置、半導体装置の製造方法、樹脂封止金型及び半導体製造システム |
US6717245B1 (en) | 2000-06-02 | 2004-04-06 | Micron Technology, Inc. | Chip scale packages performed by wafer level processing |
TW478119B (en) | 2000-06-26 | 2002-03-01 | Siliconware Precision Industries Co Ltd | Semiconductor package having heat sink which can be anchored on the substrate |
JP2002026044A (ja) | 2000-07-05 | 2002-01-25 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US6541310B1 (en) | 2000-07-24 | 2003-04-01 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a thin and fine ball-grid array package with embedded heat spreader |
SE517086C2 (sv) | 2000-08-08 | 2002-04-09 | Ericsson Telefon Ab L M | Förfarande för säkring av lodkulor och eventuella komponenter, vilka är fästa på en och samma sida av ett substrat |
US7273769B1 (en) | 2000-08-16 | 2007-09-25 | Micron Technology, Inc. | Method and apparatus for removing encapsulating material from a packaged microelectronic device |
US6432742B1 (en) | 2000-08-17 | 2002-08-13 | St Assembly Test Services Pte Ltd. | Methods of forming drop-in heat spreader plastic ball grid array (PBGA) packages |
US7262082B1 (en) | 2000-10-13 | 2007-08-28 | Bridge Semiconductor Corporation | Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture |
US7009297B1 (en) | 2000-10-13 | 2006-03-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal particle |
US6882042B2 (en) | 2000-12-01 | 2005-04-19 | Broadcom Corporation | Thermally and electrically enhanced ball grid array packaging |
TW454287B (en) | 2000-12-06 | 2001-09-11 | Siliconware Precision Industries Co Ltd | Multi-media chip package and its manufacture |
US7161239B2 (en) | 2000-12-22 | 2007-01-09 | Broadcom Corporation | Ball grid array package enhanced with a thermal and electrical connector |
US7132744B2 (en) | 2000-12-22 | 2006-11-07 | Broadcom Corporation | Enhanced die-up ball grid array packages and method for making the same |
US6906414B2 (en) | 2000-12-22 | 2005-06-14 | Broadcom Corporation | Ball grid array package with patterned stiffener layer |
US20020079572A1 (en) | 2000-12-22 | 2002-06-27 | Khan Reza-Ur Rahman | Enhanced die-up ball grid array and method for making the same |
US6507114B2 (en) * | 2001-01-30 | 2003-01-14 | Micron Technology, Inc. | BOC semiconductor package including a semiconductor die and a substrate bonded circuit side down to the die |
US6853070B2 (en) | 2001-02-15 | 2005-02-08 | Broadcom Corporation | Die-down ball grid array package with die-attached heat spreader and method for making the same |
US6614102B1 (en) | 2001-05-04 | 2003-09-02 | Amkor Technology, Inc. | Shielded semiconductor leadframe package |
US7259448B2 (en) | 2001-05-07 | 2007-08-21 | Broadcom Corporation | Die-up ball grid array package with a heat spreader and method for making the same |
US7061102B2 (en) | 2001-06-11 | 2006-06-13 | Xilinx, Inc. | High performance flipchip package that incorporates heat removal with minimal thermal mismatch |
US7015072B2 (en) | 2001-07-11 | 2006-03-21 | Asat Limited | Method of manufacturing an enhanced thermal dissipation integrated circuit package |
US6765287B1 (en) | 2001-07-27 | 2004-07-20 | Charles W. C. Lin | Three-dimensional stacked semiconductor package |
JP3607655B2 (ja) | 2001-09-26 | 2005-01-05 | 株式会社東芝 | マウント材、半導体装置及び半導体装置の製造方法 |
US7026708B2 (en) | 2001-10-26 | 2006-04-11 | Staktek Group L.P. | Low profile chip scale stacking system and method |
US6737750B1 (en) | 2001-12-07 | 2004-05-18 | Amkor Technology, Inc. | Structures for improving heat dissipation in stacked semiconductor packages |
US6879039B2 (en) | 2001-12-18 | 2005-04-12 | Broadcom Corporation | Ball grid array package substrates and method of making the same |
TW552689B (en) | 2001-12-21 | 2003-09-11 | Siliconware Precision Industries Co Ltd | High electrical characteristic and high heat dissipating BGA package and its process |
US7550845B2 (en) | 2002-02-01 | 2009-06-23 | Broadcom Corporation | Ball grid array package with separated stiffener layer |
US6861750B2 (en) | 2002-02-01 | 2005-03-01 | Broadcom Corporation | Ball grid array package with multiple interposers |
US7245500B2 (en) | 2002-02-01 | 2007-07-17 | Broadcom Corporation | Ball grid array package with stepped stiffener layer |
US6825108B2 (en) | 2002-02-01 | 2004-11-30 | Broadcom Corporation | Ball grid array package fabrication with IC die support structures |
US6653723B2 (en) | 2002-03-09 | 2003-11-25 | Fujitsu Limited | System for providing an open-cavity low profile encapsulated semiconductor package |
US6876553B2 (en) | 2002-03-21 | 2005-04-05 | Broadcom Corporation | Enhanced die-up ball grid array package with two substrates |
US20030178719A1 (en) | 2002-03-22 | 2003-09-25 | Combs Edward G. | Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package |
US7196415B2 (en) | 2002-03-22 | 2007-03-27 | Broadcom Corporation | Low voltage drop and high thermal performance ball grid array package |
US7276802B2 (en) * | 2002-04-15 | 2007-10-02 | Micron Technology, Inc. | Semiconductor integrated circuit package having electrically disconnected solder balls for mounting |
US6740546B2 (en) | 2002-08-21 | 2004-05-25 | Micron Technology, Inc. | Packaged microelectronic devices and methods for assembling microelectronic devices |
US6838761B2 (en) | 2002-09-17 | 2005-01-04 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
KR20050071524A (ko) | 2002-09-30 | 2005-07-07 | 어드밴스드 인터커넥트 테크놀로지스 리미티드 | 블럭 몰드 조립체용 열 강화 패키지 |
US6775140B2 (en) | 2002-10-21 | 2004-08-10 | St Assembly Test Services Ltd. | Heat spreaders, heat spreader packages, and fabrication methods for use with flip chip semiconductor devices |
US6798057B2 (en) | 2002-11-05 | 2004-09-28 | Micron Technology, Inc. | Thin stacked ball-grid array package |
US6848912B2 (en) | 2002-12-12 | 2005-02-01 | Broadcom Corporation | Via providing multiple electrically conductive paths through a circuit board |
US6861288B2 (en) | 2003-01-23 | 2005-03-01 | St Assembly Test Services, Ltd. | Stacked semiconductor packages and method for the fabrication thereof |
SG137651A1 (en) | 2003-03-14 | 2007-12-28 | Micron Technology Inc | Microelectronic devices and methods for packaging microelectronic devices |
TWI273680B (en) | 2003-03-27 | 2007-02-11 | Siliconware Precision Industries Co Ltd | Semiconductor package with embedded heat spreader abstract of the disclosure |
US7057277B2 (en) | 2003-04-22 | 2006-06-06 | Industrial Technology Research Institute | Chip package structure |
KR100493063B1 (ko) | 2003-07-18 | 2005-06-02 | 삼성전자주식회사 | 스택 반도체 칩 비지에이 패키지 및 그 제조방법 |
KR100574947B1 (ko) | 2003-08-20 | 2006-05-02 | 삼성전자주식회사 | Bga 패키지, 그 제조방법 및 bga 패키지 적층 구조 |
KR100546374B1 (ko) | 2003-08-28 | 2006-01-26 | 삼성전자주식회사 | 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법 |
US7372151B1 (en) | 2003-09-12 | 2008-05-13 | Asat Ltd. | Ball grid array package and process for manufacturing same |
US7026711B2 (en) | 2003-12-16 | 2006-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal dispensing enhancement for high performance flip chip BGA (HPFCBGA) |
US7198987B1 (en) | 2004-03-04 | 2007-04-03 | Skyworks Solutions, Inc. | Overmolded semiconductor package with an integrated EMI and RFI shield |
US7432586B2 (en) | 2004-06-21 | 2008-10-07 | Broadcom Corporation | Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages |
US7411281B2 (en) | 2004-06-21 | 2008-08-12 | Broadcom Corporation | Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same |
US7482686B2 (en) | 2004-06-21 | 2009-01-27 | Braodcom Corporation | Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same |
US7205177B2 (en) | 2004-07-01 | 2007-04-17 | Interuniversitair Microelektronica Centrum (Imec) | Methods of bonding two semiconductor devices |
CN100372116C (zh) | 2004-09-22 | 2008-02-27 | 日月光半导体制造股份有限公司 | 接触式传感器封装构造及其制造方法 |
US7786591B2 (en) | 2004-09-29 | 2010-08-31 | Broadcom Corporation | Die down ball grid array package |
US7271479B2 (en) | 2004-11-03 | 2007-09-18 | Broadcom Corporation | Flip chip package including a non-planar heat spreader and method of making the same |
US20060091542A1 (en) | 2004-11-03 | 2006-05-04 | Broadcom Corporation | Flip chip package including a heat spreader having an edge with a recessed edge portion and method of making the same |
US7354800B2 (en) | 2005-04-29 | 2008-04-08 | Stats Chippac Ltd. | Method of fabricating a stacked integrated circuit package system |
TW200642015A (en) | 2005-05-25 | 2006-12-01 | Siliconware Precision Industries Co Ltd | Sensor semiconductor device and fabrication method thereof |
US7566591B2 (en) | 2005-08-22 | 2009-07-28 | Broadcom Corporation | Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features |
US7582951B2 (en) | 2005-10-20 | 2009-09-01 | Broadcom Corporation | Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages |
US7768125B2 (en) * | 2006-01-04 | 2010-08-03 | Stats Chippac Ltd. | Multi-chip package system |
US7737539B2 (en) | 2006-01-12 | 2010-06-15 | Stats Chippac Ltd. | Integrated circuit package system including honeycomb molding |
US7435619B2 (en) * | 2006-02-14 | 2008-10-14 | Stats Chippac Ltd. | Method of fabricating a 3-D package stacking system |
US7385299B2 (en) * | 2006-02-25 | 2008-06-10 | Stats Chippac Ltd. | Stackable integrated circuit package system with multiple interconnect interface |
US20070200210A1 (en) | 2006-02-28 | 2007-08-30 | Broadcom Corporation | Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages |
US8026129B2 (en) * | 2006-03-10 | 2011-09-27 | Stats Chippac Ltd. | Stacked integrated circuits package system with passive components |
US7288835B2 (en) | 2006-03-17 | 2007-10-30 | Stats Chippac Ltd. | Integrated circuit package-in-package system |
US7714453B2 (en) | 2006-05-12 | 2010-05-11 | Broadcom Corporation | Interconnect structure and formation for package stacking of molded plastic area array package |
US9299634B2 (en) | 2006-05-16 | 2016-03-29 | Broadcom Corporation | Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages |
US8183680B2 (en) | 2006-05-16 | 2012-05-22 | Broadcom Corporation | No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement |
US20070273023A1 (en) | 2006-05-26 | 2007-11-29 | Broadcom Corporation | Integrated circuit package having exposed thermally conducting body |
US7808087B2 (en) | 2006-06-01 | 2010-10-05 | Broadcom Corporation | Leadframe IC packages having top and bottom integrated heat spreaders |
US8581381B2 (en) | 2006-06-20 | 2013-11-12 | Broadcom Corporation | Integrated circuit (IC) package stacking and IC packages formed by same |
US9013035B2 (en) | 2006-06-20 | 2015-04-21 | Broadcom Corporation | Thermal improvement for hotspots on dies in integrated circuit packages |
US8169067B2 (en) | 2006-10-20 | 2012-05-01 | Broadcom Corporation | Low profile ball grid array (BGA) package with exposed die and method of making same |
US7704800B2 (en) | 2006-11-06 | 2010-04-27 | Broadcom Corporation | Semiconductor assembly with one metal layer after base metal removal |
US8183687B2 (en) | 2007-02-16 | 2012-05-22 | Broadcom Corporation | Interposer for die stacking in semiconductor packages and the method of making the same |
-
2006
- 2006-10-30 US US11/589,120 patent/US8581381B2/en active Active
- 2006-11-28 EP EP06024645A patent/EP1870932B1/en active Active
-
2007
- 2007-06-18 CN CN200710126475.5A patent/CN101127344B/zh active Active
- 2007-06-20 KR KR1020070060780A patent/KR100884172B1/ko not_active IP Right Cessation
- 2007-06-20 TW TW096122032A patent/TWI455281B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020197769A1 (en) * | 2001-06-26 | 2002-12-26 | Choi Ill Heung | Semiconductor package with semiconductor chips stacked therein and method of making the package |
US20040178499A1 (en) * | 2003-03-10 | 2004-09-16 | Mistry Addi B. | Semiconductor package with multiple sides having package contacts |
TW200423322A (en) * | 2003-04-18 | 2004-11-01 | Advanced Semiconductor Eng | Stacked chip package structure |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11362057B2 (en) | 2019-10-22 | 2022-06-14 | Unimicron Technology Corp. | Chip package structure and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN101127344A (zh) | 2008-02-20 |
EP1870932B1 (en) | 2013-01-16 |
CN101127344B (zh) | 2014-04-16 |
US20070290376A1 (en) | 2007-12-20 |
TW200818455A (en) | 2008-04-16 |
US8581381B2 (en) | 2013-11-12 |
KR100884172B1 (ko) | 2009-02-17 |
EP1870932A1 (en) | 2007-12-26 |
KR20070120918A (ko) | 2007-12-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI455281B (zh) | Ic封裝體、堆疊式ic封裝器件及製造方法 | |
KR101076537B1 (ko) | 다이 위에 적층된 역전된 패키지를 구비한 멀티 칩 패키지모듈 | |
US9224677B1 (en) | Semiconductor package | |
US6492726B1 (en) | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection | |
US6818980B1 (en) | Stacked semiconductor package and method of manufacturing the same | |
US7141886B2 (en) | Air pocket resistant semiconductor package | |
US7834469B2 (en) | Stacked type chip package structure including a chip package and a chip that are stacked on a lead frame | |
TW200820397A (en) | Structure of package on package and method for fabricating the same | |
CN101252096A (zh) | 芯片封装结构以及其制作方法 | |
US20090278243A1 (en) | Stacked type chip package structure and method for fabricating the same | |
TWI517333B (zh) | 具雙重連接性之積體電路封裝系統 | |
US6903449B2 (en) | Semiconductor component having chip on board leadframe | |
US6984881B2 (en) | Stackable integrated circuit package and method therefor | |
US20090134504A1 (en) | Semiconductor package and packaging method for balancing top and bottom mold flows from window | |
CN101266966B (zh) | 多芯片封装模块及其制造方法 | |
CN101290929B (zh) | 堆栈式芯片封装结构 | |
CN112908945A (zh) | 一种封装组件、电子设备及封装方法 | |
JP2001358285A (ja) | 樹脂封止型半導体装置 | |
CN108630626A (zh) | 无基板封装结构 | |
KR20030055834A (ko) | 리드프레임을 이용하는 볼 그리드 어레이형 반도체 칩패키지와 적층 패키지 | |
CN113838826A (zh) | 封装结构及其制造方法 | |
CN101740552A (zh) | 多芯片封装结构及其制造方法 | |
CN101515555A (zh) | 覆晶式四方扁平无引脚型态封装结构及其制程 | |
JP2001308120A (ja) | 半導体装置の製造方法およびそれに用いられる半導体製造装置 | |
KR20040048451A (ko) | 반도체 패키지 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |