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TWI447889B - 晶片封裝結構 - Google Patents

晶片封裝結構 Download PDF

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Publication number
TWI447889B
TWI447889B TW100127940A TW100127940A TWI447889B TW I447889 B TWI447889 B TW I447889B TW 100127940 A TW100127940 A TW 100127940A TW 100127940 A TW100127940 A TW 100127940A TW I447889 B TWI447889 B TW I447889B
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Taiwan
Prior art keywords
wafer
bumps
package structure
pins
bonding region
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TW100127940A
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English (en)
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TW201308563A (zh
Inventor
Hung Che Shen
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Chipmos Technologies Inc
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Priority to TW100127940A priority Critical patent/TWI447889B/zh
Priority to CN201110308023.5A priority patent/CN102915989B/zh
Priority to US13/525,354 priority patent/US20130032940A1/en
Publication of TW201308563A publication Critical patent/TW201308563A/zh
Application granted granted Critical
Publication of TWI447889B publication Critical patent/TWI447889B/zh

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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Description

晶片封裝結構
本發明是有關於一種晶片封裝結構，且特別是有關於一種使用可撓性基板的晶片封裝結構。
隨著半導體技術的改良，使得液晶顯示器具有低的消耗電功率、薄型量輕、解析度高、色彩飽和度高、壽命長等優點，因而廣泛地應用在筆記型電腦或桌上型電腦的液晶螢幕及液晶電視等與生活息息相關之電子產品。其中，顯示器之驅動晶片(integrated circuit,IC)更是液晶顯示器不可或缺的重要元件。
因應液晶顯示裝置驅動晶片各種應用之需求，一般是採用捲帶自動接合(tape automatic bonding，TAB)封裝技術進行晶片封裝，其中又分成薄膜覆晶(Chip On Film,COF)封裝及捲帶承載封裝(Tape Carrier Package，TCP)。
請參考圖1，詳細而言，以捲帶自動接合方式進行晶片封裝的製程，係在完成可撓性基板50上的線路及晶片60上的凸塊62製程之後進行內引腳52接合(inner lead bonding，ILB)，使晶片60上的凸塊62與可撓性基板50上的內引腳52產生共晶接合而電性連接。現行可撓性基板50上包含內引腳52的線路一般是用銅箔形成，而內引腳52上另形成有錫層，以幫助凸塊62與內引腳52共晶接合時能確實連接。然而，在使用熱壓方式進行共晶接合時，內引腳52上的鍍錫若過多則可能會產生溢錫70，因內引腳52與凸塊62接合之處很接近晶片60邊緣，則溢錫70容易沿內引腳52延伸而接觸到配置於晶片60邊緣的靜電防護環(seal ring/guard ring)80，造成漏電或橋接短路等電性失效。此外，如圖2所示，即使未發生上述溢錫現象，仍可能因可撓性基板50的翹曲彎折而使靜電防護環80接觸到內引腳52(edge touch)，同樣會造成漏電或橋接短路等電性失效。
本發明提供一種晶片封裝結構，可降低晶片邊緣之靜電防護環因接觸內引腳而電性失效的機率。
本發明提出一種晶片封裝結構，包括晶片、可撓性基板、多個第一引腳及多個第二引腳。晶片具有主動面。主動面上設置有多個第一凸塊、多個第二凸塊與靜電防護環。第一凸塊鄰近晶片之第一邊。第二凸塊鄰近晶片相對第一邊的第二邊。靜電防護環位於第一凸塊與第一邊之間以及第二凸塊與第二邊之間。可撓性基板具有晶片接合區。晶片接合區具有相對的第一側與第二側。晶片係設置於晶片接合區內，且晶片之第一邊與第二邊分別對應晶片接合區之第一側與第二側。第一引腳配置於可撓性基板上，且從第一側進入晶片接合區內並向第二側延伸而分別與第二凸塊電性連接。第二引腳配置於可撓性基板上，且從第二側進入晶片接合區內並向第一側延伸而分別與第一凸塊電性連接。
在本發明之一實施例中，上述之晶片封裝結構更包括封裝膠體，設置於晶片與可撓性基板之間，以包覆第一凸塊、第二凸塊與靜電防護環。
在本發明之一實施例中，上述之第一引腳及第二引腳具有外接端及內接端，外接端遠離晶片接合區，內接端終止於晶片接合區內並與相應之凸塊連接。
在本發明之一實施例中，上述之第一引腳與第二引腳交錯排列。
在本發明之一實施例中，上述之晶片封裝結構更包括防銲層，防銲層位於晶片接合區之外並局部覆蓋第一引腳及第二引腳。
在本發明之一實施例中，上述之可撓性基板係適用於薄膜覆晶封裝(chip on film package，COF package)或捲帶承載封裝(tape carrier package，TCP package)。
基於上述，本發明的第一引腳從晶片接合區的第一側進入晶片接合區內，並往晶片接合區的第二側延伸而電性連接鄰近第二側的第二凸塊，且第二引腳從晶片接合區的第二側進入晶片接合區內，並往晶片接合區的第一側延伸而電性連接鄰近第一側的第一凸塊。藉由將引腳延伸經過晶片接合區至另一側而與鄰近該側的凸塊接合，使引腳不會橫越接合凸塊該側的晶片邊緣，當引腳與凸塊接合時產生溢錫，溢錫不會沿引腳延伸而接觸到配置於晶片邊緣的靜電防護環，因此可避免引腳與靜電防護環透過溢錫產生橋接而有漏電或短路等電性失效情況發生。再者，因為引腳延伸經過晶片接合區內，使可撓性基板強度增加，可防止可撓性基板產生下陷、翹曲等現象，進而避免晶片接合時因可撓性基板翹曲彎折而造成晶片邊緣接觸引腳(edge touch)的問題。引腳分佈於晶片接合區內，也可藉金屬的高導熱效率提升晶片封裝結構的散熱效率。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖3為本發明一實施例之晶片封裝結構的俯視圖。圖4為圖3之晶片封裝結構沿A-A’線的局部剖面圖。圖5為圖3之晶片封裝結構沿B-B’線的局部剖面圖。請參考圖3至圖5，本實施例的晶片封裝結構100包括晶片110、可撓性基板120、多個第一引腳130及多個第二引腳140。晶片110具有主動面110a，主動面110a上設置有多個第一凸塊112、多個第二凸塊114與靜電防護環116。第一凸塊112鄰近晶片110之第一邊110b，第二凸塊114鄰近相對第一邊110b的第二邊110c。靜電防護環116位於第一凸塊112與第一邊110b之間以及第二凸塊114與第二邊110c之間。於本實施例中，靜電防護環116環繞於晶片四周與第一凸塊112及第二凸塊114之間，然而靜電防護環116的範圍和形狀並不以此為限。以圖3的視角而言，部分第一引腳130、部分第二引腳140、第一凸塊112、第二凸塊114及靜電防護環116被晶片110所遮蔽而以虛線繪示。
可撓性基板120具有晶片接合區122，晶片接合區122具有相對的第一側122a與第二側122b。晶片110係設置於晶片接合區122內，且晶片110之第一邊110b與第二邊110c分別對應晶片接合區之第一側122a與第二側122b。第一引腳130配置於可撓性基板120上，且從第一側122a進入晶片接合區122內並向第二側122b延伸而分別與第二凸塊114電性連接。第二引腳140配置於可撓性基板120上，且從第二側122b進入晶片接合區122內並向第一側122a延伸而分別與第一凸塊112電性連接。藉此，第一引腳130與第二凸塊114接合時並不會橫跨經過第二凸塊114鄰近的晶片110之第二邊110c，換言之，第一引腳130會終止於第二邊110c之前，相同的，第二引腳140與第一凸塊112接合時並不會橫跨經過第一凸塊112鄰近的晶片110之第一邊110b，即第二引腳140會終止於第一邊110b之前，因此引腳130、140與凸塊112、114透過熱壓製程共晶接合時若產生溢錫，溢錫不會沿引腳130、140延伸而接觸到配置於晶片110邊緣的靜電防護環116，可避免第一引腳130及第二引腳140透過溢錫接觸到靜電防護環116，進而造成漏電或短路等電性失效問題發生。
晶片封裝結構100更包括防銲層160，防銲層160位於晶片接合區122之外並局部覆蓋第一引腳130及第二引腳140，以防止引腳130、140之間不當接觸而造成電性短路。本實施例的晶片封裝結構100例如為薄膜覆晶封裝，晶片接合區122是由防銲層160的開口所定義，然本發明不以此為限，可撓性基板120除了適用於薄膜覆晶封裝，亦適用於捲帶承載封裝，於捲帶承載封裝，晶片接合區122則由元件孔所定義。可撓性基板110的材料可選自聚醯亞胺(polyimide，PI)、聚酯類化合物(polyethylene terephthalate，PET)或其他合適的可撓性材料。
請參考圖3，第一引腳130及第二引腳140遠離晶片接合區122的部分可視為其外接端，外接端是作為晶片封裝結構100後續接合外部元件(例如：玻璃面板、印刷電路板)之用。而第一引腳130及第二引腳140終止於晶片接合區122內並與相應之凸塊(112或114)連接的部分可視為其內接端。藉由熱壓或超音波接合製程，可使第一引腳130及第二引腳140的內接端與相應的凸塊112、114共晶接合。由於第一引腳130及第二引腳140延伸經過晶片接合區122，使得可撓性基板120強度增加，因此可防止可撓性基板120產生下陷、翹曲等現象，進而避免晶片110接合時因可撓性基板120翹曲彎折而造成晶片110邊緣接觸引腳130、140的問題。再者，藉所述延伸分佈於晶片接合區122內的引腳130、140的金屬高導熱效率可幫助消散晶片110運作時產生的熱，進而提升晶片封裝結構100的散熱效率。在本實施例中，第一引腳130與第二引腳140係交錯排列，以使整體結構較為對稱，然本發明不以此為限，在其它實施例中，第一引腳130與第二引腳140亦可以其它適當方式排列。
請參考圖4及圖5，本實施例的晶片封裝結構100更包括封裝膠體150，封裝膠體150設置於晶片110與可撓性基板120之間，以包覆第一凸塊112、第二凸塊114與靜電防護環116，藉以防止濕氣及汙染物進入，進而保護凸塊112、114與引腳130、140之電性接點。圖6為圖3之晶片封裝結構沿C-C’線的局部剖面圖。圖7為圖3之晶片封裝結構沿D-D’線的局部剖面圖。如圖6所示，第二引腳140係延伸經過晶片110之第二邊110c所在區域，而在此區域未有凸塊與第二引腳140接合，因此不會產生溢錫現象，而可避免靜電防護環116透過溢錫而與引腳橋接導致短路。同樣地，如圖7所示，第一引腳130係延伸經過晶片110之第一邊110b所在區域，而在此區域未有凸塊與第一引腳130接合，因此不會產生溢錫現象，而可避免靜電防護環116透過溢錫而與引腳橋接導致短路。
綜上所述，本發明的第一引腳從晶片接合區的第一側進入晶片接合區內，並往晶片接合區的第二側延伸而電性連接鄰近第二側的第二凸塊，且第二引腳從晶片接合區的第二側進入晶片接合區內，並往晶片接合區的第一側延伸而電性連接鄰近第一側的第一凸塊。藉由將引腳延伸經過晶片接合區至另一側而與鄰近該側的凸塊接合，使引腳不會橫越接合凸塊該側的晶片邊緣，當引腳與凸塊接合時產生溢錫，溢錫不會沿引腳延伸而接觸到配置於晶片邊緣的靜電防護環，因此可避免引腳與靜電防護環透過溢錫產生橋接而有漏電或短路等電性失效情況發生。再者，因為引腳延伸經過晶片接合區內，使可撓性基板強度增加，可防止可撓性基板產生下陷、翹曲等現象，進而避免晶片接合時因可撓性基板翹曲彎折而造成晶片邊緣接觸引腳(edge touch)的問題。引腳分佈於晶片接合區內，也可藉金屬的高導熱效率提升晶片封裝結構的散熱效率。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
50、120．．．可撓性基板
52．．．內引腳
60、110．．．晶片
62．．．凸塊
70．．．溢錫
80．．．靜電防護環
100．．．晶片封裝結構
110a．．．主動面
110b．．．第一邊
110c．．．第二邊
112．．．第一凸塊
114．．．第二凸塊
116．．．靜電防護環
122．．．晶片接合區
122a．．．第一側
122b．．．第二側
130．．．第一引腳
140．．．第二引腳
150．．．封裝膠體
160．．．防銲層
圖1及圖2為習知捲帶式封裝結構的示意圖。
圖3為本發明一實施例之晶片封裝結構的俯視圖。
圖4為圖3之晶片封裝結構沿A-A’線的局部剖面圖。
圖5為圖3之晶片封裝結構沿B-B’線的局部剖面圖。
圖6為圖3之晶片封裝結構沿C-C’線的局部剖面圖。
圖7為圖3之晶片封裝結構沿D-D’線的局部剖面圖。
100．．．晶片封裝結構
110．．．晶片
110b．．．第一邊
110c．．．第二邊
112．．．第一凸塊
114．．．第二凸塊
116．．．靜電防護環
120．．．可撓性基板
122．．．晶片接合區
122a．．．第一側
122b．．．第二側
130．．．第一引腳
140．．．第二引腳

Claims (6)

  1. 一種晶片封裝結構，包括：一晶片，具有一主動面，該主動面上設置有多個第一凸塊、多個第二凸塊與一靜電防護環，該多個第一凸塊鄰近該晶片之一第一邊，該多個第二凸塊鄰近該晶片相對該第一邊的一第二邊，該靜電防護環位於該些第一凸塊與該第一邊之間以及該些第二凸塊與該第二邊之間；一可撓性基板，具有一晶片接合區，其中該晶片接合區具有相對的一第一側與一第二側，該晶片係設置於該晶片接合區內，且該晶片之該第一邊與該第二邊分別對應該晶片接合區之該第一側與該第二側；多個第一引腳，配置於該可撓性基板上，且從該第一側進入該晶片接合區內並向該第二側延伸而分別與該多個第二凸塊電性連接；以及多個第二引腳，配置於該可撓性基板上，且從該第二側進入該晶片接合區內並向該第一側延伸而分別與該多個第一凸塊電性連接。
  2. 如申請專利範圍第1項所述之晶片封裝結構，更包括一封裝膠體，設置於該晶片與該可撓性基板之間，以包覆該多個第一凸塊、第二凸塊與該靜電防護環。
  3. 如申請專利範圍第1項所述之晶片封裝結構，其中各該些第一引腳及該些第二引腳具有一外接端及一內接端，該外接端遠離該晶片接合區，該內接端終止於該晶片接合區內並與相應之該凸塊連接。
  4. 如申請專利範圍第1項所述之晶片封裝結構，其中該些第一引腳與該些第二引腳交錯排列。
  5. 如申請專利範圍第1項所述之晶片封裝結構，更包括一防銲層，該防銲層位於該晶片接合區之外並局部覆蓋該多個第一引腳及該多個第二引腳。
  6. 如申請專利範圍第1項所述之晶片封裝結構，其中該可撓性基板係適用於薄膜覆晶封裝或捲帶承載封裝。
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