1299908 九、發明說明： 【發明所屬之技術領域】 本發明有關於半導體製程，特別是一種低溫多晶矽薄 膜電晶體之製造方法。 【先前技術】 在平面顯示器例如液晶顯示器（LCD)、有機電致發光顯 示器或無機電致發光顯示器中，薄膜電晶體一般是用做開 關元件來控制晝素之作業，或是用做驅動元件來驅動晝 素。薄膜電晶體依其矽薄膜性質通常可分成非晶矽(a-Si)與 多晶砍(poly-Si)兩種。與非晶砍薄膜電晶體相比較’多晶 矽薄膜電晶體有更高之電子遷移率、更佳之液晶特性以及 較少之漏電流。因此，利用多晶矽薄膜電晶體製作之顯示 器會有較高之解析度以及較快之反應速度。然而，多晶矽 薄膜電晶體之製程卻也有許多缺點，例如良率較差、製程 複雜、成本較高。習知製造多晶矽薄膜之方法之一為利用 準分子雷射（excimer laser annealing)，其缺點在於雷射光之 高成本與製程不穩定。相反地，非晶矽薄膜電晶體卻能以 較低之成本與較簡單且發展已成熟之製程來備製。然而， 隨著顯示器之尺寸越來越大、對電氣及液晶特性之要求越 來越高，使得傳統非晶矽薄膜電晶體之製程已無法滿足大 尺寸顯示器之需求。低溫多晶矽薄膜電晶體及其製程乃應 運而生。 圖1A至1D所示為製造低溫多晶矽薄膜電晶體之習知 方法之一。請參閱圖1A，首先提供一個基體11。於基體 681954-0321TW 6 1299908 11上形成一個圖案化第一導體層12。接著在圖案化第一導 體層12上形成一層第一絕緣層13。於第一絕緣層13上形 __ 成一層多晶矽薄膜層14。然後於多晶矽薄膜層14上形成 I% 一層掺雜之多晶石夕薄膜層16。 請參閱圖1B，接著定義出包含一層圖案化多晶矽薄膜 層141與一層圖案化掺雜之多晶矽薄膜層161之主動區。 其後，請參閱圖1C，於主動區上形成一層圖案化第二導體 層17,經由開口 18曝露出圖案化摻雜之多晶矽薄膜層151 春 之局部。接著，請參閱圖1D，對曝露出圖案化摻雜之多晶 矽薄膜層161之局部予以蝕刻，經由該開口 18曝露出圖案 化多晶砍薄膜層141之局部。虛線所不為此低溫多晶砍薄 膜電晶體作業時之電流1〇路徑。電流1〇係由圖案化第二導 體層17、蝕刻後之圖案化掺雜之多晶矽薄膜層162之一側 流入，經由圖案化多晶矽薄膜層141，然後由圖案化第二 導體層17、蝕刻後之圖案化摻雜之多晶矽薄膜層162之另 一側流出。此習之方法之缺點在於蝕刻圖案化摻雜之多晶 • 矽薄膜層151以曝露出圖案化多晶矽薄膜層141之局部 時，請參閱圖1D，可能損及圖案化多晶矽薄膜層141之表 面140,因而增加表面140之粗糙度，從而使電流1〇減小。 另外，圖案化摻雜之多晶矽薄膜層161具有一定厚度，其 蝕刻需一段時間。因此希望能有一種製作低溫多晶矽薄膜 電晶體之方法來克服上述之缺點，也希望能減少蝕刻圖案 化摻雜之多晶矽薄膜層161所需之時間。 【發明内容】 681954-0321TW 7 Ϊ299908 根據本發明其一且縣每 多晶石夕薄膜電晶體之;Λ : ’在此提供一種製造低溫 上形成-個圖宰化第匕含提供一個基體；於基體 Q系化弟一導體層；於 成-層第-絕緣層；於第一二 ¥體層上形 層；於多晶矽薄膜層上、、％:开'成-層多晶矽薄膜 輸第二絕緣層予以==絕緣層；將多晶石夕薄 ;層與-個位於圖案化多晶㈣膜層上之 層；於圖案化第二絕緣層上形成一層換緣 :摻雜之多晶發薄膜層上形成一個圖二“導： 多晶發薄腺@ '膜層之局部’以及將曝露出的摻雜之 之局曰部:、曰之局部予以移除使曝露出圖案化第二絕緣層 法，供一種製造低溫多晶石夕薄膜電晶體之方 導辦爲個基體；於基體上形成一個圖案化第- 第-^緣2案化第一導體層上形成一層第一絕緣層；於 沉積-層層多晶石夕薄膜層，·於多晶石夕薄膜層上 圖宰化以^非等向性钱刻將第二絕緣層予以 形成一個圖案化第二絕緣層；以非等向性韻刻將 =曰曰/臈層予以圖案化以形成—個位於 缘 彻層;於圖案化第二絕緣= 圖案化第- 該圖案化第二導體層曝露出位於 ° 一絶緣層上方的摻雜之多晶矽薄膜層之局部；以1299908 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor process, and more particularly to a method of fabricating a low temperature polycrystalline thin film transistor. [Prior Art] In a flat panel display such as a liquid crystal display (LCD), an organic electroluminescence display, or an inorganic electroluminescence display, a thin film transistor is generally used as a switching element to control a pixel, or as a driving element. Drive the vegan. Thin film transistors are generally classified into amorphous germanium (a-Si) and polycrystalline silicon (poly-Si) depending on their properties. Compared with amorphous chopped film transistors, polycrystalline germanium film transistors have higher electron mobility, better liquid crystal characteristics, and less leakage current. Therefore, a display made of a polycrystalline germanium film transistor has a higher resolution and a faster reaction speed. However, the process of polycrystalline silicon thin film transistors has many disadvantages, such as poor yield, complicated process, and high cost. One of the conventional methods for fabricating polycrystalline germanium films is the use of excimer laser annealing, which has the disadvantage of high cost of laser light and unstable process. Conversely, amorphous germanium thin film transistors can be prepared at a lower cost and with a simpler and more mature process. However, as the size of displays has become larger and the requirements for electrical and liquid crystal characteristics have become higher, the process of conventional amorphous germanium film transistors has been unable to meet the needs of large-sized displays. Low-temperature polycrystalline germanium thin film transistors and their processes have emerged. One of the conventional methods for fabricating a low temperature polycrystalline germanium film transistor is shown in Figs. 1A to 1D. Referring to Figure 1A, a substrate 11 is first provided. A patterned first conductor layer 12 is formed on the substrate 681954-0321 TW 6 1299908 11. A first insulating layer 13 is then formed on the patterned first conductor layer 12. A polycrystalline germanium film layer 14 is formed on the first insulating layer 13. An I% layer of doped polycrystalline silicon film layer 16 is then formed on the polysilicon film layer 14. Referring to Figure 1B, an active region comprising a patterned polycrystalline germanium film layer 141 and a patterned doped polysilicon film layer 161 is then defined. Thereafter, referring to FIG. 1C, a patterned second conductor layer 17 is formed on the active region, and a portion of the patterned doped polysilicon film layer 151 is exposed through the opening 18. Next, referring to FIG. 1D, a portion of the polysilicon film layer 161 exposed to the patterned doping is etched, and a portion of the patterned polycrystalline chopped film layer 141 is exposed through the opening 18. The dotted line is not the current path for the low-temperature polycrystalline dicing of the film transistor. The current 1〇 flows from one side of the patterned second conductor layer 17 and the patterned patterned doped polysilicon thin film layer 162, via the patterned polysilicon thin film layer 141, and then patterned by the second conductive layer 17, after etching The other side of the patterned doped polysilicon film layer 162 flows out. A disadvantage of this method is that when the patterned doped polysilicon film layer 151 is etched to expose portions of the patterned polysilicon film layer 141, please refer to FIG. 1D, which may damage the surface 140 of the patterned polysilicon film layer 141. Thus, the roughness of the surface 140 is increased, thereby reducing the current 1〇. Further, the patterned doped polysilicon thin film layer 161 has a certain thickness, and etching requires a certain period of time. It is therefore desirable to have a method of fabricating a low temperature polycrystalline germanium film transistor to overcome the above disadvantages, and it is desirable to reduce the time required to etch the patterned doped polysilicon film layer 161. SUMMARY OF THE INVENTION 681954-0321 TW 7 Ϊ 299908 according to the present invention, each of the counties per polycrystalline film transistor; Λ: 'provided here to provide a low temperature formation - a graph of the 匕 匕 匕 提供 provides a substrate; The matrix Q is a conductor layer; the layer is formed on the first layer, and the second layer is formed on the polycrystalline germanium film layer, and the second insulating layer is opened on the polycrystalline germanium film layer. ==Insulating layer; polycrystalline thin; layer and a layer on the patterned polycrystalline (tetra) film layer; forming a layer on the patterned second insulating layer: doped polycrystalline film layer Forming a second figure "guide: polycrystalline thin gland @ 'the part of the film layer' and the exposed doping of the top portion: the portion of the crucible is removed to expose the patterned second insulating layer method, Providing a substrate for manufacturing a low-temperature polycrystalline slab film transistor; forming a patterned first-first layer on the substrate to form a first insulating layer on the first conductor layer; Layered polycrystalline stone film layer, on the polycrystalline stone layer, on the surface of the film Forming a second insulating layer into a patterned second insulating layer; patterning the 曰曰/臈 layer by an anisotropic rhyme to form a layer in the edge layer; patterning the second insulating layer = patterning a first - the patterned second conductor layer exposes a portion of the doped polysilicon film layer above the insulating layer;
681954-0321TW 1299908 及將曝露出的摻雜之多晶矽薄膜層之局部予以移除使曝露 出圖案化第二絕緣層之局部。 進一步根據本發明，在此提供一種低溫多晶矽薄膜電 晶體結構’其包含一個基體；一個位於基體上之圖案化第 一導體層；一個位於圖案化第一導體層上之第一絕緣層； 一個位於第一絕緣層上之圖案化多晶矽薄膜層；一個於圖 案化多晶石夕薄膜層上之圖案化第二絕緣層；一個位於圖案 化第一絕緣層上的圖案化摻雜之多晶矽薄膜層，該圖案化 摻雜之多晶矽薄膜層具有一開口使曝露出圖案化第二絕緣 層之局部；以及一個位於圖案化摻雜之多晶矽薄膜層上的 圖案化第二導體層，該圖案化第二導體層經由該開口使曝 露出圖案化第二絕緣層之局部。 【實施方式】 圖2A至2F為根據本發明其一具體實施例之製造低溫 多晶石夕薄膜電晶體之方法。請參閱圖2A，首先提供一個基 體21 ’例如玻璃基板，但不限定於玻璃基板。基體21之 厚度約為0.3至07釐米（mni)，但也可稍薄或稍厚。於基體 21上形成一個圖案化第一導體層22，例如可利用習知之物 理汽相沉積(PVD)或濺鍍製程於基體21先形成一層第一導 體層，然後利用習知之圖案化製程，例如微影與蝕刻，將 此第一導體層予以圖案化。圖案化第一導體層22之厚度約 為2000至3000埃(A)，但也可稍薄或稍厚。適合做為圖案 化第一導體層22之材料包含但不限定於銅（Cu)、鉻 (Cr)、鉬（Mo)、鉬鎢（MoW)以及鈦鋁鈦（TiAlTi)、鉬鋁 681954-0321TW 9 1299908 鉬（ΜοΑΙΜο)、或鉻鋁鉻(CrA1Cr)之複層結構。圖案化第一 導體層22係做為此製造中之低溫多晶梦薄膜電晶體之閘 極0 接著在圖案化第一導體層22上形成一層第一絕緣層 23，例如可利用習知之化學汽相沉積（CVD)或電漿輔助 CVD(PECVD)製程來備製。第一絕緣層23之厚度約為3〇〇〇 至4500埃(A)，但也可稍薄或稍厚。適合做為第一絕緣層 23之材料包含但不限定於氮化石夕（siiic〇n沾^丨和）、氧化石夕 (silicon oxide)及氡氧化石夕（siHc〇n 〇Xynitride)。第一絕緣層 23係做為此製造中之低溫多晶矽薄膜電晶體之閘極氧化 物。 然後於第一絕緣層23上形成一層多晶矽薄膜層24， 例如可利用習知之化學汽相沉積（CVD)或電漿辅助 CVD(PECVD)製程來備製，尤其是高密度電漿 CVD(HDPCVD)例如是電子迴旋加速器共振(ECR)CVD或 感應耦合電漿(ICP)CVD。 接著於多晶矽薄膜層24上形成一層第二絕緣層25， 例如可利用習知之化學汽相沉積（CVD)或電漿輔助 CVD(PECVD)製程來備製。適合做為第二絕緣層25之材料 包含但不限定於氧化矽(silicon oxide)。在本發明之一實施 例中，第一絕緣層23、多晶矽薄膜層24與第二絕緣層25 係於化學汽相沉積（CVD)或電漿辅助cVD(PECVD)製程之 同一反應室（chamber)中即時(匕-也幻依序備製，亦即在無須 破真空狀況下備製。 681954-0321TW 10 1299908 請參閱圖2B，利用習知之圖案化製程，例如微影與蝕 刻，將多晶矽薄膜層24與第二絕緣層25予以圖案化以形 成圖案化多晶矽薄膜層241與圖案化第二絕緣層251。圖 案化多晶矽薄膜層241之厚度約為1〇〇〇至15〇〇埃(入），但 也可稍薄或稍厚。圖案化多晶矽薄膜層241係做為此製造 中之低溫多晶石夕薄膜電晶體之通道(channei)。圖案化第二 絶緣層251之厚度約為1〇〇〇至15〇〇埃(人），但也可稍薄或 稍厚。圖案化第二絕緣層251係做為此製造中之低溫多晶 矽薄膜電晶體之通道防護層（CHP; channd pr〇tecti〇n)。 請參閱圖2C，於圖案化第二絕緣層251上形成一層摻 雜之多晶矽薄膜層26,例如可利用習知之化學汽相沉積 (CVD)或電漿輔助CVD(PECVD)製程，尤其是高密度電聚 CVD(HDPCVD)例如是電子迴旋加速器共振(ECR)CVD或 感應耦合電漿(ICP)CVD製程，在圖案化第二絕緣層251上 形成-層多晶㈣膜層之同時’導人摻雜氣體例㈣化氮 (PH3)來備製。在沉積雜雜之多晶⑪薄膜層26時，該換 雜之多晶㈣膜層26在其與圖案化多晶㈣膜層241之介 面處的沉積速率，約為每180秒2900〜4200埃 (2_〜420_80sec)，大於該摻雜之多晶石夕薄膜層％在其 與圖案化第二絕緣層251之介面處的沉積速率，約為每18〇 秒2100埃(21G_8GSee)。亦”者之沉積速率約為後者 之沉積速率的1.4〜2倍。如此使得圖案化第二絕緣層251 之上的摻雜之多晶⑦薄膜層26厚度遠小於圖案化多晶石夕 薄膜層241之介面處的換雜之多晶矽薄膜層％厚度。摻雜681954-0321TW 1299908 and removing portions of the exposed doped polysilicon film layer to expose portions of the patterned second insulating layer. Further in accordance with the present invention, there is provided a low temperature polycrystalline germanium thin film transistor structure comprising: a substrate; a patterned first conductor layer on the substrate; a first insulating layer on the patterned first conductor layer; a patterned polycrystalline germanium film layer on the first insulating layer; a patterned second insulating layer on the patterned polycrystalline silicon film layer; a patterned doped polysilicon film layer on the patterned first insulating layer, The patterned doped polysilicon film layer has an opening to expose a portion of the patterned second insulating layer; and a patterned second conductor layer on the patterned doped polysilicon film layer, the patterned second conductor The layer exposes a portion of the patterned second insulating layer via the opening. [Embodiment] Figs. 2A to 2F are views showing a method of manufacturing a low temperature polycrystalline thin film transistor according to an embodiment of the present invention. Referring to Fig. 2A, a substrate 21' such as a glass substrate is first provided, but is not limited to a glass substrate. The base 21 has a thickness of about 0.3 to 07 centimeters (mni), but may be slightly thinner or slightly thicker. Forming a patterned first conductor layer 22 on the substrate 21, for example, a first conductive layer can be formed on the substrate 21 by a conventional physical vapor deposition (PVD) or sputtering process, and then using a conventional patterning process, for example, The first conductor layer is patterned by lithography and etching. The patterned first conductor layer 22 has a thickness of about 2000 to 3000 angstroms (A), but may be slightly thinner or slightly thicker. Materials suitable for patterning the first conductor layer 22 include, but are not limited to, copper (Cu), chromium (Cr), molybdenum (Mo), molybdenum tungsten (MoW), and titanium aluminum titanium (TiAlTi), molybdenum aluminum 681954-0321TW 9 1299908 A layered structure of molybdenum (ΜοΑΙΜο) or chrome-aluminum-chromium (CrA1Cr). The patterned first conductor layer 22 is used as a gate of the low-temperature polycrystalline dream film transistor for this purpose. Next, a first insulating layer 23 is formed on the patterned first conductor layer 22, for example, a conventional chemical vapor can be utilized. A phase deposition (CVD) or plasma assisted CVD (PECVD) process is prepared. The first insulating layer 23 has a thickness of about 3 Å to 4,500 Å (A), but may be slightly thinner or slightly thicker. Suitable materials for the first insulating layer 23 include, but are not limited to, nitridite (siiic), silicon oxide, and siHc〇n 〇Xynitride. The first insulating layer 23 serves as a gate oxide of the low-temperature polysilicon film transistor for this purpose. A polysilicon thin film layer 24 is then formed on the first insulating layer 23, for example, by a conventional chemical vapor deposition (CVD) or plasma assisted CVD (PECVD) process, especially high density plasma CVD (HDPCVD). For example, electron cyclotron resonance (ECR) CVD or inductively coupled plasma (ICP) CVD. A second insulating layer 25 is then formed over the polysilicon film layer 24, for example, by conventional chemical vapor deposition (CVD) or plasma assisted CVD (PECVD) processes. Suitable materials for the second insulating layer 25 include, but are not limited to, silicon oxide. In an embodiment of the invention, the first insulating layer 23, the polysilicon film layer 24 and the second insulating layer 25 are in the same chamber of a chemical vapor deposition (CVD) or plasma assisted cVD (PECVD) process. In the instant (匕- 幻 依 依 , , , 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 681 24 and the second insulating layer 25 are patterned to form the patterned polysilicon thin film layer 241 and the patterned second insulating layer 251. The patterned polycrystalline germanium thin film layer 241 has a thickness of about 1 〇〇〇 to 15 〇〇 (in). However, it may be slightly thinner or slightly thicker. The patterned polycrystalline germanium film layer 241 is used as a channel for the low temperature polycrystalline thin film transistor in this fabrication. The thickness of the patterned second insulating layer 251 is about 1 〇〇. 〇 to 15 〇〇 (人), but can also be slightly thinner or slightly thicker. The patterned second insulating layer 251 is used as a channel protection layer for the low-temperature polysilicon film transistor for this fabrication (CHP; channd pr〇tecti〇 n) Referring to FIG. 2C, the second insulating layer 251 is patterned. A doped polysilicon thin film layer 26 is formed thereon, for example, by a conventional chemical vapor deposition (CVD) or plasma assisted CVD (PECVD) process, especially high density electropolymerization CVD (HDPCVD) such as electron cyclotron resonance ( The ECR) CVD or inductively coupled plasma (ICP) CVD process is performed by forming a layer of polycrystalline (tetra) film layer on the patterned second insulating layer 251 while introducing a dopant gas (IV) nitrogen (PH3). When the heteropoly 11 film layer 26 is deposited, the deposition rate of the polycrystalline (tetra) film layer 26 at the interface with the patterned poly (tetra) film layer 241 is about 2900 to 4200 angstroms per 180 seconds. (2_~420_80sec), a deposition rate greater than the doped polycrystalline thin film layer % at the interface with the patterned second insulating layer 251, about 2100 angstroms per 18 sec (21 G_8 GSee). The deposition rate is about 1.4 to 2 times the deposition rate of the latter. Thus, the thickness of the doped polycrystalline 7 film layer 26 on the patterned second insulating layer 251 is much smaller than the interface of the patterned polycrystalline film layer 241. The thickness of the polycrystalline germanium film layer at the place where it is doped
681954-0321TW 1299908 之多晶=薄膜層26的厚度約為5GG〜2GGG埃(人）。 接著’清參閱圖2D’在形成該摻雜之多晶矽薄膜層 26之後’形成多個貫穿至圖案化第一導體層22之接觸孔 ^(contact hole)。在本發明之—實施例中，則在形成圖案化 第一絕緣層251之後，即形成多個貫穿至圖案化第一導體 層22之接觸孔29。又，在本發明之另—實施例中，圖案 化多晶石夕薄膜層241之面積不大於其投影至圖案化第一導 體層22處所相對應之該段圖案化第一導體層221(如粗框 線所標）之面積。而在本發明之再一實施例中，圖案化第二 絕緣層251之面積不大於其投影至圖案化第一導體層22處 所相對應之該段圖案化第一導體層221之面積。 請參閱圖2E，於摻雜之多晶矽薄膜層26上形成一個 圖案化第二導體層27，例如可利用習知之物理汽相沉積 (PVD)或濺鍍製程於摻雜之多晶矽薄膜層26先形成一層第 二導體層，然後利用習知之圖案化製程，例如微影與蝕刻， 將此第二導體層予以圖案化。圖案化第二導體層27之厚度 約為2000〜3000埃(A)，但也可稍薄或稍厚。適合做為圖案 化第二導體層27之材料包含但不限定於銅（Cu)、鉻 (Cr)、鉬（Mo)、鉬鎢（MoW)以及鈦鋁鈦（TiAlTi)、鉬鋁 鉬(ΜοΑΙΜο)、或鉻鋁鉻(CrA1Cr)之複層結構。圖案化第二 導體層27係做為此製造中之低溫多晶矽薄膜電晶體之源 極與汲極。該圖案化第二導體層27經由開口 28曝露出位 於圖案化第二絕緣層251上方的摻雜之多晶矽薄膜層26之 局部。 681954-0321TW 12 1299908 請參閱圖2F，以圖案化第二導體層27為罩幕，利用 習知之圖案化製程，例如微影與蝕刻，將將曝露出的摻雜 之多晶矽薄膜層26之局部予以移除，使經由開口 28曝露 出圖案化第二絕緣層251之局部。虛線所示為此低溫多晶 矽薄膜電晶體作業時之電流I!路徑。電流I!係由圖案化第 二導體層27、蝕刻後之圖案化摻雜之多晶矽薄膜層261之 一侧流入，經由圖案化多晶矽薄膜層241，然後由圖案化 第二導體層27、蝕刻後之圖案化摻雜之多晶矽薄膜層261 之另一側流出。電流Ιι亦可由前述該另一側流入，然後由 前述該侧流出。 與圖1D所示之習知結構相比較，在圖2F之結構中， 圖案化多晶矽薄膜層241受到圖案化第二絕緣層251之保 護而免於受後續對圖案化摻雜之多晶矽薄膜層26之蝕刻 製程的影響。另外，圖案化第二絕緣層251上之圖案化摻 雜之多晶矽薄膜層26之厚度較薄，因此蝕刻時間便得以縮 短。又，電流I!係由圖案化多晶矽薄膜層241之一侧邊流 入，然後由另一側邊流出。而在圖1D所示之習知結構中， 電流1〇係由圖案化多晶矽薄膜層141之一侧的上方流入， 然後由另一側的上方流出。電流Ιι之路徑有利於降低總路 徑阻值，從而使開啟電流Ιι大於1〇。 圖3A至3F為根據本發明另一具體實施例之製造低溫 多晶矽薄膜電晶體之方法。請參閱圖3A，首先提供一個基 體31。於基體31上形成一個圖案化第一導體層32，做為 此製造中之低溫多晶矽薄膜電晶體之閘極。接著在圖案化 681954-0321TW 13 1299908 第一導體層32上形成一層第一絕緣層33，做為此製造中 之低溫多晶石夕薄膜電晶體之閘極氧化物。然後於第一絕緣 ， 層上形成一層多晶石夕薄膜層34，例如可利用習知之化 ， 學汽相沉積(CVD)或電漿輔助CVD(PECVD)製程來備势， 尤其是高密度電漿CVD(HDPCVD)例如是電子迴旋^速 器共振(ECR)CVD或感應孝禺合電漿(jcp)cVD。 、 接著於多晶石夕薄膜層34上形成一層第二絕緣層35， 例如可利用習知之化學汽相沉積（CVD)或電漿辅助 • cvd(pecvd)製程來備製。在本發明之一實施例中，第一 絕緣層33、多晶矽薄膜層34與第二絕緣層35係於化學汽 相沉積(CVD)或電漿辅助C VD(PECVD)製程之同一反應室 (chamber)中即時(in_situ)依序備製。 清參閱® 3B，利用習知之圖案化製程，例如微影與餘 刻，將夕a曰石夕薄膜層34與第二絕緣層35予以圖案化以形 成圖案化多晶矽薄膜層341與圖案化第二絕緣層351。圖 案化多晶石夕薄膜層241係做為此製造中之低溫多晶石夕薄膜 電晶體之通道(channel)，而圖案化第二絕緣層351係做為 此衣k中之低 多晶矽薄膜電晶體之通道防護層（CHp; ch画el protection)。在本實施例中，係以非等向性餘刻將 多晶石夕薄膜層3 4與第二絕緣層3 5予以圖案化。因此，相 對於基體而言，該圖案化多晶石夕薄㈣341之底部寬度 大於該圖案化多晶石夕薄膜層341之7貝部寬度’而該圖案化 第二絕緣層351之底部寬度大於該圖案化第二絕緣層351 之頂部寬度。如此使得後續在形成圖案化第二導體層27之 681954-0321TW 14 1299908 時能避免斷線之問題發生。 請參閱圖3C，於圖案化第二絕緣層351上形成一層摻 雜之多晶矽薄膜層36，例如可利用習知之化學汽相沉積 (CVD)或電漿輔助CVD(PECVD)製程，尤其是高密度電聚 =，CVD)例如是電子超旋加速器 感，合電漿⑽)CVD製程，在圖案化第二絕緣層351上 形成一層多晶矽薄膜層之同時， 、十導入摻雜氣體例如磷化氫 (PH3)來備製。在沉積該摻雜之客 ^ 办 夕晶矽薄膜層36時，該摻 雜= 曰曰石夕薄膜層36在其與圖案化多晶石夕薄膜層⑷ 面處的沉積速率，約為备& 母180秒2900〜4200埃 80sec) ’大於該換雜之多晶石夕薄膜其 與圖案化第二絕緣層351之介面♦a 印處的沉積速率，約為每180 秒 2100 埃(2100A/180sec)。亦 + ^ , 即則者之沉積速率約為後者 之沉積速率的1.4〜2倍。如此佶％门〜 使件圖案化第二絕緣層351 之上的摻雜之多晶矽薄膜層36 ， 尽度遠小於圖案化多晶矽 薄膜層341之介面處的摻雜之客 丄， 夕晶矽薄膜層36厚度，因而 有利於縮短蝕刻時間。摻雜之客曰 獲〜薦埃(A)。 〜夕薄，的厚度約為 接著，請參閱圖3D，在％ + # a 〜成该摻雜之多晶矽薄膜層 36之後，形成多個貫穿至圖案化 … 未化弟一導體層32之接觸孔 39(contact hole)。在本發明之〜眷μ 例中，則在形成圖案化 第二絕緣層351之後，即形成客 &夕個貫穿至圖案化第一導體 層32之接觸孔39。又，在本取 七明之另一實施例中，圖案 化多晶矽薄膜層341之面積小於 J於其投影至圖案化第一導體 681954-0321TW 15 1299908 層32處所相對應之該段圖案化第一導體層321(如粗框線 所標）之面積。而在本發明之再一實施例中，圖案化第二絕 • •緣層351之面積小於其投影至圖案化第一導體層32處所相 / 對應之該段圖案化第一導體層321之面積。 請參閱圖3E，於掺雜之多晶矽薄膜層36上形成一個 圖案化第二導體層37，做為此製造中之低溫多晶矽薄膜電 晶體之源極與汲極。該圖案化第二導體層37經由開口 38 曝露出位於圖案化第二絕緣層351上方的摻雜之多晶矽薄 _ 膜層36之局部。 請參閱圖3F，以圖案化第二導體層37為硬罩幕，利 用習知之圖案化製程，例如微影與蝕刻，將將曝露出的摻 雜之多晶矽薄膜層36之局部予以移除，使經由開口 38曝 露出圖案化第二絕緣層351之局部。虛線所示為此低溫多 晶矽薄膜電晶體作業時之電流12路徑。電流12係由圖案化 第二導體層37、蝕刻後之圖案化摻雜之多晶矽薄膜層361 之一側流入，經由圖案化多晶矽薄膜層341，然後由圖案 ❿ 化第二導體層37、蝕刻後之圖案化摻雜之多晶矽薄膜層 361之另一侧流出。電流12亦可由前述該另一侧流入，然 後由前述該侧流出。 在說明本發明之代表性具體實施例時，本說明書可將 本發明之方法及/或製程表示為一特定之步驟次序；不過， 由於該方法或製程的範圍並不繫於本文所提出之特定的步 驟次序，該方法或製程不應受限於所述之特定步驟次序。 身為熟習本技藝者當會了解其它步驟次序也是可行的。所 681954-0321TW 16 1299908 ^，不應將本朗書所提出的蚊步驟次序視為對於 =利乾圍之限制。此外，亦不應將有關本發明之方法及 I程的中請專雜圍僅限制細#面所载之步 者 靶，熟習此項技藝者易於瞭解，該等 序之风 並且仍涵蓋於本發明之精神與_之内。、°以改變， 熟習此項技藝者應即瞭解可對上述各項 行變化，而不致悖離其廣義之發明性概念。、因卜只施例進 本發明並不限於本揭之特定具體實施例，而’應瞭解 如後载各請求項所定義之本發明精神及範內二喊蓋歸屬 【圖式簡單說明】 的修飾。 當併同各隨附圖式而閱覽時，即可 較佳具體實施例之前揭摘要以及上文詳細^明^本發明各 本毛明之目的’各ffi式中裏圖繪有現屬較佳之為建說明 例。然應瞭解本發明並不限於所繪之 具體實施 裝置。在各圖式中： 排置方式及致偉 方去圖1八至1D所示為製造低溫多晶矽薄臈電晶體來 冬曰二A至2 F為根據本發明其一具體實施例之匍 夕曰曰矽薄暝電晶體之方法； 之1造低溫 少曰圖3A至3F為根據本發明另一具體實施 夕曰曰矽薄祺電晶體之方法。 之4造低溫 【主要元轉魏_】 U 基體 圖案化第一導體層The polycrystalline layer of 681954-0321 TW 1299908 = film layer 26 has a thickness of about 5 GG to 2 GGG angstroms (human). Next, referring to Fig. 2D', after forming the doped polysilicon thin film layer 26, a plurality of contact holes penetrating into the patterned first conductor layer 22 are formed. In the embodiment of the present invention, after the patterned first insulating layer 251 is formed, a plurality of contact holes 29 penetrating through the patterned first conductor layer 22 are formed. Moreover, in another embodiment of the present invention, the area of the patterned polycrystalline silicon film layer 241 is not greater than the portion of the patterned first conductor layer 221 that is projected to the patterned first conductor layer 22 (eg, The area marked by the thick frame line. In still another embodiment of the present invention, the area of the patterned second insulating layer 251 is not greater than the area of the patterned first conductor layer 221 that is projected to the patterned first conductor layer 22. Referring to FIG. 2E, a patterned second conductor layer 27 is formed on the doped polysilicon film layer 26, for example, by a conventional physical vapor deposition (PVD) or sputtering process on the doped polysilicon film layer 26. A second layer of conductors is then patterned using conventional patterning processes such as lithography and etching. The patterned second conductor layer 27 has a thickness of about 2000 to 3000 angstroms (A), but may be slightly thinner or slightly thicker. Materials suitable for patterning the second conductor layer 27 include, but are not limited to, copper (Cu), chromium (Cr), molybdenum (Mo), molybdenum tungsten (MoW), titanium aluminum titanium (TiAlTi), molybdenum aluminum molybdenum (ΜοΑΙΜο). ), or a plexiglass structure of chromium aluminum chromium (CrA1Cr). The patterned second conductor layer 27 is used as the source and drain of the low temperature polycrystalline germanium transistor for this fabrication. The patterned second conductor layer 27 exposes a portion of the doped polysilicon film layer 26 over the patterned second insulating layer 251 via the opening 28. 681954-0321TW 12 1299908 Referring to FIG. 2F, the second conductive layer 27 is patterned as a mask, and portions of the exposed polycrystalline germanium film layer 26 are exposed by a conventional patterning process such as lithography and etching. The removal is such that a portion of the patterned second insulating layer 251 is exposed through the opening 28. The dotted line shows the current I! path for this low temperature polycrystalline silicon transistor operation. The current I! flows from one side of the patterned second conductor layer 27 and the patterned doped polysilicon film layer 261 after etching, via the patterned polysilicon film layer 241, and then patterned by the second conductor layer 27, after etching The other side of the patterned doped polysilicon film layer 261 flows out. The current Ιι may also flow from the other side as described above and then flow out from the side as described above. Compared with the conventional structure shown in FIG. 1D, in the structure of FIG. 2F, the patterned polysilicon thin film layer 241 is protected by the patterned second insulating layer 251 from being subjected to subsequent patterning doping of the polysilicon thin film layer 26. The effect of the etching process. In addition, the thickness of the patterned doped polysilicon film layer 26 on the patterned second insulating layer 251 is thin, so that the etching time is shortened. Further, the current I! flows from one side of the patterned polysilicon thin film layer 241 and then flows out from the other side. In the conventional structure shown in Fig. 1D, the current 1〇 flows in from the upper side of one side of the patterned polysilicon film layer 141, and then flows out from the upper side of the other side. The path of the current Ιι helps to reduce the total path resistance so that the turn-on current Ιι is greater than 1〇. 3A through 3F illustrate a method of fabricating a low temperature polysilicon thin film transistor in accordance with another embodiment of the present invention. Referring to Figure 3A, a substrate 31 is first provided. A patterned first conductor layer 32 is formed on the substrate 31 as a gate of the low temperature polysilicon film transistor in the fabrication. A first insulating layer 33 is then formed over the first conductor layer 32 of patterned 681954-0321 TW 13 1299908 as the gate oxide of the low temperature polycrystalline thin film transistor for this fabrication. A layer of polycrystalline silicon film 34 is then formed on the first insulating layer, for example, by conventional vapor deposition (CVD) or plasma assisted CVD (PECVD) processes, especially for high density electricity. Plasma CVD (HDPCVD) is, for example, electron cyclotron resonance (ECR) CVD or induction filial plasma (jcp) cVD. Then, a second insulating layer 35 is formed on the polycrystalline silicon film layer 34, for example, by a conventional chemical vapor deposition (CVD) or plasma assisted cvd (pecvd) process. In an embodiment of the invention, the first insulating layer 33, the polysilicon thin film layer 34 and the second insulating layer 35 are in the same reaction chamber of a chemical vapor deposition (CVD) or plasma assisted C VD (PECVD) process. ) Instant (in_situ) is prepared in order. Referring to ® 3B, a conventional patterned process, such as lithography and lithography, is used to pattern the etched film layer 34 and the second insulating layer 35 to form a patterned polysilicon film layer 341 and a patterned second. Insulation layer 351. The patterned polycrystalline thin film layer 241 is used as a channel for the low temperature polycrystalline thin film transistor in the manufacturing process, and the patterned second insulating layer 351 is used as the low polycrystalline germanium film in the coating k. The channel protection layer of the crystal (CHp; ch draw el protection). In the present embodiment, the polycrystalline thin film layer 34 and the second insulating layer 35 are patterned by an anisotropic residue. Therefore, the bottom width of the patterned polycrystalline thin (four) 341 is larger than the 7-beat width of the patterned polycrystalline thin film layer 341 relative to the substrate, and the bottom width of the patterned second insulating layer 351 is greater than The top width of the patterned second insulating layer 351 is patterned. This makes it possible to avoid the problem of disconnection in the subsequent formation of the patterned 681954-0321TW 14 1299908 of the second conductor layer 27. Referring to FIG. 3C, a doped polysilicon thin film layer 36 is formed on the patterned second insulating layer 351, for example, by a conventional chemical vapor deposition (CVD) or plasma assisted CVD (PECVD) process, especially high density. The electropolymerization=, CVD) is, for example, an electron super-accelerator sensation, a plasma (10) CVD process, and a polysilicon film layer is formed on the patterned second insulating layer 351, and a doping gas such as phosphine is introduced. PH3) to prepare. When the doped guest wafer layer 36 is deposited, the doping = the deposition rate of the ruthenium film layer 36 at the surface of the patterned polycrystalline layer (4) is about &; mother 180 seconds 2900~4200 angstroms 80 sec) 'greater than the deposition rate of the interdigitated polysilicon film and the patterned second insulating layer 351 interface, about 2100 angstroms per 180 seconds (2100 A/ 180sec). Also + ^ , that is, the deposition rate is about 1.4 to 2 times the deposition rate of the latter. Thus, the doped polysilicon film layer 36 on the second insulating layer 351 is patterned to be much smaller than the doping of the interface of the patterned polycrystalline silicon film layer 341. 36 thickness, thus helping to shorten the etching time. Doped customers won the recommendation (A). ~ 薄薄, the thickness is about the next, please refer to FIG. 3D, after % + # a ~ into the doped polysilicon film layer 36, a plurality of contact holes are formed through the patterned ... unconformed conductor layer 32 39 (contact hole). In the example of the present invention, after the patterned second insulating layer 351 is formed, the contact holes 39 are formed to penetrate the patterned first conductor layer 32. Moreover, in another embodiment of the present invention, the area of the patterned polysilicon film layer 341 is smaller than the patterned first conductor of the segment corresponding to J at the layer 32 projected onto the patterned first conductor 681954-0321 TW 15 1299908. The area of layer 321 (as indicated by the thick frame line). In still another embodiment of the present invention, the area of the patterned second insulating layer 351 is smaller than the area of the patterned first conductive layer 321 that is projected/corresponding to the patterned first conductive layer 32. . Referring to FIG. 3E, a patterned second conductor layer 37 is formed on the doped polysilicon film layer 36 as the source and drain of the low temperature polysilicon film for this fabrication. The patterned second conductor layer 37 exposes a portion of the doped polysilicon thin film layer 36 over the patterned second insulating layer 351 via the opening 38. Referring to FIG. 3F, the second conductor layer 37 is patterned as a hard mask, and portions of the exposed doped polysilicon film layer 36 are removed by a conventional patterning process such as lithography and etching. A portion of the patterned second insulating layer 351 is exposed through the opening 38. The dotted line shows the current 12 path for this low temperature polysilicon film transistor operation. The current 12 flows from one side of the patterned second conductor layer 37 and the patterned doped polysilicon film layer 361 after etching, via the patterned polysilicon film layer 341, and then the second conductor layer 37 is patterned by the pattern, after etching The other side of the patterned doped polysilicon film layer 361 flows out. The current 12 can also flow in from the other side as described above and then flow out from the aforementioned side. In describing a representative embodiment of the invention, the present specification may represent the method and/or process of the invention as a specific sequence of steps; however, since the scope of the method or process is not limited to the particulars set forth herein The order of the steps, the method or process should not be limited to the specific order of steps described. It is also possible to be familiar with the sequence of other steps as a person skilled in the art. 681954-0321TW 16 1299908 ^, the sequence of mosquito steps proposed in this book should not be considered as a limitation for the 利干围. In addition, the method and the method of the present invention should not be limited to only the target of the person in the form of the ##, which is easy for the skilled person to understand, and the wind of the order is still covered by the present. The spirit of the invention is within _. , ° to change, those skilled in the art should be aware of the changes that can be made to the above, without departing from the broad concept of the invention. The present invention is not limited to the specific embodiments of the present invention, and 'should be understood that the spirit of the present invention as defined in the appended claims and the scope of the invention are as follows. Modification. When viewed with the accompanying drawings, the preferred embodiments of the present invention and the above detailed description of the invention are intended to be Construction examples. It is understood that the invention is not limited to the particular embodiment shown. In each of the drawings: the arrangement and the method shown in FIGS. 18 to 1D for the manufacture of a low-temperature polycrystalline silicon germanium transistor, which is a second embodiment of the invention according to another embodiment of the present invention. A method for thinning a germanium crystal; a method for making a low temperature layer 3A to 3F is a method for thinning a germanium transistor according to another embodiment of the present invention. 4 low temperature [main element turn Wei _] U matrix patterned first conductor layer
681954-0321TW 17 1299908 13 第一絕緣層 14 多晶石夕薄膜層 16 摻雜之多晶矽薄膜層 17 圖案化第二導體層 18 開口 21 基體 22 圖案化第一導體層 23 第一絕緣層 24 多晶矽薄膜層 25 第二絕緣層 26 摻雜之多晶矽薄膜層 27 圖案化第二導體層 28 開口 29 接觸孔 31 基體 32 圖案化第一導體層 33 第一絕緣層 34 多晶矽薄膜層 35 第二絕緣層 36 摻雜之多晶矽薄膜層 37 圖案化第二導體層 38 開口 39 接觸孔 140 表面 681954-0321TW 18 1299908 141 圖案化多晶矽薄膜層 161 圖案化摻雜之多晶矽薄膜層 蝕刻後之圖案化摻雜之多 162 矽薄膜層 221 圖案化第一導體層之一段 241 圖案化多晶矽薄膜層 251 圖案化第二絕緣層 261 圖案化摻雜之多晶矽薄膜層 321 圖案化第一導體層之一段 341 圖案化多晶矽薄膜層 351 圖案化第二絕緣層 361 圖案化掺雜之多晶矽薄膜層 681954-0321TW 19681954-0321TW 17 1299908 13 First insulating layer 14 Polycrystalline silicon film layer 16 Doped polysilicon film layer 17 Patterned second conductor layer 18 Opening 21 Substrate 22 Patterned first conductor layer 23 First insulating layer 24 Polycrystalline germanium film Layer 25 second insulating layer 26 doped polysilicon thin film layer 27 patterned second conductor layer 28 opening 29 contact hole 31 substrate 32 patterned first conductor layer 33 first insulating layer 34 polysilicon thin film layer 35 second insulating layer 36 doped Polycrystalline polysilicon film layer 37 patterned second conductor layer 38 opening 39 contact hole 140 surface 681954-0321TW 18 1299908 141 patterned polycrystalline germanium film layer 161 patterned doped polysilicon film layer after etching patterned doping 162 矽Film layer 221 patterning one segment of first conductor layer 241 patterning polysilicon film layer 251 patterning second insulating layer 261 patterning doped polysilicon film layer 321 patterning one segment of first conductor layer 341 patterning polysilicon film layer 351 pattern Second insulating layer 361 patterned doped polysilicon film layer 681954-0321TW 19