1283815* 九、發明說明： 【發明所屬之技術領域】 發明領域 本發明係關於可重新組配之平行性架構。 5【先前技術】 發明背景 電腦架構可使用平行處理來減少處理應用高計算需求 所需之週期率。然而，一些平行處理系統係靜態的，而不 能動態地響應不同的處理器或裝置來改變。 10【發明内容】 發明概要 本發明之一實施例為一種裝置，其包含用來儲存資料 之一記憶體單元；用來處理該資料之多個平行資料路徑； 用來控制該等資料路徑之多個控制單元；以及用來連接該 15 等控制單元至該等資料路徑之一開關，該開關用以接收組 態資訊，來建立該等控制單元與該等資料路徑之間的一第 一組連接結構以執行一第一程序，以及該等控制單元與該 等資料路徑之間的一第二組連接結構以執行一第二程序。 圖式簡單說明 20 實施例旨在於特別與區辨地指出說明書總結部分。然 而實施例無論就組織或運作方法，併與目的、特性、及優 勢，可參隨後附圖所為人瞭解： 第1圖繪示一系統10 0之一方塊圖； 第2圖繪示一系統200之一方塊圖； 5 ⑧ 1283815* 第3圖繪示一系統300之一方塊圖； 第4圖繪示一系統400之方塊圖；以及 第5圖繪示可重新組配邏輯500之一流程圖。 【實施方式】 5 較佳實施例之詳細說明 許多特定的細節可在此提出以提供對此實施例之全盤 了解。然而熟於此技者可明瞭實施例可不依循這些特定細 節來實現。在其他例子中，未詳細述及之習知的方法、程 序、構件、及電路不會混淆實施例。可了解此處所揭示之 1〇特別的結構性與功能性細節可呈現但不限定實施例之範 疇。 注意說明書中所指「一個實施例」或「一種實施例」 表示包括在至少-實施例中一特定特性、結構或與此實施 例有關的特徵。措詞「-實施例中」出現於說明書中許多 處不一定全指同一實施例。 現在詳參圖式’其中相同的部份全部以相同的參考數 值表示，第1圖中繪示適於實現—實施例之一系冬 乃系統廳之-方塊圖。系統100可包含多數個節點 之用詞在此處可指任何可處理一 」 呈現貪訊之訊號的元件、 20 模組、構件、板、裝置、吱系处 什 4糸統。訊號可為，譬如一 號、光訊號、聲訊號、化學却电机 於本文所述者。 就堵如此類。實施例不僅限 系統100可包含多數個以 點。「通訊媒體」之用與在此卢5類里通°孔媒體連接的節 处可指任何可承载任何資訊訊 6 1283815^ 號之媒體。通訊媒體的例子可包括金屬導線、半導體材料、 雙紅纜線、同軸纜線、光纖、無線射頻(RF)頻譜，等等。「連 接」或「互連」及諸如此類種種之用語在本文中可指實質 性連接、及/或邏輯性連接。節點可連接利用_或更多輸入 5 /輸出（"〇)轉接裔之通矾媒體，譬如一網路介面卡(NIC)。一 I/O轉接器可被組配以與任何適當之技術運作，來利用所欲 通Λ協疋、服務、及運作程序之設定控制電腦或網路裝置 之間訊號通訊。I/O轉接器亦可包括適當的實體連接器來連 接I/O轉接器與一適合的通訊媒體。1283815* IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to reconfigurable parallelism architectures. 5 [Prior Art] Background of the Invention Computer architectures can use parallel processing to reduce the cycle rate required to handle high computational demands. However, some parallel processing systems are static and cannot be dynamically changed in response to different processors or devices. 10 SUMMARY OF THE INVENTION An embodiment of the invention is an apparatus comprising a memory unit for storing data; a plurality of parallel data paths for processing the data; and for controlling the plurality of data paths a control unit; and a switch for connecting the control unit to the one of the data paths, the switch for receiving configuration information to establish a first set of connections between the control unit and the data paths The structure is configured to execute a first program and a second set of connection structures between the control units and the data paths to execute a second program. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments are intended to particularly identify the summary portion of the specification. However, the embodiments, regardless of the organization or operation method, and the purpose, characteristics, and advantages, can be understood by reference to the following figures: Figure 1 shows a block diagram of a system 100; Figure 2 shows a system 200 A block diagram; 5 8 1283815* FIG. 3 is a block diagram of a system 300; FIG. 4 is a block diagram of a system 400; and FIG. 5 is a flow chart showing a reconfigurable logic 500. . [Embodiment] 5 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A number of specific details are set forth herein to provide a complete understanding of this embodiment. However, it will be apparent to those skilled in the art that the embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits are not described in detail. It is to be understood that the specific structural and functional details disclosed herein may be present, but not limited to the scope of the embodiments. It is to be noted that the term "one embodiment" or "an embodiment" as used in the specification means that a particular feature, structure, or feature associated with the embodiment is included in at least the embodiment. The word "in the embodiment" appears in the specification and does not necessarily refer to the same embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The same portions are all represented by the same reference numerals, and FIG. 1 is a block diagram suitable for implementation - one of the embodiments of the system. The term "system 100" may include a plurality of nodes, and may refer to any element, module, component, board, device, or system that can handle a signal that is greedy. The signal can be, for example, the number one, the optical signal, the optical signal, the chemical but the motor described in this article. Just block it like this. Embodiments Not limited to System 100 may include a plurality of points. The use of "communication media" and the section connected to the media in this category 5 may refer to any media that can carry any information. Examples of communication media may include metal wires, semiconductor materials, dual red cables, coaxial cables, fiber optics, radio frequency (RF) spectrum, and the like. The terms "connected" or "interconnected" and the like may mean a substantial connection, and/or a logical connection herein. Nodes can be connected to use _ or more input 5 / output ("〇) transfer of media through the media, such as a network interface card (NIC). An I/O adapter can be configured to operate with any suitable technology to control signal communication between a computer or network device using the settings of the desired protocol, service, and operational procedures. The I/O adapter can also include a suitable physical connector to connect the I/O adapter to a suitable communication medium.
ίο 一實施例中，譬如系統1〇〇可實施為具有多數利用RF 頻譜來通訊資訊之節點的一無線系統，譬如蜂巢式或行動 系統。在此情況下，系統100中所示一或更多節點更可包含 適當的裝置與介面來以指定的尺]?頻譜通訊資訊訊號。這些 裝置和介面之例子可包括全向性天線和無線]^^收發器。實 15 施例不僅限於此段落中。 系統100之節點可被組配以通訊不同類型之資訊。譬如 一種可包含「媒體資訊」之資訊。媒體資訊可指任何的資 料呈現供予使用者之内容，譬如來自聲音對話、視訊會議、 流動視訊、電子郵件（remail」）訊息、語音訊息、文數符 20號、圖形、影像、視訊、文件及諸如此類之資料。語音對 話資料可為，譬如說話資訊、靜音期間、背景雜訊、覆蓋 雜訊、語調等等。其他類型資訊可包含「控制資訊」。控制 資訊可指任何呈現供予自動化系統之命令、指令、或控制 子組之資料。譬如控制資訊可用於將媒體資訊繞過一系 1283815· 統、或指示節點以一預定方式來處理媒體資訊。實施例不 僅限於此段落中。 糸統100之卽點可依據一或更多協定通訊媒體或控制 資訊。此處用語「協定」可指一指令集控制資訊如何在通 5 訊媒體上被通訊。協定可依一或更多協定標準定義，諸如 由網際網路工程師特別小組(IETF)、國際電信工會(ITU)、 諸如Intel®公司之公司、諸如此類所發表之標準。 如第1圖所示，系統100可包含具一無線節點1〇2和一無 線節點104之一無線通訊系統。無線節點102和1〇4可包含組 10配來在無線通訊媒體上通訊資訊之節點，諸wRF頻譜。無 線節點102和104可包含任何無線裝置或系統，諸如行動式 或蜂巢式電話、配備有無線存取卡或數據機之電腦、諸如 一無線個人數位助理(PDA)之一手持式客戶裝置、一無線存 取點、一基地臺、一行動式電話用戶中心，諸如此類。一 15實施例中，譬如，無線節點1〇2、及/或無線節點1〇4可包含 Intel®公司依據個人網際網路客戶架構(pca)所開發之無線 裝置。雖然第1圖顯示有限數量的節點，需瞭解系統1〇〇中 可使用任何數量之節點。再者，雖然實施例可能在本文中 以無線系統例示說明，此處所述發明原則亦可以有線通訊 20系統實施。實施例不僅限於本文所述者。 第2圖繪示依據一實施例一系統2〇〇之一方塊圖。系統 200部份可實施以’譬如無線節點1〇2、及/或1〇4。如第2圖 所示，系統200可包含一處理系統212、一可重新組配的通 訊架構(RCA)模組204、及一組配模組206，全經由一通訊匯 ⑧ 8 1283815· 流排2〇8連接。處理系統212更可包含處理器202和記憶體 210。雖然第2圖顯示有限數量的模組，需瞭解可系統200中 可使用任何數量之模組。 一實施例中，處理系統212可為主機系統上任何的處理 5系統，諸如無線節點102、及/或104。處理系統212可包含 處理器202。處理器2〇2可包含能供予本發明實施例適合的 速度與功能之任何類型之處理器。譬如，處理器202可為 IlUel公司及其他公司製造之處理器。處理器202亦可包含a 數位訊號處理器（DSP)及其附屬架構。處理器2〇2可更進一 10步包含一專用處理器，諸如一網路處理器、嵌入式處理器、 微控制器、控制器、輸入/輸出（I/O)處理器（IOP)，諸如此類。 實施例不僅限於本文所述者。 一實施例中，處理系統212可包含記憶體21〇。記憶體 210可包含一機器可讀式媒體及附帶之記憶體控制器或介 15面。機器可讀式媒體可包括能夠儲存適用以處理器202執行 之指令和資料的任何媒體。此種媒體之一些例子包括，但 不限定為，唯讀記憶體(ROM)、隨機存取記憶體(ram)、 可規劃ROM、可抹除可規劃R0M、電氣式可抹除可規劃 ROM、雙資料率（DDR)記憶體、動態RA]V[(DRAM)、同步 20 DRAM(SDRAM)、嵌入式快閃記憶體、及其他任何可儲存 數位資訊之媒體。 一實施例中，系統200可包含RCA模組204。RCA模組 204可為一種可重新組配的系統。一可重新組配的系統可能 包含可組配以執行不同類型應用之軟硬體組合。可重新組 9 ⑧ 1283815 配系統之一適切的例子可為Intel公司所開發之RCA系統， 譬如。 10 15 可重新組配的系統造成了增加對高效能計算機系統之 需求。譬如，成長了對能夠處理多重通訊協定計算機裝置 之需求，藉此使得無線節點到開關在任何各行各業的通訊 協定下均能接執’諸如IEEE802.il、IEEE802· 16、一般封 包無線電服務(GPRS)、增強式GPRS(EGPRS)、藍芽、超寬 頻（UWB)、第三代蜂巢式（3GPP)寬頻分碼多重存取 (WCDMA)展頻、第四代蜂巢式(4G)、ITUG.992.1非對稱數 位電活用戶線(ADSL)、ADSL2+、諸如此類等。這樣一種 能力可能，譬如，令一使用者隨其將膝上型電腦在其住宅 之一纜線數據機連接、其住宅設施之一無線區域網路 (WLAN)連接、上班通勤火車上的行動式連接、其公司的區 域網路連接之間移動而維持網際網路或一虛擬個人網路 (VPN)連續的通訊。另一實施例，在一些不同的通訊協定之 間切換之能力在商業旅行上是相當有用，譬如當使用者在 施用不同通訊標準之國家間或區域間移動。 電腦系統典型上包括軟硬體之組合，雖然彼此相對的 角色與和比例通常隨系統變化系統。軟體為準之系統典型 上藉執行一般用途硬體上電腦可讀式指來運作。另二 面，硬體為準之系統典型上包含特別設計來執行特定= 之電路，諸如—特定應用積體電路(asic)。 ·二 準之系統-般具有較軟體為準系統高之效能，雖然7為 型上也缺乏執行它㈣設計㈣行之特定任細外 20 的彈性。 槽案係用w'n统呈現—觀合方式，纽計或組配 致能。轉別設計的硬體達到近於傳統應體所提供 5 包括適應新:!配的!統亦提供軟體為準之系統的彈性’ 而^協疋、及標準之能力。因此，譬如，一 定，心+的系統可用於有效率地處理各式各樣通訊協 (DSP)，對各協定之專用ASIC轉之數他號處理器 〜二而郎省晶片尺寸、成本、及/或電力消耗。 1〇 多重執—mRCA模M2G4可包含用來執行複雜計算之 行單元订：：。一執行單元產生的結果可用為輸入其他執 15 分於硬體Γ記憶體Γ或送至另—處理系統。計算可 率之執；之間，使付—計算之不同部份視最有解決效 通訊夺^而分派到執行單心譬如，許多無線及有線 2執仃之實體層處理通常涉及㈣數值計算和較不 需伊^ 料之計算㈣合。特料對於使用通常 々、逮獲得之封包化資料的蚊。譬如，處理-8〇2.lla序 ,Γ上需求快速的序文偵測、快速自動增益控制(AGC) ^及快诉時間同步化。這些計算有益地藉處理器執行， 20 :匕括諸路徑執行單元能財效率地執行密集數值運 异、且一併能夠執行一般用途計算之組合。 -實施例中’ RCΑ模組2G4之—或更多執行單元可也配 以執行平行處理來減少延遲並增強整個系統效能。更特別 地，RCA模組204可組配以平行處理執行單—指令多重資料 (SI_平行處理和多重指令多重資#(Mimd)。 ^ ⑧ 11 1283815 -實施例中，RCA模組2〇4之-或更多執行單元可組配 以執行SIMD處理。SIMD處理可指利用一單—指八來斤制 多重處理資料路徑。每一資料路徑可利用多片資料執行相 同之操作。這種平行處理典型上用於規律的反覆運算，諸 5如有限脈衝響應（FIR)濾波、累乘運算、快速傅立葉轉換 (FFT)蝶型處理，諸如此類。 一實施例中，RC A模組204之一或更多執行單元可組配 以執行ΜIM D處理。當每一處理資料路徑以一分離的指令控 制時會發生MIMD處理。MIMD處理中，在資料路經上執行 10不同的操作。這種平行處理典型上用於異類處理需求應 用。譬如，超長指令字組(VLIW)處理器典型上即運用ΜΙΜ〇 處理。 一實施例中，系統200可包含組配模組2〇6。組配模組 206可儲存組態資訊來組配RCA模組204處理一給定靡用。 15譬如，組態資訊可用於以一第一組配來組配RCA模組204以 插作SIMD處理執行一第一程序。另一實施例中，組態資訊 可用於以一第一組配來組配RCA模組204，以操作MIMD處 理執行一第二程序。雖然組配模組2〇6顯示如系統2〇〇之一 刀離核組，需知組配核組206可包含一組儲存在記憒體21 〇 20中之程式指令和資料。實施例不僅限於本文所述者。 一般操作中，當電源施加到系統2〇〇時可開始系統 200。在初始化程序期間，處理系統212可利用儲存為部份 組配模組206之組態資訊組配rcA模組204。RCA模組204於 是可開始依據組態資訊種種功能。 ⑧ 12 1283815 一實施例中，RCA模組204之組配可被修改以適於特定 應用。此類修改可週期性地或依據一外部驅動事件。稱後 之例子中可包括接收使用者、應用、裝置等發佈之詳細指 令來組配RCA模組204。RCA模組204之組配可令rca模組 5 204為一給定處理實施一種特定的平行處理技術。平行處理 技術可依據一些不同的因素來選擇，諸如以每秒百萬指令 (MIPS)為單位之總處理速度、延遲次數、電力需求、諸如 此類。RCA模組2〇4可實施SIMD處理、MIMD處理、或任何 其組合，依其功能。 10 第3圖繪示依據一實施例之系統300方塊圖。系統3〇〇 可包含一處理器302、一 RCA模組304、及一類比前端 (AFE)306。處理器302和RCA模組304可分別示以，嬖如， 處理态202和RCA模組204。如第3圖所示，RCA模組304可 包含多重處理元件(PE)l-N、多重輸入/輸出（1/〇)節點、 15及多重路由引擎(R)1-P，依據任何數量之不同的拓樸結構經 由通訊媒體連接，譬如網目拓樸結構。I/C)節點1-Μ可被連 至種種外部裝置，諸如處理器302和AFE306。雖然第3圖顯 示有限數|的元件，需瞭解任何數量之元件可用於系統3〇〇 中。 20 一實施例中，RCA304可形成一基本設施，包含適應性 加速裔之異類陣列、資料驅動控制、及提供實體層（ΡΗγ) 與較低媒體存取控制(MAC)處理之一網目網路。尺(：：八3〇4可 運作為一無線裝置之數位基頻(ΡΗγ層）與較低MAC(資料鏈 結層）元件，譬如一軟體定義無線電（SDR)。實施例不僅限 13 1283815 於本文所述者。 一實施例中，RCA304可包含pE1_NcpE1_N可包含一 「粗操的」粒狀處理元件之異類集合。每一pE可組配以支 援多重協定，且可設計以具有接近相當專用硬體構件之區 5域和功率。每一PE利用資料驅動控制，且可依據想要的可 重新組配性及可標度參數程度實施。ΡΕ1·Ν可經由路由元件In an embodiment, for example, the system 1 can be implemented as a wireless system having a plurality of nodes that utilize the RF spectrum to communicate information, such as a cellular or mobile system. In this case, one or more of the nodes shown in system 100 may further include appropriate means and interfaces to communicate the information signals at a specified frequency. Examples of such devices and interfaces may include omnidirectional antennas and wireless transceivers. The 15 examples are not limited to this paragraph. Nodes of system 100 can be configured to communicate different types of information. For example, a piece of information that can include "media information." Media information may refer to any content presented to the user, such as from voice conversations, video conferencing, mobile video, email (remail) messages, voice messages, number 20, graphics, video, video, files. And such information. The voice message can be, for example, talking information, mute period, background noise, coverage noise, intonation, and the like. Other types of information may include "Control Information". Control information may refer to any material that presents a command, instruction, or control subgroup for an automated system. For example, control information can be used to bypass media information through a series of 1283815 systems, or to instruct nodes to process media information in a predetermined manner. The embodiment is not limited to this paragraph.糸 100 100 points can be based on one or more agreements for communication media or control information. The term "agreement" as used herein may refer to an instruction set to control how information is communicated on the media. Agreements may be defined in accordance with one or more agreed standards, such as standards published by the Internet Engineers Panel (IETF), the International Telecommunications Union (ITU), companies such as Intel®, and the like. As shown in FIG. 1, system 100 can include a wireless communication system having a wireless node 1〇2 and a wireless node 104. Wireless nodes 102 and 111 may include nodes 10 that are configured to communicate information over the wireless communication medium, the wRF spectrum. Wireless nodes 102 and 104 can include any wireless device or system, such as a mobile or cellular telephone, a computer equipped with a wireless access card or data machine, a handheld client device such as a wireless personal digital assistant (PDA), Wireless access point, a base station, a mobile phone user center, and the like. In one embodiment, for example, the wireless node 1, 2, and/or the wireless node 1-4 may include a wireless device developed by Intel® under the Personal Internet Client Architecture (pca). Although Figure 1 shows a limited number of nodes, it is important to know that any number of nodes can be used in System 1〇〇. Moreover, while the embodiments may be illustrated herein as a wireless system, the inventive principles described herein may also be implemented in a wired communication system. Embodiments are not limited to those described herein. FIG. 2 is a block diagram of a system 2 according to an embodiment. Portions of system 200 may be implemented such as wireless nodes 1, 2, and/or 1 . As shown in FIG. 2, the system 200 can include a processing system 212, a reconfigurable communication architecture (RCA) module 204, and a set of matching modules 206, all via a communication sink 8 8 1283815. 2〇8 connection. Processing system 212 may further include processor 202 and memory 210. Although Figure 2 shows a limited number of modules, it is to be understood that any number of modules can be used in system 200. In one embodiment, processing system 212 can be any processing 5 system on the host system, such as wireless node 102, and/or 104. Processing system 212 can include a processor 202. Processor 2〇2 can include any type of processor that can be adapted to the speed and functionality of embodiments of the present invention. For example, processor 202 can be a processor manufactured by IlUel Corporation and other companies. The processor 202 can also include a digital signal processor (DSP) and its associated architecture. The processor 2〇2 may further include a dedicated processor such as a network processor, an embedded processor, a microcontroller, a controller, an input/output (I/O) processor (IOP), and the like. . Embodiments are not limited to those described herein. In one embodiment, processing system 212 can include memory 21A. The memory 210 can include a machine readable medium and an attached memory controller or interface. Machine-readable media can include any medium that can store the instructions and material for execution by processor 202. Some examples of such media include, but are not limited to, read only memory (ROM), random access memory (ram), programmable ROM, erasable programmable ROM, electrical erasable programmable ROM, Dual data rate (DDR) memory, dynamic RA]V [(DRAM), Synchronous 20 DRAM (SDRAM), embedded flash memory, and any other media that can store digital information. In an embodiment, system 200 can include RCA module 204. The RCA module 204 can be a reconfigurable system. A reconfigurable system may contain a combination of hardware and software that can be assembled to perform different types of applications. Reconfigurable 9 8 1283815 An appropriate example of a distribution system can be an RCA system developed by Intel Corporation, for example. 10 15 Reconfigurable systems have created an increase in demand for high-performance computer systems. For example, the need to be able to handle multiple communication protocol computer devices has grown, thereby enabling wireless node-to-switch connections in any communication protocol of any industry, such as IEEE 802.il, IEEE 802.16, general packet radio services ( GPRS), Enhanced GPRS (EGPRS), Bluetooth, Ultra Wideband (UWB), 3rd Generation Honeycomb (3GPP) Broadband Code Division Multiple Access (WCDMA) Spread Spectrum, 4th Generation Honeycomb (4G), ITUG. 992.1 Asymmetric Digital Active Subscriber Line (ADSL), ADSL2+, and the like. Such a capability, for example, would allow a user to connect his laptop to one of his home's cable modems, one of its residential facilities, a wireless local area network (WLAN) connection, and an on-duty commuter train. The connection, the company's regional network connection moves to maintain continuous communication over the Internet or a virtual private network (VPN). In another embodiment, the ability to switch between different communication protocols is quite useful in business travel, such as when a user moves between countries or regions that apply different communication standards. Computer systems typically include a combination of hardware and software, although the relative roles and proportions of each other typically vary systemically with the system. Software-based systems typically operate on computer-readable fingers that perform general-purpose hardware. On the other hand, a hardware-based system typically includes circuitry specifically designed to perform a particular =, such as a specific application integrated circuit (asic). · The second standard system - generally has a softer system-based system performance, although the 7-type is also lacking in the flexibility of performing (4) design (4) specific lines. The trough case is presented by the w'n system—the combination method, the new meter or the group function. The hardware of the transfer design is close to that provided by the traditional application. 5 It includes adapting to the new:! The system also provides the flexibility of the system based on the software, and the ability to cooperate with the standard. Therefore, for example, the system of Heart+ can be used to efficiently process a variety of communication protocols (DSPs), and the dedicated ASICs for each protocol can be transferred to the number of processors, and the chip size, cost, and / or power consumption. 1〇 Multiple execution—mRCA mode M2G4 can contain line units for performing complex calculations::. The results produced by an execution unit can be used to input additional data to the memory or to another processing system. Calculate the rate of execution; between the different parts of the payment-calculation, depending on the most effective communication, and the assignment to the execution of a single heart, many of the wireless and wired 2 physical layer processing usually involves (4) numerical calculations and Less need to calculate the calculation of the material (four). Special materials for mosquitoes that use packetized data that is usually obtained and caught. For example, the -8〇2.lla sequence is processed, and rapid prologue detection, fast automatic gain control (AGC), and fast time synchronization are required. These calculations are advantageously performed by the processor, 20: the path execution unit can efficiently perform intensive numerical operations and can perform a combination of general purpose calculations. - In the embodiment, the RC Α module 2G4 - or more execution units can also be configured to perform parallel processing to reduce delay and enhance overall system performance. More specifically, the RCA module 204 can be configured to perform parallel-execution multi-data (SI_parallel processing and multi-instruction multi-source #(Mimd) in parallel processing. ^ 8 11 1283815 - In the embodiment, the RCA module 2〇4 The - or more execution units can be configured to perform SIMD processing. SIMD processing can refer to the use of a single-to-eight-in-one to process multiple processing data paths. Each data path can perform the same operation using multiple pieces of data. Processing is typically used for regular inverse operations, such as finite impulse response (FIR) filtering, multiplication operations, fast Fourier transform (FFT) butterfly processing, and the like. In one embodiment, one of the RC A modules 204 or More execution units can be configured to perform ΜIM D processing. MIMD processing occurs when each processing data path is controlled with a separate instruction. In MIMD processing, 10 different operations are performed on the data path. Typically used for heterogeneous processing demand applications. For example, a very long instruction word group (VLIW) processor typically employs ΜΙΜ〇 processing. In one embodiment, system 200 can include an assembly module 2〇6. 206 can be stored The configuration information is configured to assemble the RCA module 204 to process a given application. For example, the configuration information can be used to assemble the RCA module 204 with a first group to perform a SIMD process to execute a first program. In another embodiment, the configuration information can be used to assemble the RCA module 204 in a first group to operate the MIMD process to execute a second program. Although the assembly module 2〇6 is displayed as the system 2 A set of off-core sets, the set of matching core sets 206 can include a set of program instructions and data stored in the records 21 〇 20. Embodiments are not limited to those described herein. In general operation, when power is applied to the system 2 The system 200 can be started. During the initialization process, the processing system 212 can utilize the configuration information stored as the partial assembly module 206 to assemble the rcA module 204. The RCA module 204 can then begin to be based on configuration information. 8 12 1283815 In one embodiment, the assembly of the RCA module 204 can be modified to suit a particular application. Such modifications can be performed periodically or in accordance with an external drive event. The latter example can include receiving users. Detailed instructions for the release of applications, devices, etc. Equipped with RCA module 204. The combination of RCA modules 204 allows rca module 5 204 to implement a particular parallel processing technique for a given process. Parallel processing techniques can be selected based on a number of different factors, such as The total processing speed, the number of delays, the power demand, and the like in units of 10,000 instructions (MIPS). The RCA module 2〇4 can implement SIMD processing, MIMD processing, or any combination thereof, depending on its function. 10 Figure 3 shows the basis A block diagram of a system 300 of an embodiment. The system 3A can include a processor 302, an RCA module 304, and an analog front end (AFE) 306. Processor 302 and RCA module 304 can be shown, for example, processing state 202 and RCA module 204, respectively. As shown in FIG. 3, the RCA module 304 can include multiple processing elements (PE) 1N, multiple input/output (1/〇) nodes, 15 and multiple routing engines (R) 1-P, depending on any number. The topology structure is connected via a communication medium, such as a mesh topology. The I/C) nodes 1-Μ can be connected to various external devices such as the processor 302 and the AFE 306. Although Figure 3 shows the components of the finite number |, it is important to know that any number of components can be used in the system. In one embodiment, the RCA 304 can form a basic facility comprising a heterogeneous array of adaptive accelerations, data driven control, and a mesh network providing physical layer (ΡΗγ) and lower media access control (MAC) processing. The ruler (:: 八三〇4 can operate as a digital baseband (ΡΗγ layer) and a lower MAC (data link layer) component of a wireless device, such as a software defined radio (SDR). The embodiment is not limited to 13 1283815 In one embodiment, RCA 304 may comprise pE1_NcpE1_N may comprise a heterogeneous set of "rough" granular processing elements. Each pE may be configured to support multiple protocols and may be designed to have a rather rather dedicated hard Zone 5 domain and power of the body member. Each PE is driven by data and can be implemented according to the desired reconfigurability and scaleability parameters. ΡΕ1·Ν can be routed through the component
Rl-Μ以一相對低的延遲網目連接，使得架構不實質地影響 先前例說地調校規模。 一實施例中，ΡΕ1-Ν可特製為位址類之通訊應用。如 10此，ρΕ1-Ν可包含一相對較粗顆粒，其特別定位於前端育後 端處理功能、以及種種一般用途之操作。雖然ρΕ1_Ν可各被 設計為不同的操作，它們均共用包括SIMD、及/或MIMD平 行性的相似架構方式。另外，它們都具有可透過顧客定製 達最佳化之執行單元來執行其所欲功能同時允許一些合理 15 的參數變更彈性。 一實施例中，一或更多PE1_N之PE可實施為一般用途 微編碼加速H(GPMCA)。AGPMCA可組配以執行一組一般 運算，諸如矩陣轉換、符號編解碼、解變頻、循環冗餘檢 查（CRC)處理，諸如此類。在者，pE可組配以為這些操作 20執行平行處理，諸如SIMD處理，MIMD處理，諸如此類。 這樣一種PE可參照第4圖作更進一步之描述。 一實施例中」RCA304可包含I/O節點1-M。I/O節點1-M 可操作為介接與種種外部裝置，諸如一處理器3〇2。處理器 302可包含’一嵌入式控制器。1/〇節點亦可介接與 P83815 AFE306。實施例不僅限於本文所述者。 -實施例中，系統300可包含一或更多類比RF前端裝 置，諸如AFE306。為從無線節點i〇2、及/或i〇4傳送，afe· 可轉換RF之數位化基頻樣本。相同地，為接收的rf訊號， 5 AFE306可轉換所欲RF頻帶至一數位化基頻。實施例不僅限 於本文所述者。 * 一般操作中，處理器302可提供所需之全面控制和監督 來下載必需的設定資訊至每一PE1_N*I/0節點1-M，以及任 何必需之AFE306資訊。另外，就其控制功能，處理器3〇2 10可提供MAC層功能性操作。在PE1-N網目每一處1係一路由 引擎（R1-M) ’其為部份網目互聯。每一 pEi-N電氣連接 R1_M。初始化期間，處理器302經由網目互聯利用組配資 料封包下載組恝資訊及資料記憶體之初始内容至每一 PE1-N。一旦所有組態資訊經下載而pEiN被起始，處理操 15 作可開始。 系統300可執行一些不同的功能，諸如傳送與接收功 能。當執行傳送功能時，處理器302為PHY基頻處理傳遞資 料到PE1-N。當基頻處理發生，數位化樣本流至一或更多 AFE306以轉換成RF，接著經由一附數天線發送。就接收功 20能，AFE3〇6自天線接收RF訊息，將RF訊號轉成基頻，並為 數位基頻處理傳遞數位化樣本PE1-N。一經處理，數位資料 為MAC層處理被遞送到處理器3〇2。 苐4圖緣不依據一貫施例一系統4〇〇之一方塊圖。系統 400可示以譬如，一pe，譬如系統300之peI-N。另外，系 ⑤ 1283815 統400可實施以任何可以具有可重新組配的硬體和軟體元 件之處理系統之部份。實施例不僅限於本文所述者。 一實施例中，系統400可包含負責執行操作之一 GPMCA建構方塊，諸如種種通訊協定之基頻符號處理 5 f⑽，諸如IEEE802.11、IEEE802.16、一般封包無線電服務 (GPRS)、增強式GPRS(EGPRS)、藍芽、超寬頻(UWB)、第 三代蜂巢式(3GPP)寬頻分碼多重存取(WCDMA)展頻、第四 代蜂巢式（4G)、ITUG.992.1非對稱數位電話用戶線 (ADSL)、ADSL2+、諸如此類等。通訊協定之類型不僅限 10 於本文中所述者。 一實施例中，符號處理可能需要一些不同的資料路 徑。系統400可組配以適用一給定之協定。又，不同的平行 處理結構可用於一給定協定中不同的功能。因此，系統4〇〇 可減少整個裝置之時脈和電力需求，諸如無線節點1〇2、及 15 / 或 104。 如所示第4圖，系統400可包含連接至一開關404之多重 控制單元1-R。控制單元1-R和開關404可連至一主控制器 402。開關404亦可連至資料路徑(DP)l-S。DP1-S可連至記 憶體406。雖然第4圖顯示有限數量的控制單元與資料路 20徑，需瞭解任何數量之可用於系統400中而仍落於實施例之 範圍中。 一實施例中，系統4〇〇可包含控制單元丨-R。系統4〇〇 之操作以一或更多控制單元丨-R控制。每一控制單元卜R組 配以傳送從控制單元所執行之功能推衍出之功能控制訊息 16 1283815 至系統400之種種構件。譬如，控制單元丨可經由開關4〇4傳 迗功能控制訊息至DPI，指定操作從記憶體4〇6讀取之資 料。一實施例中，每一控制單元丨劣傳送表示單一功能之功 能控制訊息。每一控制單元1-R可為可重新組配的來提供不 5同的功能。一實施例中，用於重新組配種種DP1-S之訊息町 藉-執行-或更多控制單元之狀態機器於每一時脈週期被 傳送。 一實施例中，系統400可包含]〇1>14。1^^一般設計 來執行密集的數值運算，譬如那些涉及Dsp計算之運管。 10 DP1-S可組配以根據控制單元^和DP1_S之間的連接:構 利用SIMD處理或MIMD處理平行執行其處理。每一資^路 徑可組配與任何適於一組想要的運算的邏輯電路。譬如， 資料路徑可包含一多輸入預加法器、乘法器、一累加器暫 存器，諸如此類。一實施例中，這些元件可以控制單元來 15組配以執行不同的功能 '此類快速FFT、濾波操作、諸 類等等。 〇此 一實施例中，系統400可包含開關404。開關4〇4可包含 可以切換控制單元i-R和DP1_S間之訊息的任何開關。 控制哪些控制單元連接至哪個DP。連接結構令控制單一 * 20送控制訊息至連接的DP。此開關可包含，譬如，一 鬥開關、 月板’諸如此類。實施例不僅限於本文所述者。 一實施例中，系統400可包含主控制器4〇2。士 ^ α 王控制器 402可接收來自組配模組2〇6之組態資訊，並組配開關奶4來 依據一給定應用建立連接。譬如，一單一控制單元（链如Rl-Μ is connected with a relatively low latency mesh, so that the architecture does not materially affect the previously calibrated scale. In one embodiment, ΡΕ1-Ν can be specially designed as a communication application of the address class. For example, ρΕ1-Ν may comprise a relatively coarser particle which is particularly localized to the front end post-processing function and to a variety of general purpose operations. Although ρΕ1_Ν can each be designed for different operations, they all share a similar architectural approach including SIMD, and/or MIMD parallelism. In addition, they all have the ability to perform their desired functions through custom-designed execution units while allowing some reasonable 15 parameter flexibility. In one embodiment, one or more PEs of PE1_N may be implemented as a general purpose microcoded acceleration H (GPMCA). The AGPMCA can be configured to perform a set of general operations such as matrix conversion, symbolic codec, de-conversion, cyclic redundancy check (CRC) processing, and the like. In other words, the pE can be configured to perform parallel processing for these operations 20, such as SIMD processing, MIMD processing, and the like. Such a PE can be further described with reference to FIG. In an embodiment, the RCA 304 can include an I/O node 1-M. The I/O nodes 1-M are operable to interface with various external devices, such as a processor 3〇2. Processor 302 can include an embedded controller. The 1/〇 node can also interface with the P83815 AFE306. Embodiments are not limited to those described herein. In an embodiment, system 300 can include one or more analog RF front end devices, such as AFE 306. To transmit from the wireless node i〇2, and/or i〇4, the afe· convertible RF digital baseband samples. Similarly, for the received rf signal, the 5 AFE 306 can convert the desired RF band to a digitized baseband. The embodiments are not limited to those described herein. * In normal operation, processor 302 can provide the full control and supervision required to download the necessary setup information to each PE1_N*I/0 node 1-M, as well as any required AFE 306 information. In addition, with its control function, the processor 3〇2 10 can provide MAC layer functional operations. In each of the PE1-N networks, a routing engine (R1-M) is part of the mesh interconnection. Each pEi-N is electrically connected to R1_M. During initialization, the processor 302 downloads the initial contents of the group information and data memory to each PE1-N via the mesh interconnection using the combined resource packet. Once all configuration information has been downloaded and pEiN is initiated, the processing can begin. System 300 can perform a number of different functions, such as transmitting and receiving functions. When the transfer function is performed, processor 302 passes the data to PE1-N for the PHY baseband processing. When the baseband processing occurs, the digitized samples are streamed to one or more AFEs 306 for conversion to RF, and then transmitted via an additional antenna. In response to the received power 20, the AFE3〇6 receives the RF message from the antenna, converts the RF signal to the fundamental frequency, and delivers the digitized samples PE1-N for the digital baseband processing. Once processed, the digital data is delivered to the processor 3〇2 for MAC layer processing.苐4 picture edge is not based on a consistent example of a system 4 〇〇 one block diagram. System 400 can be shown, for example, as a pe, such as peI-N of system 300. In addition, the system 5 1283815 can be implemented as part of any processing system that can have reconfigurable hardware and software components. Embodiments are not limited to those described herein. In one embodiment, system 400 can include a GPGCA construction block responsible for performing operations, such as baseband symbol processing 5f(10) for various communication protocols, such as IEEE 802.11, IEEE 802.16, General Packet Radio Service (GPRS), Enhanced GPRS. (EGPRS), Bluetooth, Ultra Wideband (UWB), 3rd Generation Honeycomb (3GPP) Broadband Code Division Multiple Access (WCDMA) Spread Spectrum, 4th Generation Honeycomb (4G), ITUG.992.1 Asymmetric Digital Telephone Subscriber Line (ADSL), ADSL2+, and the like. The type of communication agreement is not limited to 10 described in this article. In one embodiment, symbol processing may require some different data paths. System 400 can be configured to apply a given agreement. Also, different parallel processing structures can be used for different functions in a given protocol. Thus, system 4 can reduce the clock and power requirements of the entire device, such as wireless nodes 1, 2, and 15 / or 104. As shown in Figure 4, system 400 can include multiple control units 1-R coupled to a switch 404. Control unit 1-R and switch 404 can be coupled to a main controller 402. Switch 404 can also be connected to data path (DP) 1-S. DP1-S can be connected to the memory 406. While Figure 4 shows a limited number of control units and data paths, it is to be understood that any number can be used in system 400 while still falling within the scope of the embodiments. In one embodiment, system 4A can include a control unit 丨-R. The operation of system 4 is controlled by one or more control units 丨-R. Each control unit R is configured to transmit various functional components of the system control message 16 1283815 derived from the functions performed by the control unit. For example, the control unit 传 can transmit the function control message to the DPI via the switch 4〇4, and specify the information to be read from the memory 4〇6. In one embodiment, each control unit transmits a function control message that represents a single function. Each control unit 1-R can be reconfigurable to provide a different function. In one embodiment, the state machine for reassembling the various DP1-S messages, the -execution- or more control units is transmitted at each clock cycle. In one embodiment, system 400 can include a <1> 14. 1^^ is generally designed to perform intensive numerical operations, such as those involving Dsp calculations. 10 DP1-S can be grouped according to the connection between the control unit ^ and DP1_S: The processing is performed in parallel using SIMD processing or MIMD processing. Each path can be combined with any logic suitable for a desired set of operations. For example, the data path can include a multiple input pre-adder, multiplier, an accumulator register, and the like. In one embodiment, these components can be controlled by a group of 15 to perform different functions 'such fast FFTs, filtering operations, classes, and the like. In this embodiment, system 400 can include a switch 404. Switch 4〇4 can include any switch that can switch between messages between control units i-R and DP1_S. Control which control units are connected to which DP. The connection structure allows a single control to send control messages to the connected DP. This switch can include, for example, a bucket switch, a moonboard, and the like. Embodiments are not limited to those described herein. In an embodiment, system 400 can include a main controller 4〇2. The controller α α can receive configuration information from the assembly module 2〇6 and combine the switch milk 4 to establish a connection according to a given application. For example, a single control unit (chain such as
17 1283815 控制單元1)可組配以控制全部4個資料路徑Dp〗$。在此狀 況下，主控制器402可組配開關404來連接控制單元1一 DP1-S來令控制單元1傳送控制訊息至〇]?14。此可為一適 口來執行SIMD處理之組配，譬如。另一實施例中，每一控 5制單元可組配以控制分別對應的DP1-S。每一控制單元 1 R可僅傳送控制訊息至其個別DP1-S。此可為適於執行 MIMD處理之組配。亦可實施任何控制單元之 、·且配。譬如，可組配成以一控制單元控制兩資料路徑，而 另一控制單元控制令兩資料路徑之一2χ2組配。實施例不僅 10限於本文所述者。 一實施例中，系統400可包含記憶體4〇6。記憶體4〇6 I含任何满型之§己憶體以儲存糟系統400執行之資料。記 憶體406可從其他ΡΕ以封包型式累積資料。收到得資料可儲 存在纪憶體406中。當所接收之資料達到開始處理之足量 時，控制單元1-R開始傳送控制訊息到Dpi_s來開始處理資 料。 前述系統之操作更可參照附圖與例子更詳細地描述。 某些圖式可能包括規劃邏輯。雖然此處所呈現之圖式可能 包括一特定規劃邏輯，需知規劃邏輯僅為提供此處所述一 2〇般功能性可如何實施之例子。再者，給定的規劃邏輯除非 、、二心定’否則不一定得須以所示順序執行。另外，雖然髓 、’、°之規劃邏輯在此處所述為實施於前述模組中，需瞭解規 邏輯可實施於此系統内任何地方並仍落於此實施例之範 疇。 ⑧ 1283815 第5圖繪示依據一實施例用於一可組配邏輯500之一方 塊流程圖。第5圖繪示一可組配邏輯5〇〇，其可表示依據一 貫施例由一PE執行之操作。如所示可組配邏輯500,組態資 成可在方塊502之一開關被接收。此開關可組配以建立在多 5數個控制單元和多數個資料路徑之間的一第一組連接來於 方塊504執行利用SIMD處理之一第一程序。此開關可組配 以建立在多數個控制單元和多數個資料路徑之間的一第二 組連接來於方塊5〇6執行利用MIMD處理之一第二程序。每 一控制單it可控制_單_程式指令之執行。 1〇 一貫施例中，每一控制單元可組配以控制單一程式指 7之執行。程式指令可依據不同的應用變化。 貝施例中，第一組連接可組配開關404以一第一組配 來連接控制單元1_R及資料路徑DP1-S以執行SIMD處理。譬 如第組連接可連接至少一控制單元至多重資料路徑 1 S以泫個控制單元控制多重資料路徑DP1-S。在此組 酉己中，话董' j ^ 母一資料路徑1^^可組配以利用儲存在記憶 一 貝料執行一組相同的平行操作。此可適於許多通訊 應用，諸如 、、 乂刀頻(0FDM)載波上執行編碼之符號。由於所有 20載波^執仃相似的操作，s細處理可造成改善的系統效 月匕貝^例不僅限於本文所述者。 、例中，第二組連接可組配開關404來連接控制單 元1-R到在一楚一 一 系一、、且配之資料路徑DP1-S以執行MIMD處 理。譬如，裳— 一、、且連接可連接多重控制單元至多重資料路 ⑧ 19 1283815 徑，以每一控制單元來控制一單一資料路徑。在此組配中， 譬如，每一資料路徑DP1-S可利用儲存在記憶體4〇6中之資 料組配與一組不同的平行操作。此可適於許多通訊應用， 諸如實施PHY控制狀態機器，及整個資料流操作諸如竄插 5和多工。此群組包含在某些情況中需平行執行之異類低 MIPS操作，且因kMIMD處理可實施以增進系統效能。實 施例不僅限於本文所述者。 部份實施例可被實施以例用一架構，其可依據任何數 量之因素變化，譬如所欲運算率、功率位準、熱容受、處 1〇理週期預算、輸入資料率、輸出資料率、記憶體資源、資 料匯流排速度、和其他效能限制。譬如一實施例的一部分 可施用由處理器執行之軟體，如前述。另一範例中，一實 施例可實施以專用硬體，譬如ASIC、可規劃邏輯裝置(朽 或DSP、及相伴硬體結構。又另一實施例，可施用任何麵 15規劃的一般用途電腦構件與客製硬體構件之組合。實施例 不僅限於此段落中。 實施例可能已描述一或更多模組。雖然以「模組」來 說明實施例以便描述，然而更可以一或更多電路、構件、 暫存器、處理器、軟體副常式、或任何其組合來代替一個、 20多個、或所有的模組。實施例不僅限於此段落中。 在此以舉例說明實施例之一些特性，許多的修改、替 換、變更、及等效同時將令熟於此技者所思及。因此也就 是說，隨附申請專利範圍及意圖涵蓋所有落於具有實施例 所揭示精神之修改與變化。 1283815 圖式簡單說明】 第1圖繪示一系統100之一方塊圖； 第2圖繪示一系統200之一方塊圖； 第3圖繪示一系統300之一方塊圖； 第4圖繪示一系統400之方塊圖；以及 第5圖繪示可重新組配邏輯500之一流程圖 主要元件符號說明】 102· 104· 202· 204. 206· 208· 210· >無線節點 *無線節點 •處理器 •RCA模組 •組配模組 •匯流排 •記憶體 302 304 306 402 404 406 處理器 RCA AFE 主控制器 開關 記憶體 502-206····程序 212····處理系統17 1283815 Control unit 1) can be combined to control all 4 data paths Dp〗. In this case, the main controller 402 can be configured with a switch 404 to connect the control unit 1 - DP1-S to cause the control unit 1 to transmit control messages to 〇 14 14 . This can be a suitable interface for performing SIMD processing, for example. In another embodiment, each of the control units can be combined to control the respective DP1-S. Each control unit 1 R can only transmit control messages to its individual DP1-S. This can be a combination suitable for performing MIMD processing. It can also be implemented with any control unit. For example, it can be configured to control two data paths by one control unit, and the other control unit controls one of the two data paths to be combined. Embodiments are not limited to only those described herein. In one embodiment, system 400 can include memory 4〇6. The memory 4〇6 I contains any full-form suffix to store the data executed by the bad system 400. The memory 406 can accumulate data from other types in a packet type. The data received can be stored in the memory 406. When the received data reaches a sufficient amount to start processing, the control unit 1-R starts transmitting a control message to Dpi_s to start processing the data. The operation of the foregoing system can be described in more detail with reference to the accompanying drawings and examples. Some diagrams may include planning logic. While the figures presented herein may include a particular planning logic, it is understood that the planning logic is merely an example of how the functionality described herein can be implemented. Furthermore, the given planning logic does not necessarily have to be performed in the order shown unless it is . Additionally, while the planning logic of the marrow, ', is described herein as being implemented in the aforementioned modules, it is to be understood that the logic can be implemented anywhere within the system and still fall within the scope of the embodiments. 8 1283815 FIG. 5 is a flow diagram of a block diagram for an assembleable logic 500 in accordance with an embodiment. Figure 5 illustrates an configurable logic 5 〇〇 which may represent the operation performed by a PE in accordance with a consistent embodiment. The logic 500 can be assembled as shown, and the configuration information can be received at one of the blocks 502. The switch can be configured to establish a first set of connections between the more than five control units and the plurality of data paths to perform a first program using SIMD processing at block 504. The switch can be configured to establish a second set of connections between the plurality of control units and the plurality of data paths to perform a second program utilizing MIMD processing at block 5-6. Each control unit can control the execution of the _ single_program instruction. 1〇 In the usual example, each control unit can be combined to control the execution of a single program finger. Program instructions can vary depending on the application. In the example of the first embodiment, the first set of connectable switch 404 is coupled to the control unit 1_R and the data path DP1-S in a first group to perform SIMD processing.譬 For example, the first group connection can connect at least one control unit to the multiple data path 1 S to control the multiple data paths DP1-S by one control unit. In this group, the words 'dong' j-mother data path 1^^ can be combined to perform a set of identical parallel operations using the memory stored in the material. This can be adapted to many communication applications, such as , , , , , , , , , , , , , , , , , , , , , , , , , Since all 20 carriers perform similar operations, s fine processing can result in improved system efficiency. The examples are not limited to those described herein. In the example, the second group of connections can be configured to switch the control unit 404 to connect the control unit 1-R to the data path DP1-S to perform the MIMD processing. For example, the skirt - one, and the connection can be connected to multiple control units to the multiple data path 8 19 1283815 path, with each control unit to control a single data path. In this combination, for example, each data path DP1-S can be grouped with a different set of parallel operations using the data stored in the memory 4〇6. This can be adapted for many communication applications, such as implementing a PHY control state machine, and the entire data flow operations such as cutting 5 and multiplexing. This group contains heterogeneous low MIPS operations that need to be performed in parallel in some cases, and can be implemented to improve system performance due to kMIMD processing. The embodiments are not limited to those described herein. Some embodiments may be implemented to use an architecture that may vary depending on any number of factors, such as desired rate of operation, power level, heat capacity, 1 processing period budget, input data rate, output data rate. , memory resources, data bus speed, and other performance limitations. A software executed by a processor can be applied as part of an embodiment, as previously described. In another example, an embodiment may be implemented with dedicated hardware, such as an ASIC, programmable logic device (degraded or DSP, and associated hardware structure. Yet another embodiment, a general purpose computer component that can be applied to any face 15 plan Combination with custom hardware components. Embodiments are not limited to this paragraph. Embodiments may have described one or more modules. Although the embodiments are described in terms of "modules" for description, one or more circuits may be used. A component, a register, a processor, a software subroutine, or any combination thereof, in place of one, more than 20, or all of the modules. Embodiments are not limited in this paragraph. Here are some examples of embodiments Many modifications, substitutions, alterations, and equivalents will be apparent to those skilled in the art. Therefore, the scope of the accompanying claims is intended to cover all modifications and changes that come within the spirit of the embodiments. 1283815 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a system 100; FIG. 2 is a block diagram of a system 200; FIG. 3 is a block diagram of a system 300; A block diagram of a system 400 is shown; and FIG. 5 illustrates a flow chart of the main components of one of the reconfigurable logics 500. 102·104·202· 204. 206·208·210· > Wireless Node* Wireless Node • Processor • RCA Module • Assembly Module • Bus • Memory 302 304 306 402 404 406 Processor RCA AFE Main Controller Switch Memory 502-206···· Program 212····Processing System