1277126 12336twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體製程，且特別是有關於一 種釋放晶圓應力的方法。 【先前技術】 由於現今半導體元件係建構於單晶矽晶圓（silic〇n wafer)上，為了量產及降低製造成本，晶圓直徑已由早期 的4吋、5吋、6吋演變至現今的8吋及12吋，使得一片 晶圓上能同時製作更多晶片。 在許多半導體製程中，都是先將連續的膜層沈積於整 片曰曰圓上之後’再以微影敍刻製程來形成所需之圖案化膜 層。以金屬内連線製程為例，係在晶圓上形成介電層之後， 再圖案化此介電層以形成介層窗開口或是溝渠，然後再於 介層窗開口或是溝渠填入金屬材料。然而，當所沈積的膜 層由於製^素(例如：化學機械研料)而使其具有高應 力時，此高應力膜層將使得整個晶圓產她曲，而此種魏 曲現象將對後續製程造成影響。 第一 1A圖至第ic圖係!會示習知金屬内連線製程的流 ^面示意圖。首先，請參照第1A圖，晶圓100上已形 */入’Ll層102 ’並且在介電層102巾已形成有多個接觸 =二固104，接著，在整個晶圓100上形成介電層106 介電層102與接觸窗/介層窗刚上。其中由於介 電層^具有高應力，而使得晶圓100呈勉曲狀態。 接著，請參照第1B圖，進行微影製程，以在介電層 1277126 12336twf.doc/006 106上形成圖案化之光阻層1⑽。此時，圖案化之光阻層 108係暴露出介電層106之預定形成溝渠的位置，亦即是 金屬導線之預定配設位置。 接著，請參照第1C圖，壤授一蝕刻製程，移除暴露 出之介電層106,以形成開合、^〇〉)此時由於介電層1〇6 已不再是一連續之膜層，且介電廣1〇6被移除之部分所形 成的開口 11〇可釋放其所承受之應力。因此，介電層1〇6 在蝕刻的製程後，會恢復原先未翹曲的形狀。 然而，圖案化之光阻層108係形成於翹曲狀態下的介 電層106上，而形成在開口 11〇的過程中，由於介電層ι〇6 會恢復原先之形狀，因此，當晶圓恢復未翹曲的狀態後， 開口 110的位置會產生偏移而導致與接觸窗/介層窗綱 對不準(misalignment)的問題。 尚且，上述對不準的問題係由翹曲中心向外圍漸漸增 大’對於較大尺寸的晶圓而言，此翻題更顯嚴重，對於 翹曲晶圓的外圍位置而言，在後續形成金屬導線的製程 中’甚至可能會造成金屬導線無法電性祕至接觸窗/介 層窗104的問題，進而影響元件之效能，降低製程 【發明内容】 、因此，本發明的目的就是提供一種釋放晶圓應力的方 法’可以釋放晶圓上之高應力膜層的應力。 、本發明的再—目的是提供—種釋放晶®應力的方法， 了避免晶圓在微影製程中因晶圓麵曲而產生對不準的問 1277126 12336twf.doc/006 本發明提出一種釋放晶圓應力的方法，此方法係首先 提供一晶圓，且晶圓上至少已形成有介電層覆蓋於其上。 而且，晶圓具有一第一區域及一第二區域。其中至少在第 一區域内之介電層上未配置有電路。接著在第一區域内之 介電層中形成開口。然後再於介電層上形成材料層，其中 此材料層的材質包括介電材料或是金屬材料。此時，材料 層會在對應於開口的表面上形成P陷區境。此凹陷區域可 釋放材料層所承受之應力，進而降低其施予晶圓的應力。 本發明還提出一種釋放晶圓應力的方法，此方法係首 先提供一晶圓，且晶圓上至少已形成有介電層覆蓋於其 上。而且，此晶圓具有第一區域及第二區域。其中至少在 第一區域内之介電層上未配置電路。 接著在介電層上形成材料層，其中此材料層的材質包 括介電材料或是金屬材料，再於第一區域内的材料層中形 或多」缸開口。此些開口即可吸收材料層所承受之應力，進 而降低其施予晶圓的應力。 由上述可知，由於本發明藉由使高應力膜層（材料層） 成為不連續平坦且具有高低差的結構，因此能夠釋放高應 力膜層所產生的應力以避免晶圓翹曲，進而防止微影製程 中之的光阻產生對不準的問題。而且，由於本發明並未增 加製程之光罩數，因此亦不會增加製程之複雜度。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳之實施例，並配合所附圖式，作詳細 說明如下。 1277126 12336twf.doc/006 【實施方式】 第2A圖至第2C圖係繪示本發明一較佳實施例的一 種釋，晶圓應力的方法之流程剖面示意圖，其係以應用於 一金屬内連線製程進行說明，且為求簡化起見，並避免造 成本發明不必要之限制，係於下_製 及其相對_咖。 钱丨刀稱什 …首先明參照第2A圖，晶圓200上至少已形成有介 電層f8。其中，介電層期的材質例如是氧化梦、氮化 石夕或是—般所常使㈣低介電材料，其形成方法依材質的 不同，例如可以是化學氣相沈積法或是旋塗法。此外，晶 ^ 200上具有區域202及區域204,其中區域2〇2内例如 是形成有半導體元件（未繪^)，其例如是預定形成晶片 (die)的區域。而且，至少在區域綱内之介電層薦 上未配置有任何電路，其例如是晶圓切割道。 接著，請參照第2B圖，於區域202内之介電層208 中形成多個開口 210，並同時在區域204内的介電層208 中形成多個開口 212。其中，開口 210與開口 212 ^形成 方法例如是微影及蝕刻製程。然後在開口 21〇中填入材料 層214。其中，材料層214的材質例如是金屬材料或是其 他的導電材料，對於金屬内連線製程的應用而言，此材^ 層214可為介層窗插塞’其材質例如是鶴或銅。 接著，請參照第2C圖，接著在介電層208上形成材 料層216，其中材料層216的材質例如是介電材料或是金 屬材料，且因製程的因素而具有高應力。特別的是，由於 1277碰μ. •doc/006 在區域204内的開口 212中並未填有材料層214，园此覆 蔞於開口 2丨2上的材料層2丨6會在對應於開口 212處產矣 一凹陷區域218 ’使得材料層216產生一不平坦之表面。 上述之釋放晶圓應力的方法係在未配置有電路的區域 204内形成多個開口 212,使得沈積於其上的材料層216 之表面具有凹陷區域218，而不再是一個連續平坦的表 面。並藉由凹陷區域218來釋放材料層216所產生的高應 力，從而避免晶圓產生翹曲。因此，後續的微影蝕刻製程 不會因為晶圓趣曲而產生對不準的問題。 而且，開口 212可與半導體製程中所需之開口 210於 同一微影蝕刻步驟完成，所以本發明所需之光罩數係與習 知製耘所需之光罩數相同。因此，本發明係可在不增加製 程複雜度的前提下，達成上述釋放高應力膜層之應力以 免晶圓龜曲的目的。 此外，在本發明的另一實施例中，則是以不同於上述 實施例之步驟來達到相同的功效。以下將以文字配合圖 示，對此實施例加以詳細說明。同樣的，為求簡化起^二 並避免造成本發明不必要之限制，係於下述的製程中 部分構件及其相職的說明。而且，以下實麵之 的元件標號與上述實施例相同者，其#質與形成 ^比 相似，上述實施例中所作之說明，以下將不再贅述。/白 第3Α圖至第3D圖係繪示本發明之另_較伟 的-種釋放晶圓應力的方法之流程剖面示意圖^ 參照第3Α圖，在晶圓上至少已形成有介電層細明 1277126 12336twf.doc/0〇6 此外’晶圓200具有區域202及區域204，區域202内例 如是形成有半導體元件（未繪示），其例如是預定形成晶 片（die)的區域。而且，至少在區域204内之介電層208 上未配置有任何電路，其例如是晶圓切割道。 接著，請參照第3B圖，在區域202内之介電層208 中形成多個開口 210,然後在開口 210中填入材料層214。 其中’材料層214的材質例如是金屬材料或是其他的導電 材料，對於金屬内連線製程的應用而言，此材料層214可 為介層窗插塞，其材質例如是鎢或銅。 接著’請參照第3C圖，在介電層208上形成材料層 216同時覆蓋整個晶圓2〇〇，其中材料層216的材質例如 是介電材料或是金屬材料。請參照第3D圖，於區域2〇4 内的材料層216中形成多個開口 218a，使得原為一平坦 之膜層的材料層216被圖案化。其中，開口 218a的形成 方法例如是微影及蝕刻製程。 本實施例雖與上一實施例之步驟流程不相同，但其仍 是藉由嚷壞材料層216之連續性，及终變其表面之平坦 性’以降低材料層216上的應力，因此同樣能夠達成避免 材料層216之面應力造成整個晶圓2〇〇翹曲以及後續微影 蝕刻製程對不準的問題。 、 在第一實施例中，開口 212係暴露出介電層2〇8下方 的膜層（圖式中為晶圓200)而形成貫孔，然而開口 212亦 可以是未暴露出介電層208下方的膜層而形成凹槽。同樣 的第二實施例中的開口 218a可為貫孔亦可為凹槽。 1277126 12336twf.doc/006 而且’於上述二較佳實施例中，雖然是以金屬内連線 製程作說明，然而本發明並不限定於此，本發明亦可以應 用於記憶體元件的位元線製程或是其他半導體元件的製程 中，只要是在晶圓上形成高應力膜層的場合，如本發明所 述的釋放其應力，就包含於本發明的技術特徵中。 由上述可得知，由於本發明藉由使高應力膜層成為不 連續平坦且具有高低差的結構，因此能夠釋放高應力膜層 所產生的應力以避免晶圓魅曲，進而防止微影製程中之的 光阻產生對不準的問題。 而且’由於本發明並未增加製程之光罩數，因此亦不 會增加製程之複雜度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限疋本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1A圖至第1C圖係繪示習知金屬内連線製程的流 程剖面示意圖。 第2A圖至第2C圖係繪示本發明一較佳實施例的一 種釋放晶圓應力的方法之流程剖面示意圖。 第3A圖至第3D圖係繪式本發明之另一較佳實施例 的一種釋放晶圓應力的方法之流程剖面示意圖。 【主要元件符號說明】 100、200 :晶圓 11 1277126 12336twf.doc/006 104 ··接觸窗 102、106、208、216 :介電層 108 :圖案化之光阻層 110、210、212 :開口 202、204 :區域 214 :材料層 218 :凹陷區域1277126 12336twf.doc/006 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor process, and more particularly to a method of releasing wafer stress. [Prior Art] Since today's semiconductor components are built on single-crystal silicon wafers, the wafer diameter has evolved from the early 4吋, 5吋, 6吋 to the present day for mass production and reduced manufacturing costs. 8吋 and 12吋, enabling more wafers to be produced simultaneously on a single wafer. In many semiconductor processes, a continuous film layer is deposited on the entire wafer circle and then a microlithographic process is used to form the desired patterned film layer. Taking a metal interconnect process as an example, after forming a dielectric layer on a wafer, the dielectric layer is patterned to form a via opening or a trench, and then the metal is filled in the via opening or the trench. material. However, when the deposited film layer is subjected to high stress due to a chemical (for example, chemical mechanical polishing), the high stress film layer will cause the entire wafer to produce a curvature, and the Weiqu phenomenon will be Subsequent processes have an impact. The first 1A to the ic diagrams show the flow diagram of the conventional metal interconnect process. First, referring to FIG. 1A, the wafer 100 has been shaped into the 'L1 layer 102' and a plurality of contacts = two solids 104 have been formed on the dielectric layer 102. Then, the entire wafer 100 is formed on the wafer 100. The electrical layer 106 is just above the dielectric layer 102 and the contact/via. The wafer 100 is in a distorted state due to the high stress of the dielectric layer. Next, referring to FIG. 1B, a lithography process is performed to form a patterned photoresist layer 1 (10) on the dielectric layer 1277126 12336 twf.doc/006 106. At this time, the patterned photoresist layer 108 exposes a predetermined location of the dielectric layer 106 to form a trench, that is, a predetermined arrangement position of the metal wires. Next, referring to FIG. 1C, an etching process is performed to remove the exposed dielectric layer 106 to form an opening and closing, and the dielectric layer 1〇6 is no longer a continuous film. The opening 11 形成 formed by the layer and the portion of the dielectric which is removed by a wide band can release the stress it is subjected to. Therefore, the dielectric layer 1〇6 is restored to the original unwarped shape after the etching process. However, the patterned photoresist layer 108 is formed on the dielectric layer 106 in the warped state, and in the process of forming the opening 11 ,, since the dielectric layer ι 6 will return to the original shape, After the circle is restored to the unwarped state, the position of the opening 110 is offset to cause a misalignment problem with the contact window/via window. Moreover, the above-mentioned problem of inaccuracy is gradually increasing from the center of the warp to the periphery. For larger wafers, this problem is more serious. For the peripheral position of the warped wafer, it is formed later. In the process of metal wires, it may even cause the problem that the metal wires cannot be electrically connected to the contact window/via window 104, thereby affecting the performance of the components and reducing the process. [Invention] Therefore, the object of the present invention is to provide a release. The method of wafer stress 'can release the stress of the high stress film layer on the wafer. Further, the object of the present invention is to provide a method for releasing crystal stress, which avoids the wafer from being inaccurate due to wafer curvature in the lithography process. 1277126 12336 twf.doc/006 The present invention proposes a release A method of wafer stress, which first provides a wafer on which at least a dielectric layer has been formed. Moreover, the wafer has a first area and a second area. At least the circuit is not disposed on the dielectric layer in the first region. An opening is then formed in the dielectric layer in the first region. A layer of material is then formed on the dielectric layer, wherein the material of the material layer comprises a dielectric material or a metal material. At this time, the material layer forms a P-trap region on the surface corresponding to the opening. This recessed area releases the stresses that the material layer is subjected to, thereby reducing the stress applied to the wafer. The present invention also provides a method of releasing wafer stress by first providing a wafer with at least a dielectric layer formed thereon overlying the wafer. Moreover, the wafer has a first region and a second region. At least the circuit is not disposed on the dielectric layer in the first region. A layer of material is then formed on the dielectric layer, wherein the material of the material layer comprises a dielectric material or a metal material, and a plurality of cylinder openings are formed in the material layer in the first region. These openings absorb the stresses that the material layer is subjected to, thereby reducing the stress applied to the wafer. As apparent from the above, since the present invention has a structure in which the high stress film layer (material layer) is discontinuously flat and has a height difference, the stress generated by the high stress film layer can be released to avoid wafer warpage, thereby preventing micro The photoresist in the shadow process creates a problem of inaccuracy. Moreover, since the present invention does not increase the number of masks of the process, it does not increase the complexity of the process. The above and other objects, features, and advantages of the present invention will become more apparent from the understanding of the appended claims appended claims 1277126 12336twf.doc/006 [Embodiment] FIG. 2A to FIG. 2C are schematic cross-sectional views showing a method for explaining wafer stress according to a preferred embodiment of the present invention, which is applied to a metal interconnect. The line process is described, and for the sake of simplicity, and to avoid unnecessary limitations of the present invention, the system is based on the following. The money knives are said to have first formed a dielectric layer f8 on the wafer 200 with reference to FIG. 2A. The material of the dielectric layer is, for example, an oxidized dream, a nitriding stone or a (four) low dielectric material, and the forming method is different depending on the material, for example, chemical vapor deposition or spin coating. . Further, the crystal 200 has a region 202 and a region 204 in which, for example, a semiconductor element (not shown) is formed in the region 2?, which is, for example, a region where a die is to be formed. Moreover, at least the dielectric layer within the region is not provided with any circuitry, such as a wafer scribe. Next, referring to FIG. 2B, a plurality of openings 210 are formed in the dielectric layer 208 in the region 202, and a plurality of openings 212 are formed in the dielectric layer 208 in the region 204 at the same time. The forming method of the opening 210 and the opening 212 is, for example, a lithography and etching process. A material layer 214 is then filled in the opening 21A. The material layer 214 is made of a metal material or other conductive material. For the metal interconnect process, the material layer 214 can be a via plug. The material is, for example, a crane or copper. Next, referring to FIG. 2C, a material layer 216 is formed on the dielectric layer 208, wherein the material layer 216 is made of, for example, a dielectric material or a metal material, and has high stress due to process factors. In particular, since the 1277 touches μ. •doc/006, the opening 212 in the area 204 is not filled with the material layer 214, and the material layer 2丨6 covering the opening 2丨2 corresponds to the opening. The depression region 218' at 212 causes the material layer 216 to produce an uneven surface. The above method of releasing wafer stress is to form a plurality of openings 212 in regions 204 where no circuitry is disposed such that the surface of material layer 216 deposited thereon has recessed regions 218 instead of a continuous flat surface. The high stress generated by the material layer 216 is released by the recessed regions 218 to avoid warpage of the wafer. Therefore, the subsequent lithography process will not cause problems due to the interestingness of the wafer. Moreover, the opening 212 can be completed in the same lithographic etching step as the opening 210 required in the semiconductor process, so the number of masks required in the present invention is the same as the number of masks required for conventional fabrication. Therefore, the present invention can achieve the above-mentioned stress of releasing the high stress film layer without the problem of process complexity, thereby avoiding the purpose of wafer torment. Further, in another embodiment of the present invention, the same effects are achieved in steps different from those of the above embodiments. This embodiment will be described in detail below with reference to the text. Similarly, for the sake of simplicity and avoidance of unnecessary limitations of the invention, some of the components and their descriptions are described in the processes described below. Further, the following element numbers are the same as those of the above embodiment, and the quality of the following is similar to the formation ratio. The description of the above embodiments will not be repeated below. /White 3D to 3D are schematic flow diagrams of a method for releasing wafer stress in the present invention. Referring to FIG. 3, at least a dielectric layer is formed on the wafer. Further, the wafer 200 has a region 202 and a region 204. For example, a semiconductor element (not shown) is formed in the region 202, which is, for example, a region where a die is to be formed. Moreover, at least the dielectric layer 208 within the region 204 is not provided with any circuitry, such as a wafer scribe. Next, referring to FIG. 3B, a plurality of openings 210 are formed in the dielectric layer 208 in the region 202, and then the material layer 214 is filled in the opening 210. The material layer 214 is made of a metal material or other conductive material. For the metal interconnect process, the material layer 214 can be a via plug, and the material thereof is, for example, tungsten or copper. Next, please refer to FIG. 3C to form a material layer 216 on the dielectric layer 208 while covering the entire wafer 2, wherein the material layer 216 is made of a dielectric material or a metal material. Referring to Figure 3D, a plurality of openings 218a are formed in material layer 216 in region 2〇4 such that material layer 216, which was originally a flat film layer, is patterned. The forming method of the opening 218a is, for example, a lithography and etching process. Although this embodiment is different from the procedure of the previous embodiment, it still reduces the stress on the material layer 216 by reducing the continuity of the material layer 216 and the flatness of the surface. It is possible to avoid the problem that the surface stress of the material layer 216 is avoided, causing the entire wafer 2 warpage and the subsequent lithography process to be inaccurate. In the first embodiment, the opening 212 exposes the film layer under the dielectric layer 2〇8 (the wafer 200 in the drawing) to form a through hole, but the opening 212 may also be the unexposed dielectric layer 208. A groove is formed by the underlying film layer. The opening 218a in the same second embodiment may be a through hole or a groove. 1277126 12336twf.doc/006 and 'in the above two preferred embodiments, although the metal interconnect process is described, the present invention is not limited thereto, and the present invention can also be applied to the bit line of the memory element. In the process of the process or other semiconductor device, as long as the high stress film layer is formed on the wafer, the stress released as described in the present invention is included in the technical features of the present invention. As can be seen from the above, since the present invention has a structure in which the high stress film layer is discontinuously flat and has a height difference, the stress generated by the high stress film layer can be released to avoid wafer distortion, thereby preventing the lithography process. The photoresist in the middle produces a problem of inaccuracy. Moreover, since the present invention does not increase the number of masks of the process, it does not increase the complexity of the process. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and it is to be understood that those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1C are schematic cross-sectional views showing a conventional metal interconnect process. 2A to 2C are schematic cross-sectional views showing a flow of a method for releasing wafer stress according to a preferred embodiment of the present invention. 3A through 3D are schematic cross-sectional views showing a flow of a method of releasing wafer stress in accordance with another preferred embodiment of the present invention. [Description of main component symbols] 100, 200: Wafer 11 1277126 12336twf.doc/006 104 · Contact windows 102, 106, 208, 216: Dielectric layer 108: Patterned photoresist layer 110, 210, 212: Opening 202, 204: region 214: material layer 218: recessed region
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