JPS63258020A - Formation of element isolation pattern - Google Patents
Formation of element isolation patternInfo
- Publication number
- JPS63258020A JPS63258020A JP9102687A JP9102687A JPS63258020A JP S63258020 A JPS63258020 A JP S63258020A JP 9102687 A JP9102687 A JP 9102687A JP 9102687 A JP9102687 A JP 9102687A JP S63258020 A JPS63258020 A JP S63258020A
- Authority
- JP
- Japan
- Prior art keywords
- film
- mask
- pattern
- groove
- element isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 22
- 230000015572 biosynthetic process Effects 0.000 title 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 13
- 238000001459 lithography Methods 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229960000583 acetic acid Drugs 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012362 glacial acetic acid Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体デバイスにおける素子分離パターンの形
成方法に関し、特にリソグラフィの解像度以上の微細な
素子分離パターンを形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming an element isolation pattern in a semiconductor device, and particularly to a method for forming an element isolation pattern finer than the resolution of lithography.
シリコンデバイスの素子分離技術として、近年誘電体分
離が盛んに行われている。最も一般的な方法は、シリコ
ン基板に溝を掘り込み、その溝の側面をシリコン酸化膜
で覆い、更に残った空間を多結晶シリコン等で埋め込み
、表面を平坦化するものである。Dielectric isolation has been actively used as an element isolation technology for silicon devices in recent years. The most common method is to dig a trench in a silicon substrate, cover the sides of the trench with a silicon oxide film, and then fill the remaining space with polycrystalline silicon or the like to flatten the surface.
このような構造の素子分離パターンを形成するには、通
常シリコン基板表面に熱酸化でシリコン酸化膜を被覆し
、その上にフォトレジストパターンを形成し、このフォ
トレジストをマスクとしてシリコン酸化膜を選択的にエ
ツチングし、更にシリコン酸化膜をマスクとしてシリコ
ン基板を選択的にエツチングし、シリコンの溝を形成す
る方法が用いられている。To form an element isolation pattern with such a structure, a silicon oxide film is usually coated on the surface of a silicon substrate by thermal oxidation, a photoresist pattern is formed on it, and the silicon oxide film is selected using this photoresist as a mask. A method is used in which silicon grooves are formed by selectively etching the silicon substrate using a silicon oxide film as a mask.
ところで、近年における半導体デバイスの高集積比が進
むにつれて素子パターンの微細化への要求が厳しくなり
、同時に素子分離幅の縮小への要求゛も厳しくなってき
ている。Incidentally, as the integration ratio of semiconductor devices has increased in recent years, the demand for miniaturization of element patterns has become stricter, and at the same time, the demand for reduction of element isolation width has also become stricter.
しかしながら、上述した従来の素子分離パターン形成方
法においては、素子分離幅はフォトレジストパターン幅
によって決定されており、現在量産ラインで主流となっ
ている光露光技術では、最小線幅０．８μｍが解像限界
である。このため、従来の素子分離パターンの形成方法
では、この寸法以下の素子分離幅を得ることは難しく、
上記した素子分離幅の縮小への要求を充分溝たすまでに
は到っていない。However, in the conventional device isolation pattern forming method described above, the device isolation width is determined by the photoresist pattern width, and with the light exposure technology currently mainstream on mass production lines, the minimum line width is 0.8 μm. This is the image limit. Therefore, with conventional methods of forming element isolation patterns, it is difficult to obtain element isolation widths smaller than this dimension.
It has not yet been possible to sufficiently satisfy the above-mentioned demand for reduction in element isolation width.
本発明はりソグラフィの解像限界による制約を受けるこ
とのない微細な素子分離幅が得られる素子分離パターン
の形成方法を提供することを目的としている。It is an object of the present invention to provide a method for forming an element isolation pattern that allows a fine element isolation width to be obtained without being constrained by the resolution limit of lithography.
本発明の素子分離パターンの形成方法は、シリコン基板
上に下地膜を形成する工程と、この上に所要パターンの
溝パターン膜を形成する工程と、この上に第１マスク膜
を形成しこれを異方性エツチングにより前記溝パターン
膜の側壁にのみ残す工程と、前記溝パターン膜を除去す
る工程と、残された前記第１マスク膜上に第２マスク膜
を形成しかつ第１マスク膜が露呈されるまで第２マスク
膜をエツチングする工程と、第１マスク膜を除去する工
程と、前記第２マスクをマスクとして前記下地膜を選択
エツチングする工程と、少なくとも前記下地膜をマスク
にしてシリコン基板をエツチングして溝を形成する工程
を含んでいる。The method for forming an element isolation pattern of the present invention includes a step of forming a base film on a silicon substrate, a step of forming a groove pattern film of a desired pattern on this, and a step of forming a first mask film on this. a step of leaving only the sidewalls of the groove pattern film by anisotropic etching, a step of removing the groove pattern film, and a step of forming a second mask film on the remaining first mask film and removing the first mask film. a step of etching the second mask film until it is exposed; a step of removing the first mask film; a step of selectively etching the base film using the second mask as a mask; and a step of selectively etching the base film using at least the base film as a mask. It includes the step of etching the substrate to form a groove.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）乃至（ｉ）は本発明の一実施例を製造工程
順に示す縦断面図、第２図（ａ）、（ｂ）はその製造工
程途中における一部の平面図である。FIGS. 1(a) to 1(i) are longitudinal sectional views showing an embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) and 2(b) are plan views of a part in the middle of the manufacturing process.
先ず、第１図（ａ）のように、シリコン基板１上に熱酸
化法を用いて厚さ１．０μｍの第１のシリコン酸化膜２
を形成し、次にＣＶＤ法により厚さ０．２μｍのシリコ
ン窒化膜３を形成する。これらの膜２．３は下地膜とし
て構成される。更に、この上の素子領域となる部分に溝
パターン膜としての厚さ１．０μｍの多結晶シリコンパ
ターン４を常法により選択的に形成する。この時の平面
状態を第２図（ａ）に示す。First, as shown in FIG. 1(a), a first silicon oxide film 2 with a thickness of 1.0 μm is formed on a silicon substrate 1 using a thermal oxidation method.
Then, a silicon nitride film 3 with a thickness of 0.2 μm is formed by CVD. These films 2.3 are configured as base films. Furthermore, a polycrystalline silicon pattern 4 having a thickness of 1.0 μm as a groove pattern film is selectively formed on the portion that will become the element region by a conventional method. The planar state at this time is shown in FIG. 2(a).
次に、第１図（ｂ）のように、第１マスク膜として厚さ
０．５μｍの第２のシリコン酸化膜５をＣＶＤ法により
形成する。その後、ＣＦ、とＨ２ガスを用いたりアクテ
ィブイオンエツチング法により、前記第２のシリコン酸
化膜５の異方性エツチングを行い、第１図（ｃ）のよう
に、多結晶シリコンパターン４の側壁部のみに第２のシ
リコン酸化膜５を残す。Next, as shown in FIG. 1(b), a second silicon oxide film 5 having a thickness of 0.5 μm is formed as a first mask film by the CVD method. Thereafter, the second silicon oxide film 5 is anisotropically etched using CF and H2 gas or by active ion etching, and the sidewalls of the polycrystalline silicon pattern 4 are etched as shown in FIG. Only the second silicon oxide film 5 is left.
更に、弗酸、硝酸、沃素人氷酢酸の混合水溶液に浸漬す
ることにより、第１図（ｄ）のよ゛うに、溝パターン膜
としての多結晶シリコン４のみを除去する。Further, by immersing it in a mixed aqueous solution of hydrofluoric acid, nitric acid, and iodine glacial acetic acid, only the polycrystalline silicon 4 as the groove pattern film is removed, as shown in FIG. 1(d).
続いて、第１図（ｅ）のように、第２マスク膜としてフ
ォトレジスト（製品名、０ＦＰＲ８００：東京応化製）
６を回転塗布し、約１μｍの厚さに形成する。その後、
０□プラズマを用いてフォトレジスト６の表面を０．３
μｍの厚さだけ除去すると、第１図（ｆ）のように、前
記第２のシリコン酸化膜５表面が露出する。Subsequently, as shown in FIG. 1(e), a photoresist (product name, 0FPR800: manufactured by Tokyo Ohka) was applied as a second mask film.
6 is coated by spin coating to form a thickness of approximately 1 μm. after that,
0□ Using plasma, the surface of photoresist 6 is coated with 0.3
When a thickness of μm is removed, the surface of the second silicon oxide film 5 is exposed as shown in FIG. 1(f).
更に、弗酸溶液に浸漬することにより、第１図（ｇ）の
ように、第１マスク膜としての第２のシリコン酸化膜５
だけを除去する。Furthermore, by immersing it in a hydrofluoric acid solution, a second silicon oxide film 5 as a first mask film is formed as shown in FIG. 1(g).
Remove only.
残ったフォトレジスト６をマスクとして、ＣＦ４とＨ２
ガスを用いたりアクティブイオンエツチング法により、
第１図（ｈ）のように、下地膜としての前記シリコン窒
化膜３及び第１のシリコン酸化膜２を選択的に異方性エ
ツチングする。Using the remaining photoresist 6 as a mask, CF4 and H2
By using gas or active ion etching method,
As shown in FIG. 1(h), the silicon nitride film 3 and the first silicon oxide film 2 as the base film are selectively anisotropically etched.
しかる上で、残されたシリコン窒化膜３．第１のシリコ
ン酸化膜をマスクとして、ＣＢｒＦ、ガスを用いたりア
クティブイオンエツチング法によってシリコン基板１を
選択的に異方性エツチングし、第１図（ｉ）のように深
さ２μｍのシリコン溝７を形成する。このときの平面状
態を第２図（ｂ）に示す。また、このとき、フォトレジ
スト６は除去してもしなくても良い。After that, the remaining silicon nitride film 3. Using the first silicon oxide film as a mask, the silicon substrate 1 is selectively anisotropically etched using CBrF, gas, or active ion etching to form a silicon groove 7 with a depth of 2 μm as shown in FIG. 1(i). form. The planar state at this time is shown in FIG. 2(b). Further, at this time, the photoresist 6 may or may not be removed.
したがって、この方法によればシリコン溝７の幅寸法は
、第２のシリコン酸化膜５の膜厚に略等しい寸法となり
、量産ラインのりソグラフィ技術ではその解像限界によ
って実現が困難な０．５μｍ更にこれ以下の微細な素子
分離用としてのシリコン溝を形成できる。Therefore, according to this method, the width of the silicon groove 7 is approximately equal to the thickness of the second silicon oxide film 5, and the width is 0.5 μm, which is difficult to achieve in mass production line lithography technology due to its resolution limit. It is possible to form silicon grooves for element isolation that are smaller than this.
なお、素子分離幅は、第１マスク膜としての第２のシリ
コン酸化膜厚を制御することでコントロールできること
はいうまでもなく、例えば０．３μｍの素子分離幅を得
るためには第２のシリコン酸化膜５の膜厚を０．３μｍ
にすればよい。It goes without saying that the element isolation width can be controlled by controlling the thickness of the second silicon oxide film as the first mask film. For example, in order to obtain an element isolation width of 0.3 μm, The thickness of the oxide film 5 is 0.3 μm.
Just do it.
第３図＜２１＞及び（ｂ）は本発明方法を実際に適用す
る場合の平面状態を示しており、第１図（ａ）の工程で
第３図（ａ）のように多結晶シリコン４のパターンを配
列形成することにより、第３図（ｂ）に示す格子状のシ
リコン溝７を形成することができる。3<21> and (b) show the planar state when the method of the present invention is actually applied. In the step of FIG. 1(a), as shown in FIG. By arranging and forming the patterns, it is possible to form the lattice-shaped silicon grooves 7 shown in FIG. 3(b).
ここで、下地膜、溝パターン膜、第１マスク膜。Here, a base film, a groove pattern film, and a first mask film.
第２マスク膜は夫々エツチング選択性を有していればよ
く、例えば次の組合わせとしてもよい。It is sufficient that each of the second mask films has etching selectivity, and for example, the following combination may be used.
（１）下地膜（上層）−シリコン窒化膜溝パターン膜
−シリコン酸化膜
第１マスク膜 −多結晶シリコン
第２マスク膜 −フォトレジスト
（２）下地）模（上層）−多結晶シリコン溝パターン１
１タ −シリコン窒化膜第１マスク膜 −シリコン酸
化膜
第２マスク膜 −フォトレジスト
（３）下地膜（上層）−シリコン窒化膜溝パターン膜
−アルミニウム膜
第１マスク膜 −シリコン酸化膜
第２マスク膜 −フォトレジスト
（４）下地膜 −シリコン酸化膜単層溝パターン
膜 −シリコン窒化膜
第１マスク膜 −多結晶シリコン
第２マスク膜 −フォトレジスト
また、フォトレジストに代えて、他の有機樹脂材を用い
てもよい。(1) Base film (upper layer) - silicon nitride film groove pattern film
- Silicon oxide film first mask film - Polycrystalline silicon second mask film - Photoresist (2) base) pattern (upper layer) - Polycrystalline silicon groove pattern 1
1 - Silicon nitride film first mask film - Silicon oxide film second mask film - Photoresist (3) base film (upper layer) - Silicon nitride film trench pattern film
- Aluminum film first mask film - Silicon oxide film second mask film - Photoresist (4) base film - Silicon oxide film single layer groove pattern film - Silicon nitride film first mask film - Polycrystalline silicon second mask film - Photo Resist Also, other organic resin materials may be used instead of photoresist.
以上説明したように本発明は、下地膜上に形成した溝パ
ターン膜と第１マスク膜を利用して、第２マスク膜を所
要の溝パターンに形成し、この第２マスク膜をマスクと
して下地膜をエツチングし、かつこの下地膜をマスクに
してシリコン基板に溝をエツチング形成しているので、
素子分離パターンをリソグラフィの解像限界に制約され
ることがなく形成でき、その幅寸法を第１マスク膜の膜
厚でコントロールすることができるので、素子分離溝を
従来以上に微細化できる効果がある。As explained above, the present invention utilizes a groove pattern film formed on a base film and a first mask film to form a second mask film in a desired groove pattern, and then uses the second mask film as a mask to form a second mask film. Since the base film is etched and the grooves are etched into the silicon substrate using this base film as a mask,
The element isolation pattern can be formed without being restricted by the resolution limit of lithography, and its width can be controlled by the thickness of the first mask film, so the element isolation groove can be made smaller than before. be.
第１図（ａ）乃至第１図（ｉ）は本発明の一実施例を製
造工程順に示す断面図、第２図（ａ）及び（ｂ）は夫々
第１図（ａ）及び第１図（ｉ）の工程における平面図、
第３図（ａ）及び（ｂ）は本発明を適用した一例の広範
囲の平面図である。
１・・・シリコン基板、２・・・第１のシリコン酸化膜
（下地膜）、３・・・シリコン窒化膜（下地膜）、４・
・・多結晶シリコン膜（溝パターン膜）、５・・・第２
のシリコン酸化膜（第１マスク膜）、６・・・フォト第
２図FIGS. 1(a) to 1(i) are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) and (b) are FIGS. 1(a) and 1(i), respectively. A plan view in the step (i),
FIGS. 3(a) and 3(b) are wide plan views of an example to which the present invention is applied. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... First silicon oxide film (base film), 3... Silicon nitride film (base film), 4...
...Polycrystalline silicon film (groove pattern film), 5...Second
Silicon oxide film (first mask film), 6...Photograph 2
Claims (1)
上に所要パターンの溝パターン膜を形成する工程と、こ
の上に第１マスク膜を形成しこれを異方性エッチングに
より前記溝パターン膜の側壁にのみ残す工程と、前記溝
パターン膜を除去する工程と、残された前記第１マスク
膜上に第２マスク膜を形成しかつ第１マスク膜が露呈さ
れるまで第２マスク膜をエッチングする工程と、第１マ
スク膜を除去する工程と、前記第２マスクをマスクとし
て前記下地膜を選択エッチングする工程と、少なくとも
前記下地膜をマスクにしてシリコン基板をエッチングし
て溝を形成する工程を含むことを特徴とする素子分離パ
ターンの形成方法。(1) A step of forming a base film on a silicon substrate, a step of forming a groove pattern film of a desired pattern on this, and a step of forming a first mask film on this and anisotropically etching it to form the groove pattern film. a step of leaving only the groove pattern film on the side wall of the film; a step of removing the groove pattern film; and forming a second mask film on the remaining first mask film and removing the second mask film until the first mask film is exposed. a step of etching the first mask film, a step of selectively etching the base film using the second mask as a mask, and a step of etching the silicon substrate using at least the base film as a mask to form a groove. A method for forming an element isolation pattern, the method comprising the step of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9102687A JPS63258020A (en) | 1987-04-15 | 1987-04-15 | Formation of element isolation pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9102687A JPS63258020A (en) | 1987-04-15 | 1987-04-15 | Formation of element isolation pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63258020A true JPS63258020A (en) | 1988-10-25 |
Family
ID=14015014
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9102687A Pending JPS63258020A (en) | 1987-04-15 | 1987-04-15 | Formation of element isolation pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63258020A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04107949A (en) * | 1990-08-28 | 1992-04-09 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US5595941A (en) * | 1994-06-01 | 1997-01-21 | Mitsubishi Denki Kabushiki Kaisha | Method of forming fine patterns |
| WO2009122764A1 (en) * | 2008-03-31 | 2009-10-08 | 東京エレクトロン株式会社 | Hole forming method, hole forming apparatus, and program |
| JP2010080944A (en) * | 2008-08-25 | 2010-04-08 | Elpida Memory Inc | Method for manufacturing semiconductor device |
-
1987
- 1987-04-15 JP JP9102687A patent/JPS63258020A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04107949A (en) * | 1990-08-28 | 1992-04-09 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US5595941A (en) * | 1994-06-01 | 1997-01-21 | Mitsubishi Denki Kabushiki Kaisha | Method of forming fine patterns |
| US5688723A (en) * | 1994-06-01 | 1997-11-18 | Mitsubishi Denki Kabushiki Kaisha | Method of forming fine patterns |
| US5710066A (en) * | 1994-06-01 | 1998-01-20 | Mitsubishi Denki Kabushiki Kaisha | Method of forming fine patterns |
| WO2009122764A1 (en) * | 2008-03-31 | 2009-10-08 | 東京エレクトロン株式会社 | Hole forming method, hole forming apparatus, and program |
| JP2010080944A (en) * | 2008-08-25 | 2010-04-08 | Elpida Memory Inc | Method for manufacturing semiconductor device |
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