JPH10242275A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture of a semiconductor device which can prevent plug loss or remaining of a poly plug, in the case of forming the poly plug by PSC(Poly Shrinked Contact) method. SOLUTION: A contact hole 24 is formed in the interlayer insulating film 16 on an Si substrate 10, and here an Si film 26 is deposited to fill the contact hole 24, and it is etched back to form a poly plug 28 fitted with a pad. Next, an Si film 36 large in etching rate is made on the topside of the poly plug 28 and the interlayer insulating film 16. After this, the whole face is etched back to expose the poly plug 28. Then, an insulating film is deposited on this upper layer, and a contact hole is made, and the contact hole is provided with a metallic plug.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a method of forming a contact hole in an interlayer insulating film on a Si substrate by using a PSC (Poiy Shrinked Contact) method to form a poly plug.
y Plug, a polycrystalline silicon plug).

[0002]

2. Description of the Related Art Recent LSIs have a gate length of 0.25.
In the μm generation, the ratio of the diameter of the contact hole to the area of the memory cell increases, which makes it difficult to reduce the chip size. This can be solved by reducing the diameter of the contact hole. However, in practice, it is difficult to reduce the diameter of the contact hole because there is a limit in a mask patterning technique for forming the contact hole. Therefore, the PSC (Poiy Shrinked Contact) method is considered promising.

FIGS. 4 and 5 are explanatory views showing an example of a manufacturing process of a semiconductor device using a conventional PSC method. First,
As shown in FIG. 4A, a Si substrate 1 is formed by a known process.
After the transistors 12 and 14 are formed on the insulating film 16, an interlayer insulating film 16 is formed, a first Si film 18 is deposited on the insulating film 16, and then the resist 8 is patterned. Next, as shown in FIG. 4B, the first Si film 18 and the interlayer insulating film 1 are formed.
6 is etched to form a groove 20 for a contact hole.
To form Next, as shown in FIG.
By depositing a film 22, a part of the groove 20 is reduced, and FIG.
As shown in FIG. 5D, the second Si film 22 is etched back to form sidewalls 222 and 224, and the sidewalls 222 and 224 are used as a mask.
As shown in (E), the contact hole 24 is formed by etching the interlayer insulating film 16.

[0004] Next, as shown in FIG.
A film 26 is deposited to fill the contact hole 24, and the third Si film 26 and the first Si film are formed as shown in FIG.
The film 18 is etched back to form a padded poly plug 28 made of polysilicon (polycrystalline silicon, Poly Si). Thereafter, as shown in FIG. 5H, an insulating film 30 is formed on the poly plug 28 and the interlayer insulating film 16.
And a contact hole 32 is formed by anisotropic etching or the like, and a metal plug 34 is provided in the contact hole 32.

[0005]

However, in the above conventional example, as shown in FIGS. 5 (G) and 5 (H), for example, the etching surface of the poly plug 28 is deeper than the etching surface of the interlayer insulating film 16 and the plug loss (Plug) is reduced. Loss)
If the over-etching amount is reduced in order to increase the PL or conversely suppress the plug loss PL, a Poly residue remains on the upper surface of the interlayer insulating film 16 due to the problem of uniformity of the etching apparatus. Here, as a method of etching, there is a technique of confirming the end point of the etching by checking the light emission of the plasma. However, in the case of etching back the poly plug 28, it is not so effective in suppressing the plug loss. For this reason, when a plug loss occurs, it has an adverse effect on flattening the upper layer and forming a stack contact. For example, poly (Pol
y) The rest causes a short circuit, and conversely, the plug loss
As shown in FIG. 5H, a connection failure of the stack contact is caused. Since a stack contact is indispensable for reducing the memory cell size, improvement has been required. Therefore, an object of the present invention is to provide a semiconductor device manufacturing apparatus capable of preventing plug loss and poly residue when a poly plug is formed by, for example, a PSC method.

[0006]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a contact hole in an interlayer insulating film on a Si substrate; and providing a poly plug in the contact hole. The poly plug is formed so as to have a plug loss, and after forming a Si film on the upper surface of the poly plug and an interlayer insulating film, the Si film is entirely etched back to expose the poly plug. And

In the above-described method of manufacturing a semiconductor device according to the present invention, a Si film is formed on the upper surface of a polyplug formed with plug loss and an interlayer insulating film, and the entire surface is etched back to expose the polyplug. Therefore, connection failure of the stack contact due to plug loss in the poly plug can be eliminated, and the cause of the short circuit can be eliminated without remaining poly.

[0008]

Next, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described. 1 to 3 are explanatory views showing an example of a manufacturing process of a semiconductor device using the PSC method according to the present invention. Elements common to FIGS. 4 and 5 will be described with the same reference numerals.

First, as shown in FIG. 1A, after transistors 12 and 14 are formed on a Si substrate 10 by a known process, an interlayer insulating film 16 made of SiO ₂ is formed. A first Si film 18 is deposited, for example, to a thickness of 350 nm, and then the resist 8 is patterned with, for example, 0.30 μm square. Next, as shown in FIG.
The film 18 and a part of the interlayer insulating film 16 are etched to form a groove 20 for a contact hole. Next, as shown in FIG. 1C, a second Si film 22 is deposited, for example, to a thickness of 150 nm to shrink a part of the groove 20, and as shown in FIG. 1D, the second Si film 22 is formed. 22 is etched back to form sidewalls 222 and 224.

Then, utilizing the etching selectivity of Si forming the sidewalls 222 and 224 and SiO ₂ forming the interlayer insulating film 16, Si is used as a mask and FIG.
As shown in (E), the SiO ₂ of the interlayer insulating film 16 is etched to form a contact hole (Shrinked Contact) 24.
To form Next, as shown in FIG.
A film 26 is deposited to a thickness of, for example, 350 nm to form a contact hole 2
4 is buried, and as shown in FIG.
6 and a mask poly (Mask Po) of the first Si film 18.
ly) to form a padded poly plug 28. At this time, the poly residue of the mask poly completely disappears, and the plug loss is reduced.
The etch-back is controlled at such a timing that a is formed.

Next, as shown in FIG. 2 (H), the impurity concentration of the same film as the interlayer insulating film 16 or a higher impurity concentration than the third Si film 26 is formed on the upper surfaces of the poly plug 28 and the interlayer insulating film 16. The fourth Si film 36 having the increased
D (Chemical Vapor Deposition). Thereafter, as shown in FIG. 3I, the entire surface is etched back by ion etching to expose the poly plug 28. Then, as shown in FIG. 3 (J), an insulating film 30 is laminated on the poly plug 28 and the interlayer insulating film 16, and a contact hole 32 is formed by anisotropic etching or the like. 34 are provided. As described above, a stack contact is formed, the poly plug 28 and the metal plug 34 are connected, and connected to an upper layer wiring (not shown).

As described above, in this embodiment, in the PSC, the mask poly is etched to form the poly plug 28, the oxide film (the fourth Si film 36) is formed on the upper surface by CVD, and the entire surface is etched by ion etching. By backing, etching was performed until the poly plug 28 was completely exposed. For this reason,
Poor connection of the stack contact due to plug loss can be prevented. Also, by performing etching so as to form plug loss at the time of forming the poly plug 28, the poly residue can be reliably removed and the cause of the short circuit can be eliminated. Can be.

The present invention is not limited to the above example, but can be widely applied as a method of manufacturing various semiconductor devices in which plug loss occurs after forming a polyplug.

[0014]

As described above, according to the present invention, Si
When a contact hole was formed in the interlayer insulating film on the substrate and a poly plug was provided in the contact hole, the poly plug was formed in a state having plug loss, and a Si film was formed on the upper surface of the poly plug and the interlayer insulating film. Thereafter, the entire surface of the Si film was etched back to expose the poly plug. For this reason, poor connection of the stack contacts due to plug loss can be prevented. In addition, when the poly plug is formed, by performing etching so as to form a plug loss, the poly residue can be reliably removed, so that the cause of the short circuit can be eliminated.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an example of a manufacturing process of a semiconductor device using a PSC method according to the present invention.

FIG. 2 is an explanatory view showing an example of a manufacturing process of a semiconductor device using the PSC method according to the present invention.

FIG. 3 is an explanatory view showing one example of a manufacturing process of a semiconductor device using the PSC method according to the present invention.

FIG. 4 is an explanatory view showing an example of a manufacturing process of a semiconductor device using a conventional PSC method.

FIG. 5 is an explanatory view showing an example of a manufacturing process of a semiconductor device using a conventional PSC method.

[Explanation of symbols]

Reference numeral 8: resist, 10: Si substrate, 12, 14: transistor, 16: interlayer insulating film, 18: first Si
Film, 20 groove, 22 second Si film, 222, 224
... sidewalls, 24, 32 ... contact holes, 26 ... third Si film, 28 ... poly plugs, 30 ...
... an insulating film, 34 ... a metal plug, 36 ... a fourth Si film.

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a contact hole is formed in an interlayer insulating film on a Si substrate and a poly plug is provided in the contact hole, wherein the poly plug is formed in a state having plug loss. A method of manufacturing a semiconductor device, comprising: forming a Si film on the upper surface of a polyplug and an interlayer insulating film; and etching back the entire Si film to expose the polyplug. 2. The method according to claim 1, wherein the Si film formed on the upper surfaces of the polyplug and the interlayer insulating film has a higher etching rate than the polyplug. 3. The method according to claim 2, wherein the Si film formed on the upper surface of the polyplug and the interlayer insulating film is the same film as the interlayer insulating film. 4. The method according to claim 2, wherein the Si film formed on the upper surfaces of the polyplug and the interlayer insulating film has a higher impurity concentration than the polyplug. 5. An interlayer insulating film is formed on an upper surface of a Si substrate on which a transistor is formed, a first Si film is deposited on the insulating film, and then a resist is patterned to form a first Si film and an interlayer insulating film. A portion is etched to form a groove for a contact hole, and then a second Si film is deposited to reduce a portion of the groove, and the second Si film is etched back to form a sidewall. 2. The method according to claim 1, wherein the contact hole is formed by etching an interlayer insulating film using the sidewall as a mask. 6. After forming the contact hole, a third Si film is deposited to fill the contact hole,
6. The method of manufacturing a semiconductor device according to claim 5, wherein said third Si film and said first Si film are etched back to form a padded poly plug. 7. After forming the poly plug, a fourth Si film having the same impurity concentration as the interlayer insulating film or an etching rate higher than that of the third Si film and having a higher etching rate is formed on the upper surface of the poly plug and the interlayer insulating film. Formed by CVD,
7. The method according to claim 6, wherein the poly plug is exposed by etching back the entire surface. 8. The semiconductor device according to claim 1, wherein an insulating film is further formed on the upper surface of the poly plug and the interlayer insulating film exposed by the entire surface etch back to form a contact hole, and the metal plug is buried. 8. The method for manufacturing a semiconductor device according to claim 7.