1258850 九、發明說明： 【發明所屬之技術領域】 本發明係提供一種覆晶基板，其基板表面具有二絕緣 層’並疋義有晶片連接區與被動元件連接區。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a flip-chip substrate having a substrate having a second insulating layer and having a wafer connection region and a passive component connection region. [Prior Art]
Ik著攜V式電子器材的發展，各種輕、薄、短小的封 裝體不斷地被開發出來，覆晶（flip-chip)球閘陣列(ball gdd array, BGA)封裝體就是其中一例。在覆晶bga封裝體中， 晶粒(die)不再是將接合墊(b〇nding pad)經由打金線卜以 bonding)來連接到封裝基板上，而是反轉過來透過銲料凸塊 (solder bump)或導電聚合物凸塊(c〇nductive p〇iymer bump) 來連接到封裝基板上，因此覆晶BGA封裝體可提升電路密 度及提昇電氣特性。 覆晶接合屬於面型陣列式（areaarray)的接合，因此能 應用於極南密度的構裝。簡單來說，覆晶接合的觀念係先 在晶粒的鮮塾上長成銲錫凸塊，然後再將晶粒或晶片（chip) 置放到封裝基板上並完成接墊對位後，並以回銲(refl〇w)熱 處理配合鋒錫溶融時之表面張力效應使銲錫成球，進而完 1258850 成晶片與覆晶基板之接合。這種方式不僅可突破傳統打線 技術的數目限制，適合多腳數元件封裝，而且電性效能也 因具有較短的内連線(connection path)而大幅提升。 凊茶考第1圖，第1圖為習知覆晶球閘陣列封裝體1〇 的剖面示意圖。覆晶球閘陣列封裝體10，其主要包含有一 覆晶基板(substrate) 12及一晶粒Μ藉由銲料凸塊(s〇lder bump) 32銲接在覆晶基板12的上表面16之電性連接墊 21。其中，覆晶BGA封裝體1〇另包含有複數個表面黏著 墊（surface mount pad) 22、複數個錫球銲墊（solder bau pad) 24分別設在覆晶基板12之上表面16以及下表面is上， 以及二綠漆層（solder mask) 26、28分別覆蓋在電性連接墊 21、表面黏著墊22、錫球銲墊24之外的,上表面16以及下 表面18上，用來做為防銲層。 另外’晶粒14表面亦設有複數個接合塾(bonding pad> 30，且接合墊30的位置係相對應設於覆晶基板12之電性 連接墊21的位置。覆晶BGA封裝體10在晶粒14之接合 墊30與覆晶基板12之電性連接墊21之間設有複數個銲料 凸塊(solder bump) 32形成銲錫接合，用來固定並電性連接 晶粒14。而覆晶基板12與晶粒14之間的空隙可視需要， 1258850 〆主入一底部禮、封層（underfill layer) 34並予以填滿，用以保 護封裝體10免受外界環境的影響，同時消除銲料凸塊32 連接處的應力。 迫覆晶BGA封裝體10組裝完成後，再利用複數個錫銲 球36將覆晶BGA封裝體10裝著在一印刷電路板(pdnt circuit board，PCB)上，使覆晶BGA封裝體1〇與印刷電路 板得以電性連接在一起。 在白知封衣技術中，覆晶基板均係由一大片基板切割名 成。而為提昇各覆晶基板與晶粒連接之品質與可靠度，必 須於每-個覆晶基板與晶粒連接之各電性連接墊上加預鲜 錫。但是在預銲錫印刷製程時，往往因為每—個覆晶基板 上又包含有尺寸大小、分布密度不—㈣性連接塾，例如 Γ當作晶片魏連接裂第1性賴墊以及被動元件 =連祕之第二電㈣㈣，因此在大片基板表面全面 來當作_狀料科，便錢域蓋於板面各 =綠漆層料整的情形， 板遡的現象，使得後續在進行預 ^ 到整板面於複數個晶片連接區進：、’ P,衣程時’將面臨 銲錫印刷製程的品質不易控制，：預銲錫之印刷’造成預 工制進而導致大小球、預銲踢 1258850 量 率:::::連接時_落等現象’進-步導致產品良 1有ϋ於此’ t請人乃_此等缺點及依據乡年從事製 ^該類產品之相關經驗’悉心觀察且研究之，進而提出: 不但可有效降低上述之_，並能大幅提升封裝品 貝及良率。 【發明内容】 因此本發明之主要目的在於提供—種具有不同表⑷ ’曰之覆晶基板，以避免習知覆晶基板缺點。 根據本發明之專·圍中所揭露之覆晶基板，其以 —基板，且基板表面定義有晶片連接區與被 _ ―设數個弟—電性連接塾，設置於晶片連接區内、至,, 弟-電性連接墊，設置於被動元件連接、 開口之第一頌续展举从 圖案41 —弟、、、Β緣層，覆盖於晶片連接區之基板與複數個第 連接墊上，並於開口露出複數第一電性連接墊之上 表面’及一圖案化開口之複數第二絕緣層，覆蓋於被動元 ，連接區之基板與第二電性連接塾上，並於開口露出複數 第二電性連接墊之上表面。 !25885〇 本發明之目的在於担Μ φ 預杯锡（presolder)有良 技# t _ 妁口口貝，以利於和晶片連 接侍以提南封裝品質及良率。 本發明又一目的在於提一舜曰 板本身板翱，而、生士 /、设日日基板，侍以減少因基 ^ 以成預銲錫印刷不良率發生。 本發明再一目的在於提供_舜曰 /曰 捉1、 设日日基板，侍以應用於高 數及微細凸塊間距之覆晶封裝。 【實施方式】 為了使#審查委員能更近_步了解本發明之特徵及 技術内容’請參閱以下有關本發明之詳細說明與附圖。然 而所附圖雜供參考與辅助說_，並非絲對本發明加 以限制者。 請參考第2圖至第4圖，第2圖至第4圖為本發明覆 晶基板100之示意圖。如第2圖所示，本發明覆晶基板1〇〇 包含有一基板110,且基板110定義有晶片連接區12〇以及 被動元件連接區122。本發明係先利用習知之連接墊製程， 以於基板110表面之晶片連接區12〇以及被動元件連接區 1258850 122内’同日年製作出複數個第_電性連接塾⑴以及第二 電性連接墊114，分別用來當作晶片連接墊以及被動元件 =接墊。接著分別塗佈第一絕緣層116以及第二絕緣層118 设孤於基板110之晶片連接區12〇、被動元件連接區m、 第笔〖生連接墊112以及第二電性連接墊114上方，然後 進行圖案化開孔(Patterning)製程，以去除位於連接墊 112 114上方之部分第一絕緣層116以及第二絕緣層u8, 進而露出晶片連接區120内之各連接墊112之上表面，以 形成一具複數開口 124之晶片連接區12〇;並暴露出被動 兀件連接區122之第二電性連接墊114之上表面，以形成 一具複數開口 126之被動元件連接區122，即形成具圖案 化開口之第一絕緣層116與第二絕緣層118。另外，基板 110之下表面亦塗佈有一防銲層13〇並且部分覆蓋在錫球 銲塾134上。 其中，基板110係可為一兩層或多層電路板，第一絕 緣層116可為防銲材料、有機高分子樹脂或環氧樹脂等之 "%材料之其中任一者，例如綠漆(solda mask)、雙順丁少希 酉夂酉&亞胺/二氮陕（Bismaleimide Triazine，BT)、聚亞醯胺 (P〇lyimide，PI)、苯環丁稀(Benzocyclobutene，BCB)、液 日日來合物（LCP)、聚四氟乙稀（p〇iytetrafluoroethylene 10 1258850 PTFE)專材料，而苐_絕緣層118則可為上述材料之其中 任一者。值得注意的是，由於本發明之主要目的是避免習 知基板表面凹凸不平、彎曲板翹或銲錫球之不均勻等現 象，以有效控制預銲錫印刷製程之品質，因此第一絕緣層 116之厚度需咼於弟—絕緣層之厚度，以於進行預銲錫 印刷製程時，設於晶片連接區12〇上之第一絕緣層116能 均勻且一致地與鋼版(metalmask)密接，進而得到一良好之 印刷u口質。也就是說，本發明特意設計不同絕緣層厚度以 有效改善後續預銲錫印刷製程，並解決整板面於複數個晶 片連接區120第一電性連接墊112進行預銲錫印刷時，所 面臨之防銲層凹凸不平致影響預銲錫均勻性不佳的問題。 此外，可在晶片連接區12〇形成第一絕緣層116以及在被 動兀件連接區122形成第二絕緣層118，而第一絕緣層116 以及第二絕緣層118可視產品設計上的需求以及實際製程 上的需要考量而具有相同組成材料或具有不相同組成材 料。 接著，如第3圖所示，利用複數個銲料凸塊226將晶粒 220固定並電性連接於覆晶基板1〇〇上，並注入一底部密 封層222並予以填滿，用以保護覆晶BGA封裝體200免受 外界環境的影響，同時消除銲料凸塊226連接處的應力。 11 1258850 其中銲料凸塊226設置於晶粒22〇表面之連接墊224與覆 晶基板100之第一電性連接墊112之間，並與印刷於該電 性連接墊112上之預紅錫經迴銲(refl〇w)形成銲錫接合。迨 覆晶BGA封裝體200組裝完成後，再利用複數個錫銲球。 228將覆晶BGA封裝體200裝著在一印刷電路板上，使覆 晶BGA封裝體200與印刷電路板得以電性連接在一起。设 另外’為使之後晶粒接著更為緊密，因此本發明根據 力學結構，另外設計於晶片連接區12〇内製作導電柱 鲁 (conductive post)128，如第4圖所示，用以增加預銲錫 (presoldeO與連接墊的接觸面積，因此本發明係於連接 晶粒之連接墊112上形成導電柱(c〇nductive p〇s〇i28，並將 其设置於銲接開口 124區域所暴露之連接墊112之上表面 以增加預銲錫與連接墊112的接著面積提身接合強度^其 中連接墊112、H4以及導電柱128可為銅、鎳、錫又、金、、· 銀、鎳金合金、銅銀合金、或銅錫合金等高導電性之金屬。 练合上述，本發明覆晶基板之結構相較習知技藝至少 包括以下之優點： (1)本叙明之覆晶基板之結構係採用二絕緣層，並使晶片 連接區與被動元件連接區之高度不同，以利於進行銲 12 1258850 錫印刷日t使整個基板板面能夠均'^且一致的與鋼版 (metal mask)緊逸、連接’因此得到良好之印刷品質， 對於高I/O數及細凸塊間距(Bump Pitch)之預鋒錫品 質更穩定且效果佳，進一步提升封裝品質以及良率。 (2 )本發明之復曰曰基板之結構採用中央凸起之電性連接 墊，故可有效增加銲錫與連接墊導體接著部之接觸面 積極穩定性，以大幅提昇預銲錫之均勻度與接著品 質’更進一步提昇回銲之品質並且減少氣泡之產生。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第i圖為習知覆晶球格陣列封裝體1〇的剖面示意圖。 第2圖至第4 W為本發明覆晶基板之示意圖。 13 1258850 【主要元件符號說明】 10 覆晶BGA封裝體 14 晶粒 18 下表面 22 表面黏著墊 26,28 綠漆層（solder mask) 32 焊料凸塊 36 錫鲜球 110 基板 114 第二電性連接墊 118 第二絕緣層 122 被動元件連接區 126 開口 130 防銲層（solder mask) 200 覆晶BGA封裝體 222 底部密封層 226 鲜料凸塊 覆晶基板 上表面 電性連接墊 錫球銲墊 接合墊 底部密封層 覆晶基板 籲 第一電性連接墊 第一絕緣層 晶片連接區 開口 導電柱 錫球鲜塾 晶粒 連接墊 錫鲜球 14Ik has been developing V-type electronic devices, and various light, thin and short package bodies have been continuously developed. One example is a flip-chip ball gdd array (BGA) package. In a flip-chip bga package, the die is no longer connected to the package substrate by bonding the bonding pad (b〇nding pad), but is reversed through the solder bump ( Solder bumps or conductive bumps are connected to the package substrate, so flip-chip BGA packages can increase circuit density and improve electrical characteristics. Flip-chip bonding is a joint of area arrays and can therefore be applied to very dense structures. To put it simply, the concept of flip-chip bonding is to first grow a solder bump on the slab of the die, and then place the die or chip on the package substrate and complete the pad alignment. Reflow (refl〇w) heat treatment combined with the surface tension effect of the front tin melt to make the solder into a ball, and then the 1258850 wafer and the flip chip substrate. This method not only breaks through the limitation of the number of traditional wire bonding technologies, but also is suitable for multi-pin component packaging, and the electrical performance is greatly improved by having a short connection path.凊茶考1, Figure 1 is a schematic cross-sectional view of a conventional flip-chip ballast array package 1〇. The flip chip ballast array package 10 mainly includes a flip-chip substrate 12 and a die, which are soldered to the upper surface 16 of the flip chip substrate 12 by solder bumps 32. Connect the pad 21. The flip-chip BGA package 1 further includes a plurality of surface mount pads 22, and a plurality of solder bau pads 24 are respectively disposed on the upper surface 16 and the lower surface of the flip-chip substrate 12. Is, and two green paint layers 26, 28 covering the upper surface 16 and the lower surface 18 of the electrical connection pad 21, the surface adhesive pad 22, and the solder ball pad 24, respectively, for making For the solder mask. In addition, the surface of the die 14 is also provided with a plurality of bonding pads 30, and the positions of the bonding pads 30 are correspondingly disposed at positions of the electrical connection pads 21 of the flip chip 12. The flip-chip BGA package 10 is A plurality of solder bumps 32 are formed between the bonding pads 30 of the die 14 and the electrical connection pads 21 of the flip chip 12 to form a solder bond for fixing and electrically connecting the die 14. The gap between the substrate 12 and the die 14 can be optionally filled, and the 1258850 is filled into a bottom layer, an underfill layer 34, and filled to protect the package 10 from the external environment while eliminating solder bumps. The stress at the junction of the block 32. After the assembly of the flip-chip BGA package 10 is completed, the flip-chip BGA package 10 is mounted on a printed circuit board (PCB) by using a plurality of solder balls 36. The flip-chip BGA package 1〇 is electrically connected to the printed circuit board. In the white sealing technology, the flip chip substrate is cut by a large substrate, and the connection between the flip chip and the die is improved. Quality and reliability must be on each flip-chip substrate Pre-tin solder is added to each of the electrical connection pads of the granules. However, in the pre-solder printing process, it is often because each of the flip-chip substrates contains a size and a density of distribution, such as Γ as a wafer. Wei connected to the first sexual mat and passive components = the second electric (four) (four) of the secret, so the surface of the large substrate is fully treated as a _-form, and the money field is covered on the surface of the board = green paint layer The phenomenon of slabs makes the subsequent advancement of the entire board into a plurality of wafer connection areas: , 'P, clothing time' will face the quality of the solder printing process is not easy to control,: pre-solder printing 'causes The system then leads to the size of the ball, pre-welding kick 1258850 rate::::: when connected _ falling and other phenomena 'in-step leads to good product 1 ϋ ' 乃 乃 此 此 此 此 此 此 此 此 此 此 此The related experience of this kind of product is carefully observed and studied, and it is proposed that: not only can the above-mentioned _ effectively be reduced, but also the packaged product and the yield can be greatly improved. [The present invention] Therefore, the main object of the present invention is to provide - Species with different tables (4) '曰The flip-chip substrate is used to avoid the disadvantages of the conventional flip-chip substrate. The flip-chip substrate disclosed in the specification of the present invention has a substrate, and the surface of the substrate defines a wafer connection region and a plurality of brothers. - Electrical connection 塾, disposed in the wafer connection area, to, the young-electrical connection pad, disposed in the passive component connection, the opening of the first continuous display from the pattern 41 - brother,, and the edge layer, covering And a plurality of second connection pads on the substrate and the plurality of connection pads of the die connection region, and exposing a plurality of second insulating layers on the upper surface of the plurality of first electrical connection pads and a patterned opening, covering the passive element, the substrate of the connection region The second electrical connection is connected to the upper surface of the plurality of second electrical connection pads. !25885〇 The purpose of the present invention is to ensure that the φ pre-cup has a good technique #t _ 妁 口 口 口, in order to facilitate the connection with the wafer to serve the quality and yield of the package. Another object of the present invention is to provide a slab of the slab itself, and the shovel/day setting substrate is used to reduce the defect rate of the pre-solder printing. A further object of the present invention is to provide a lithographic package for use in high-order and fine bump pitches. [Embodiment] In order to make the # review committee closer to understand the features and technical contents of the present invention, please refer to the following detailed description of the present invention and the accompanying drawings. However, the drawings are to be understood as being limited to the invention and are not intended to limit the invention. Please refer to FIGS. 2 to 4, and FIGS. 2 to 4 are schematic views of the flip-chip substrate 100 of the present invention. As shown in Fig. 2, the flip chip substrate 1A of the present invention comprises a substrate 110, and the substrate 110 defines a wafer connection region 12A and a passive component connection region 122. The invention first utilizes a conventional connection pad process to fabricate a plurality of first electrical connections (1) and a second electrical connection in the wafer connection region 12〇 on the surface of the substrate 110 and the passive component connection region 1258850 122. Pads 114 are used as wafer connection pads and passive components = pads, respectively. Then, the first insulating layer 116 and the second insulating layer 118 are respectively disposed on the wafer connection region 12A of the substrate 110, the passive component connection region m, the first connection pad 112 and the second electrical connection pad 114, Then, a patterning process is performed to remove a portion of the first insulating layer 116 and the second insulating layer u8 over the connection pads 112 114 to expose the upper surface of each of the connection pads 112 in the wafer connection region 120. Forming a die connection region 12 of the plurality of openings 124; and exposing the upper surface of the second electrical connection pad 114 of the passive component connection region 122 to form a passive component connection region 122 having a plurality of openings 126, ie, forming The first insulating layer 116 and the second insulating layer 118 are patterned with openings. In addition, the lower surface of the substrate 110 is also coated with a solder resist layer 13 〇 and partially covered on the solder ball 134. The substrate 110 can be a two-layer or multi-layer circuit board, and the first insulating layer 116 can be any of the materials such as a solder resist material, an organic polymer resin or an epoxy resin, such as green paint. Solda mask), Shuangshun Dingxixi &imimide/Bismaleimide Triazine (BT), P〇lyimide (PI), Benzocyclobutene (BCB), Liquid Day The extract (LCP), polytetrafluoroethylene (p〇iytetrafluoroethylene 10 1258850 PTFE) special material, and the 苐 _ insulating layer 118 can be any of the above materials. It is to be noted that, since the main purpose of the present invention is to avoid the phenomenon that the surface of the substrate is uneven, the curved plate is warped or the solder ball is uneven, and the quality of the pre-solder printing process is effectively controlled, the thickness of the first insulating layer 116 is The thickness of the insulating layer is required for the pre-solder printing process, and the first insulating layer 116 disposed on the wafer connection region 12 is uniformly and uniformly adhered to the metal mask, thereby obtaining a good Printed u mouth quality. That is to say, the present invention deliberately designs different insulating layer thicknesses to effectively improve the subsequent pre-solder printing process, and solves the problem that the whole board faces the pre-solder printing of the first electrical connection pads 112 of the plurality of wafer connection regions 120. The unevenness of the solder layer affects the problem of poor uniformity of the pre-solder. In addition, a first insulating layer 116 may be formed in the wafer connection region 12 and a second insulating layer 118 may be formed in the passive component connection region 122, and the first insulating layer 116 and the second insulating layer 118 may be visually designed and required. The process needs to have the same composition material or have different composition materials. Next, as shown in FIG. 3, the die 220 is fixed and electrically connected to the flip-chip substrate 1 by a plurality of solder bumps 226, and a bottom sealing layer 222 is filled and filled to protect the The crystalline BGA package 200 is protected from the external environment while eliminating stress at the junction of the solder bumps 226. 11 1258850 wherein the solder bumps 226 are disposed between the connection pads 224 on the surface of the die 22 and the first electrical connection pads 112 of the flip chip 100, and the pre-red tin printed on the electrical connection pads 112. Reflow (refl〇w) forms a solder joint.后 After the flip-chip BGA package 200 is assembled, a plurality of solder balls are used. 228 mounts the flip-chip BGA package 200 on a printed circuit board to electrically connect the flip-chip BGA package 200 to the printed circuit board. In order to make the subsequent crystal grains more compact, the present invention further designs a conductive post 128 in the wafer connection region 12〇 according to the mechanical structure, as shown in FIG. 4, to increase the pre- Solder (the contact area of the presoldeO and the connection pad, so the present invention is formed on the connection pad 112 connecting the die to form a conductive post (c〇nductive p〇s〇i28, and is placed in the connection pad exposed by the soldering opening 124 area) The upper surface of 112 is used to increase the bonding strength of the pre-solder and the bonding pad 112. The connecting pads 112, H4 and the conductive pillars 128 may be copper, nickel, tin, gold, silver, nickel alloy, copper. A highly conductive metal such as a silver alloy or a copper-tin alloy. As described above, the structure of the flip-chip substrate of the present invention includes at least the following advantages over the prior art: (1) The structure of the flip-chip substrate of the present invention is two The insulating layer and the height of the connection area of the die and the passive component are different to facilitate the soldering 12 1258850 tin printing day t so that the entire substrate surface can be uniformly and consistently connected with the metal mask. 'because This gives good printing quality, and is more stable and effective for high I/O number and Bump Pitch, and further improves package quality and yield. (2) The retanning of the present invention The structure of the substrate adopts the central protruding electrical connection pad, so that the positive contact stability between the solder and the connecting portion of the connecting pad conductor can be effectively increased, thereby greatly improving the uniformity and the subsequent quality of the pre-solder to further improve the quality of the reflow. The present invention is only a preferred embodiment of the present invention, and the equivalent variations and modifications made by the scope of the present invention should be within the scope of the present invention. FIG. 2 is a schematic cross-sectional view of a conventional flip-chip array package. FIG. 2 to FIG. 4W are schematic diagrams of a flip-chip substrate of the present invention. 13 1258850 [Description of main components] 10 Flip-chip BGA package 14 crystal Grain 18 lower surface 22 surface adhesive pad 26, 28 green powder layer (solder mask) 32 solder bump 36 tin fresh ball 110 substrate 114 second electrical connection pad 118 second insulation layer 122 passive component Bonding area 126 opening 130 solder mask 200 flip chip BGA package 222 bottom sealing layer 226 fresh bump bumping substrate upper surface electrical connection pad solder ball bonding pad bottom sealing layer flip chip substrate An electrical connection pad first insulation layer wafer connection area opening conductive column tin ball fresh 塾 die connection pad tin fresh ball 14