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TWI245386B - Heat-dissipating semiconductor device with a flexible circuit board - Google Patents

Heat-dissipating semiconductor device with a flexible circuit board Download PDF

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Publication number
TWI245386B
TWI245386B TW093140870A TW93140870A TWI245386B TW I245386 B TWI245386 B TW I245386B TW 093140870 A TW093140870 A TW 093140870A TW 93140870 A TW93140870 A TW 93140870A TW I245386 B TWI245386 B TW I245386B
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Taiwan
Prior art keywords
heat
semiconductor device
flexible
board
patent application
Prior art date
Application number
TW093140870A
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English (en)
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TW200623362A (en
Inventor
Shih-Ping Hsu
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Phoenix Prec Technology Corp
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Publication of TW200623362A publication Critical patent/TW200623362A/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

1245386 九、發明說明： 【發明所屬之技術領域】 —種結合有可撓性軟板之散 種散熱封裝件整合有可猝姓护妃 千蛉版衣置，尤指 【先前技術】 之㈣型半導體裝置。 笔子產品縮小化，ρ足a , 單一功处刑…長久以來的發展趨勢，並且以往 行動電話結合數位相機之多功、!7^ 的需求’如 口梦+ 钺之夕功月匕（multiple function)電子 ::，使得隨身型的電子產品不再僅有單一使用功能。為 处^產業之積體電路（lnt啊ed咖uh，ic)係朝向多功 性迠之方向發展。如具有多種功能的積體電路，由 盆得以提供多種不同的功能，而以ic為主體架構，並在 ::輸入/輸出接點上連接不同的被動元件，如電阻、電容或 电感等所組成之群組之一，即可組合成該1(：所提供之 能0 但以封裝完成之1C連接被動元件之方式，通常係先製 作印刷兒路板，再將該Ic及被動元件插裝在印刷電路板 上，而藉由印刷電路板以達成連接。如此一來，則使得整 體的體積變大，而無法達到薄小之目的。 又習知之散熱增益型球柵陣列式（EBGA, Enhanced Bal1 Gnd Array)，如第1圖所示，係在一散熱板li(heat sink) 上宜衣一具有開口 12丨（opening)的基板12，於該基板12 的開口 121内裝置一晶片13(chip)，且該晶片13以銲線14 連接至基板12 ’並且在基板12的表面上植接有複數個錫 5 18106 1245386 球15。 雖然該EBGA結構藉由散熱板u，而 能，伸今玄其扣Ί 9 有问放Λ兵之效 亥基板12之開口 121裝置晶片η 位置可供裝置其它元件 1夕餘的 (active element)，使 之甩谷或氣阻等被動元件 使用需求，而-法 …、次1乍其匕的應用變化。 【發明内容】 鑑於前述習知技術之缺失，本㈣之 =了種結合有可撓性軟板之散熱封I件，俾:係在提 間以格載外接電子元件。 于^ i、配置空 =發明之又—目的，係在提供―種杜 ^板之散熱封裳件，藉以免除配置二性軟板 之Μ發明之次一目的，係在提供-種Μ有問題。 之放熱封裝件，以構建模组化結構，俥：有可撓性軟板 件。 得俾可便於外接電子元 本發明之再一目的，係在提供一 之散，同時得縮小封裝體積 有可繞性軟板 軟板二 =，，:= 至少—可撓性軟板，係接 啟熱封裝件；以及 上，以供承接複數電m亚連接在該散熱封裝件 而該散熱封裝件係包括 之表面，且該封裝，係結 -切體元件’係埋 ：/、有至少-開口 ；至少 衣基板之開口内，並且結合在 】8]〇6 6 1245386 ί熱片的表且該半導體元件係以打線連接至封裝基 I於封Α基板表面植接複數個導電元件。 該可撓性軟板上得接置至少—带 件係如主動元件、砒叙_ M 电子兀件，而该電子元 性軟板提供接置空問，A认 件寺俾可猎由可撓 由該可撓性軟板芦矛配置空間不足的問題。俾藉 :配成夕種不同功能及特性的封裝 γ壬 用效能。 早J徒回日日片的使 再者，該可撓性軟板得進 性軟板貼置在該散熱封裝件之二折使:可挽 上的電子元件得以結合在散熱几性軟板 整體體積。 午上俾可鈿小封裝的 又垓可撓性軟板係包括有複數個 一 連接墊接置至外部電子裝+ 而可藉由該 子裝置，俾可提供變換組裝的導體裝置或電 圍。 早性而可有更大的應用範 【實施方式】 着 以下係藉由特定的目碰+ 式，熟習此技藝之:=Γ例說明本發明之實施方 瞭解本發明之其他優點心兒明書所揭示之内容輕易地 /、他彳支點與功效。本發 的具體實施例加以施行或鹿、了糟由其他不同 可基於不同觀點與鹿：： °兄明書中的各項細節亦 種修部與變更。在不恃離本發明之精神下進行各 以下之實施例係進一牛 V砰細§兄明本發明之觀點，但並 18106 7 1245386 非—以任何觀點限制本發明之範疇。 [第一實施例] 請參閱第2圖，係盔士六nn 軟板Hi% t、..’…、奄月所揭露—種結合有可撓性 孕人扳之放熱.型丰導體裝置 熱封##2 不思囚，主要係包括：一散 …対衣件3,係於—例如金屬 ^ 骞次陶瓦之散熱片31表面結合 封衣基板32,於該封裝基板32且 該開口 321内置入 /、"開口 32卜方； 件33結合在散^ 31^=4件33,並使該半導體元 導體元件33之散執饮:而;以藉由該散熱片31提高半 34rw- κ 、放此，而该半導體元件33係以銲線 34(wire bond)接至封裝基柘 、， 住兮本_ μ 板32，亚以一封裝膠體％覆蓋 任6亥丰V體兀件33及鋥蜱以^ 0> JU AK ^ r 7 ，又於該封裝基板32表面形 成係如錫球（solder ball)、鋥執n 」、 電凸塊之導電元件36 .以及f p pad)、接腳(pin)或導 並電性少—可挽性軟板4，係接置 連接在该放熱封裝件3之封裝基板^上，而 性軟板4係為一軟性的㊉ ^ 接複數電子元件41,==，於該可撓性軟板4得供承 動元件或光學元件等，^子元件41係如主動元件、被 、，、中之主動元件係如光元件或半導 “卜而§亥被動元件係如電阻、電容或電感所組成之群
組0 T 且°亥放鋪裝件3之封裝基板32包括有複數個連接墊 37 ’又該可撓性軟板4表面具有連接墊42 ’其得以銀膠 (silVei lesign)、銲錫（5〇】叫、導電樹脂、八⑶等電性連 4电子兀件41係可透過該可撓性軟板4而電性連接至該散 8 】81〇6 1245386 得有更佳的使用範圍。 [第三實施例] 同請參閱第4圖，係為本發明之另—實施結構剖面干立 =述實施例不同處在於該可撓性軟板 ： 二固=封裝件3之另一表面上，例如可固定在二 ‘ _面，以提升接置於該可撓性軟板4上+# 41之散熱效率， 导版4上包子兀件 合成-許，位^ 板4與散熱封裝件3結 門而；右 體積並可擴充電子元件41的配置空 間而可有較廣之應用範圍。 由上述之貫施結構態樣令，散熱封裝件u 軟板，而可提供配置空間以連接電子丄:件:接置可换性 體元件之使用效妒，… 件，俾以提高半導 ^ _ b亚^供模組化結構以提供變換搭 電子兀件之變換使用的彈性。 又換格載 用以:ΪΓ"4 為本發明之較佳實施例而已’並非 用以限定本發明之實質技術内匕1非 内容係廣義地定義於下述之申請專5明之貫質技術 成之技術實體或方法，若是與 \，任何他人完< 者係完全相同，亦或為同—等效=申範圍所定義 此申請專利範圍中。 句將被視為涵蓋於 【圖式簡單說明】 示意=圖係為習知散熱增益型間球陣列封裝之結構剖面 第2圖係為本發明之具有可 中間板以薛線接至半導體元件的剖面==裝件結構的 18106 10 1245386 第3圖係為本發明之結合有可撓性軟板之 的半導體元件埋設在中間板内並以增層結構連;:::裝件 板的剖面示意圖；以及 可纹性軟 弟4圖係為本發明之結合有可撓性軟板之 的可撓性軟板貼合在半導體裝置一側的剖面十炙伞 【主要元件符號說明】 /、思圖。 11、21散熱板 121 、 221 、 321 開口 14、34 銲線 24 線路增層結構 31 散熱片 32, 絕緣板 33 半導體元件 36 導電元件 39 外部電子裝置 41 電子元件 43 電性連接材 12、22 基板 13、23 晶片 15、25 锡球 3 散熱封裝件 32 封裝基板 321 、 321，開口 35 封裝膠體 38 線路增層結構 4 可撓性軟板 37 、 42 、 42’連接塾 18106 11

Claims (1)

1245386 第93140870號專利申請案 申請專利範圍修正本 1 · 一種結合有可A (94年9月曰 —散熱片r'人板之散熱型半導體裝置，包括: —封裝基板，係結合在該散埶 基板具有至少—開口；…片之表面，且該封舞 至少一半導體元件，#娌讯卢# 内，=結合在該散熱片的表=裝基板之開口 固定於該散熱片上。 Μ可撓性軟板係可彎折 2· ^請專利範圍第μ 散熱片之材質係 衣置，其中，該 3.如申請專利範圍第5陶究其中之-者。 半導體元件係散熱型半導體裝置，其中，該 4 封裝基板表面形咸導H〇nd)連接至封裝基板，並於 ，二可繞性軟板之散熱型半導體裝置，包括： 矣巴緣板，儀牡 具有至少1 〇 · 'σ σ该散熱片之表面，且該絕 至少一半導體元 並且結合在該散仏埋呂又在该絕緣板之開口 至」、—。放熱片的表面；以及 、σ教板，係接置並電性連接該半導 1 】8106(修 1245386 . * 件，以供承接複數個電子元件，該可挽性軟板係可彎折 固定於該散熱片上。 5. 如申凊專利範圍帛4項之散熱型半導體裝置，其中，該 絶緣板及半導體兀件表面形成—線路增層結構，並於線 路增層結構表面形成導電元件。 6. ::請：：範圍第}項或第4項之散熱型半導體裝置， 其中，该半導體元件係為一晶片。 7·=請=範圍第3項或第5項之散熱型半導體裝置, 二’，電元件係為錫球(s〇】der _、銲墊 pad)、接腳（ριη)及導電凸塊其中之一者。 8. 圍第1項之散熱型半導體裝置，其中，該 于裝基板包括有複數個連接墊，且 h性連接材使該可撓二= 接墊接置並電性連接該封裝基板。 9. 如申請專利範圍f 5項之散熱型半導 線路增声紝福勺紅女、— 、置-、中’该 …。構包括有稷數個連接墊，且 有相對應的連接墊，藉由一 1 人板〆、 之連接執垃¥、，+, 电性連接材使該可撓性軟板 ，接墊接置亚電性連接該線路增層結構。 1 0·如申請專利範圍第1或 中mu 月文熱型半導體裝置，其 ^ "T 性軟板復包括複數個#·於η & 墊，拉㈣個叹於另外位置的連接 猎由该連接塾以接置至外部電子裝置。 1 ·如申請專利範圍第1或 中…工 飞項之散熱型半導體裝置，1 中之一者。 ⑨兀件_兀件及光學元件其 】8106(修正本） 2 1245386 12. 如申請專利範圍第11項之散熱型半導體裝置，其中， 該主動元件係為光電元件及半導體元件其中之一者。 13. 如申請專利範圍第11項之散熱型半導體裝置，其中， 該被動元件係為電阻、電容及電感所形成之組合。 3 18106(修正本）
TW093140870A 2004-12-28 2004-12-28 Heat-dissipating semiconductor device with a flexible circuit board TWI245386B (en)

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Application Number Priority Date Filing Date Title
TW093140870A TWI245386B (en) 2004-12-28 2004-12-28 Heat-dissipating semiconductor device with a flexible circuit board

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Application Number Priority Date Filing Date Title
TW093140870A TWI245386B (en) 2004-12-28 2004-12-28 Heat-dissipating semiconductor device with a flexible circuit board

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TWI245386B true TWI245386B (en) 2005-12-11
TW200623362A TW200623362A (en) 2006-07-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447690A (zh) * 2019-08-29 2021-03-05 力成科技股份有限公司 天线置顶的半导体封装结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112447690A (zh) * 2019-08-29 2021-03-05 力成科技股份有限公司 天线置顶的半导体封装结构
CN112447690B (zh) * 2019-08-29 2024-05-14 力成科技股份有限公司 天线置顶的半导体封装结构

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