TWI240329B - Method of forming adjacent holes on a semiconductor substrate - Google Patents

Abstract

A method of forming adjacent holes on a semiconductor substrate is disclosed. The adjacent holes are separated by a fine line structure. The method includes the steps of providing a semiconductor substrate with an insolating layer on the substrate, forming a step-shaped structure, with a first horizontal surface, a second horizontal surface, and a vertical surface, on the surface of the insolating layer, depositing a sacrificial layer with an average thickness, forming a patterned photoresist layer on portions of the first and second horizontal surface, performing an etch-back process to remove the sacrificial layer not covered by the photoresist layer and forming a spacer on the vertical surface, removing the patterned photoresist layer, and using the spacer and the remaining sacrificial layer as a hard mask to remove the insulating layer, thereby forming two adjacent holes.

Description

1240329 Wufa Description of the invention (1) Technical field of the invention ^ Invention, a method of forming a plurality of hole structures on a semiconductor substrate ', especially a method of forming two adjacent and intervening hole structures on a semiconductor substrate. Ί With the use of more and more high-tech technologies in the prior art, the pore structure derived from the semiconducting product is used to define the derived hole structure. Semi-wide, especially in the technology industry, the semiconductor components that are continuously included in the accumulation of light-weight products are also getting smaller and smaller. For example, when you want to make, you can't just design the pattern from the beginning. Among them, the demand for the degree of integration of structures (such as contact holes) is caused by the bad opening. The production of conductors is becoming thinner, thinner, and more and more. Many small wires are made. One light is 5 and the semiconductor is one. Two phases. When the product is operating, the signal is short, and the electricity is short. There are many gold caps with wide technological distances and semi-adjacent holes that need to be imported with more materials. The sub-products cannot be used. Therefore, the problem per unit and half is a line or a complex structure with multiple rows of open conductors. Standard or level. The process of opening a single conductor is also due to the process of opening the shadow rice. The possible causes may be caused by the plane. The plane elements need to be carved in order to make them extremely semi-conductive. Please refer to Figure 1 to Figure 2 to Figure 2. Known on a semiconductor substrate

1240329 V. Description of the invention (2)-10 Schematic diagram of the process of making two adjacent hole structures. The semiconductor substrate i 〇 includes a plurality of gate structures 1 2, 1 4, 16, 18, a protective layer 24 covering the electrodes, and a borophos-phosilicate glass used as an insulating layer. glass (BPSG) layer 20 and undoped silicate glass (USG) layer 22. First, as shown in the figure, a photoresist layer (not shown) is formed on the surface of the USG layer, and then a lithography process is performed, and the photoresist layer is removed above the position where the hole structure is planned to be formed to form a patterned photoresist layer 26 . Next, as shown in FIG. 2, an _ anisotropic etching process, such as a dry-etching process, is performed to remove the USG layer 22 and the BPSG layer that are not covered by the patterned photoresist layer 26. 20 until the surface of the protective layer > '24 to form two adjacent hole structures 28, 30. Finally, as shown in FIG. 3, the patterned photoresist layer 26 is removed to complete the fabrication of the hole structures 28 and 30. In this conventional technique, since the adjacent hole structures 28 and 30 are very close, the USG layer 22 and the BPSG layer 20 sandwiched between the two form a thin line structure 3 2 with a small width, for example, the thin line structure 3 The width of 2 is less than 100 angstroms (A). In this case, when only a single photomask is used to transfer the pattern to the photoresist layer, it is difficult to accurately define the fine line structure on the photoresist layer. The pattern of 2 forms the ideal patterned light p shown in Figure 1 and the layer 2 6 ′ may cause the thin line structure 3 2 position shift, width change or even disappear, which will cause defects in the process and seriously affect subsequent processes and products. Yield. For example, when the thin line structure 3 2 must meet the crossing of the gate 1 4,

1240329

In the condition of the middle gate, 'If the patterned photoresist layer 26 cannot accurately define the position of the line structure 32, the subsequent production of materials on the surface of the thin line structure 32 (such as conductive materials such as polysilicon layers) will also generate positions. The M gates are confusing with the pattern design of the road, such as short circuit, loss of electrical connection, etc. In addition, in this conventional technique, 弁 θ for pattern transfer must have a high thickness, so after development, the patterning is blocked, and 2 6 has a high aspect ratio, resulting in The photoresist layer 26 is likely to collapse in subsequent processes, which is also a great problem for semiconductor processes. See Figures 4 to 5 for details. Figures 4 to 5 are schematic diagrams of the conventional manufacturing process using masks to assist in making adjacent hole structures. The protective layer 60 on a = 54 ^ 56 ^ 58 ^ t ^ ^, and the bpsg layer 62 and the USG layer 64. First, as shown in Aβ, a layer of a nitrogen and silicon compound, a mask layer 66, is deposited on the USG layer 64, and then a photoresist layer is deposited on the surface of the mask layer 66. The mask of ★ Use lithography technology to transfer the pattern to the photoresist layer, forming a ^ ’

化 光阻 层 6 8. Then, as shown in FIG. 5, an etching process is performed to remove the masking layer 66 not covered by the patterned photoresist layer 68, so that the remaining mask 66 has the same pattern as the patterned photoresist layer 68. Then, the resist layer 68 is removed, and an etching process is performed to remove the unmasked layer 6—the light USG layer 64 and the BPSG layer 62, up to the surface of the protective layer 60, and finally, it may be lean. It is necessary to remove or leave the mask layer 6 6 to form two adjacent hole structures 7 2 and a thin line structure 7 4 sandwiched between the two.

1240329 V. Description of the invention (4) In this conventional technique, although the patterned photoresist layer 68 has a high aspect ratio, the photoresist layer may collapse in subsequent processes. However, when the reticle pattern is transferred to the photoresist layer by lithography technology, because the width of the thin line structure 74 pattern is too narrow, it is impossible to define an accurate pattern on the photoresist layer, so that the pattern of the photoresist layer 68 is patterned. Unlike the mask pattern, it will also have a negligible effect on subsequent processes, leading to a reduction in yield. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method capable of accurately transferring a pattern and fabricating two extremely adjacent hole structures, so as to solve the problems of the conventional manufacturing process. According to the patent application scope of the present invention, a method for forming two adjacent hole structures on a semiconductor substrate is disclosed. The two adjacent holes are respectively a first hole structure and a second hole structure. The first and second hole structures They are separated by a thin line structure. The method of the present invention includes the following steps: providing a semiconductor substrate with an insulating layer on the surface, forming a stepped structure on the surface of the insulating layer, the stepped structure comprising a first horizontal step surface, a second horizontal step surface, and A vertical step surface between the first and second horizontal step surfaces, and then a uniform sacrificial layer is deposited on the surface of the insulating layer, covering the first horizontal step surface, the second horizontal step surface, and the vertical step surface, and then forming a pattern Chemical photoresist layer covering the first and second

Page 9 1240329 V. Description of the invention (5) A part of the surface of the horizontal step surface is subjected to an etching process to remove the sacrificial layer not covered by the patterned photoresist layer on the first and second horizontal step surfaces, and A sidewall is formed on the vertical ladder surface, and finally the patterned photoresist layer is removed, and the sidewall and the remaining sacrificial layer are used as a masking layer, and an insulating layer not covered by the masking layer is formed to form The adjacent first hole structure and the second hole structure. Because the present invention performs two photolithography processes (using two patterned photoresist layers for photomask pattern transfer) and a sacrificial layer as a mask layer for etching during pattern transfer, it can effectively make up for the conventional knowledge. In the technology, when the lithography process is used only once, the pattern is distorted because the line width is too small to exceed the exposure limit. And after the second lithography, when the sacrificial layer is etched back, the thickness of the sidewalls formed on the vertical step surface can be easily adjusted using known techniques to achieve the desired minimum size and meet the original circuit design line Wide width, and subsequently use the side wall as a masking layer, when etching the insulating layer, you can also use techniques known to those skilled in the art, such as adjusting the etching ratio, to completely retain the insulating layer covered by the masking layer, so that the original The circuit pattern can be accurately transferred to the semiconductor substrate to form two extremely adjacent hole structures. In order to make your reviewers understand the features and technical contents of the present invention more closely, please refer to the following detailed description and drawings of the present invention. However, the drawings are only for reference and auxiliary explanation, and are not intended to limit the present invention.

Page 10 1240329 V. Description of the invention (6) Please refer to FIG. 6 to FIG. 12 for implementation. FIGS. 6 to 12 are two adjacent hole structures 1 3 0, 1 formed on a semiconductor substrate 100 according to the present invention. 3 2 Process schematic diagram. The semiconductor substrate 100 includes a gate structure 102, 104, 106, 108, and a protective layer i10, a BPSG layer 112, and a USG layer 114 covering the gate structures. Among them, the BPSG layer 112 and the USG layer 114 are used. As the insulating layer on the ferroconductor substrate 100, and each of the gate structures 10, 102, 106, and 08 includes a gate oxide layer, a conductive layer, an insulating layer, a side wall, Drain and source. First, a photoresist is formed on the USG layer 1 1 4 (not shown), and then a photomask and a lithography process are used to transfer the photomask ^ to the photoresist layer to form a patterned photoresist. Layer n6. It is worth noting that the pattern of the patterned photoresist layer 116 is different from the original circuit design, that is, the pattern does not completely define the boundary between two adjacent hole structures 丨 3 〇, 1 2 2, as shown in Figure 6 It is shown that the patterned photoresist layer n 6 defines the position of the hole structure 1 3 0 near the hole structure 1 3 2, but the patterned photoresist layer 1 1 6 does not define the other side of the hole structure i 30 and the hole structure 1 ^ position.叩 Please refer to FIG. 7, an etching process is performed to remove a portion of the USG layer 114 that is not covered by the patterned photoresist layer 116 to form a first-order structure on the surface of the USG layer 11 4, which has a first horizontal step surface n 8 , The second horizontal step surface 1 2 0 higher than the first water step surface 1 1 8 and the vertical step surface 1 2 2 are located at two levels

1240329 V. Description of the invention

The water step surface 118 and the second horizontal step surface 120 have a step height difference. Then, the straight layer 124 covers the surfaces of the first-horizontal step surface " 8: the second horizontal p from the surface 120 and the vertical step surface 122. In a preferred embodiment of the present invention, the thickness of the sacrificial layer 24 is approximately equal to the height difference between the first and second surfaces 116 and 118, that is, the surface of the sacrificial layer 124 covering the first horizontal plane 118 and the first plane The surfaces of the two horizontal step surfaces 120 are located on the same plane. The material of the sacrificial layer 124 may be silicon nitride, which is used as a liner silicon nitride layer in subsequent processing.

Referring to FIG. 8, a patterned photoresist layer 126 a, b is then formed on the sacrificial layer 24. The patterned photoresist layer 126a defines the side positions of the hole structure 132 opposite to the hole structure 130, and the patterned photoresist layer 26b defines the side positions of the hole structure 130 opposite to the hole structure 132. Next, as shown in FIG. 9, an etching process is performed to remove the sacrificial layer 124 not covered by the patterned photoresist layers U 6 a and b, and a sidewall 1 2 8 is formed on the surface of the vertical step surface 12 2, and then moved. In addition to the patterned photoresist layers 1 2 6 a, b. In a preferred embodiment of the present invention, the etch-back process is an anisotropic etching process or a dry etching process. Please refer to FIG. 10, using the remaining sacrificial layer 1 2 4 and the side wall 1 2 8 as a masking layer during the etching of the insulating layer, an etching process is performed to remove the USG layer 114 and the BPSG layer 11 which are not covered by the masking layer. 2 and the protective layer 110 to the gate structure 10, 102, 106, 108 surface to form two adjacent holes.

1240329 V. Description of the invention (8) The hole structures 1 3 0 and 1 3 2 are separated by a thin line structure 1 34. During the etching process, the side wall 1 28 is used as a mask layer on the thin line structure 1 34 to protect the pattern of the thin line structure 1 34. Therefore, the width of the thin line structure 1 34 is the bottom of the side wall 1 28. Therefore, those skilled in the art can use known techniques to adjust the bottom width of the sidewalls 1 2 8 during the deposition or etch-back of the sacrificial layer 1 2 4 to obtain the desired thin line structure 134 pattern. After the fabrication of the hole structures 130 and 132 is completed, other semiconductor device manufacturing processes can be continued.

Please refer to FIG. Η and FIG. 12. In the embodiment of the present invention, a first doped polysilicon layer 136 is deposited on the semiconductor substrate 100, and a hole structure 130 and 132 is filled with a first doped polysilicon layer 136. The BPSG layer serves as a support layer 138 for the subsequent chemical mechanical polishing process. Then, a chemical mechanical polishing process is performed to remove the remaining sacrificial layers 1 2 4, sidewalls 1 2 8 and some of the first doped polycrystalline silicon layers 1 3 6, support layers 1 3 8 and USG layers 1 1 4 to make the semiconductor substrate ^ \ 〇〇 The surface is flattened, as shown in Figure 11. In the chemical mechanical polishing & " removing the support layer 138, and depositing a dielectric layer 140 'composed of nitrogen oxide (N0) and a second doped polycrystalline chip Η on the semiconductor substrate 100 surface. Finally, according to the product design and needs, the lithography and etching process can be performed to remove the parts.

The second doped polycrystalline stone layer 142 and the dielectric layer 14 are divided to form a bit line pattern or capacitor. Compared with the conventional technology, the present invention mainly uses two lithography and uses

Page 13 1240329 V. Description of the invention (9) The sidewall is etched as a masking layer to define the pattern of two adjacent hole structures 1 30, 1 3 2 because the bottom width of the sidewall can be adjusted by The sacrificial layer 1 is controlled at 24 o'clock, so those skilled in the art can easily obtain a predetermined width of the bottom of the side wall in the process, and obtain a process with a pattern that cannot be patterned or precisely formed.

Thin line structure of the same width 1 3 4. According to the present invention, it is effective to know that in the technology, the thin line structure pattern 1 3 4 is precisely transferred due to factors such as light scattering during pattern transfer, and even the thin line structure (3 4 disconnection or position shift problem, especially when the thin line structure is caused). When the 1 3 4 pattern is less than 10 angstroms, the method according to the present invention can also effectively produce the structure i34 pattern and position to complete the production of two extremely adjacent holes 13 2. At the same time, the method of the present invention can also avoid ^ and directly The patterned photoresist layer is used to etch the insulating layer. When the photoresist layer collapses due to an excessively high aspect ratio, the success rate is greatly improved, and the product yield can be effectively improved. The range made by the range is equal to cover the range. The preferred embodiment, any application for specialization and modification in accordance with the present invention shall be covered by the patent of the present invention.

1240329 Brief description of the diagrams Brief description of the diagrams Figures 1 to 3 are schematic diagrams of a conventional process for fabricating two adjacent hole structures on a semiconductor substrate. Figures 4 to 5 are schematic diagrams of the conventional manufacturing process using a masking layer to assist in making two adjacent hole structures. 6 to 12 are schematic diagrams of a process for forming two adjacent hole structures on a semiconductor substrate according to the present invention. Schematic symbol description

10 Semiconductor substrate 12 ^ 14 '16, 18 [20 BPSG layer 22 USG layer 24 Protective layer 26 Patterned photoresist layer 28> 30 Hole structure 32 Fine line structure 50 Semiconductor substrate 52 ^ 54, 56' 58 f 60 Protective layer 62 BPSG Layer 64 USG layer 66 Masking layer 68 Patterned photoresist layer 70 ^ 72 Hole structure 74 Fine line structure 100 Semiconductor substrate 102 ^ 104 '106' 108 Gate structure 110 Protective layer 112 BPSG layer 114 USG layer 116 Patterned photoresist 118 The first horizontal step surface 120 The second horizontal step surface gate structure Page 15 1240329 Brief description of the drawing 122 Vertical step surface 124 Sacrificial layer 126 Patterned photoresist layer 128 Side wall 130 ^ 1 3 2 Hole structure 134 Fine line structure 136 First doped polycrystalline silicon layer 138 support layer 140 dielectric layer 142 second doped

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Claims (1)

1240329 6. Scope of patent application 1. A method for forming two adjacent hole structures on a semiconductor substrate, the two adjacent holes are a first hole structure and a second hole structure, respectively, between the first and second hole structures Separated by a thin line structure, the method includes the following steps: providing a semiconductor substrate having an insulating layer thereon; forming a stepped structure on the surface of the insulating layer, the stepped structure including a first horizontal step surface, a first step surface Two horizontal step surfaces and a vertical step surface are located between the first and second horizontal step surfaces; a uniform thickness sacrificial layer is deposited on the surface of the insulating layer, covering the first horizontal step surface, the second horizontal step surface, and the A vertical step surface; forming a patterned photoresist layer covering part of the first and second horizontal step surfaces; performing an etching process to remove The patterned photoresist layer covers the sacrificial layer, and forms a sidewall on the vertical step surface; removing the patterned photoresist layer; and using the sidewall and the remaining sacrificial layer Layer as a mask layer (hard mask), # carved not cover the insulating layer of the mask layer, to form two neighboring porous structure. 2. The method according to item 1 of the scope of patent application, wherein the width of the bottom of the side wall is approximately equal to the width of the thin line structure. 3. The method as described in item 1 of the scope of patent application, wherein the width of the thin line structure is slightly less than 100 angstroms (A). Page 17 1240329 6. Application for Patent Scope 4. The method as described in item 1 of the patent application scope, wherein the insulating layer includes unoped silicate glass (USG) and borophos -phosilicate glass (BPSG). 5. The method according to item 1 of the scope of patent application, wherein the insulating layer comprises a first insulating layer and a second insulating layer located above the first insulating layer. 6. The method according to item 5 of the scope of patent application, wherein the surfaces of the first and second horizontal step surfaces are the first insulating layer. 7. The method according to item 5 of the scope of patent application, wherein the first insulating layer is composed of undoped silica glass, and the second insulating layer is composed of borophosphosilicate glass. 8. The method according to item 1 of the scope of patent application, wherein the first and second horizontal step masks have a step height difference, and the thickness of the sacrificial layer is approximately equal to the height difference. 9. The method according to item 1 in the scope of patent application, the sacrificial layer is a liner silicon nitride layer ° 1 0. The method according to item 1 in the scope of patent application, wherein the etch-back system Page 18 1240329 VI. Scope of patent application The process is a dry-etching process. 1 1. The method according to item 1 of the scope of patent application, wherein the first horizontal step surface is lower than the second horizontal step surface. ί IliH Page 19