KR0172541B1 - Method of forming multi-layer wiring - Google Patents
Method of forming multi-layer wiring Download PDFInfo
- Publication number
- KR0172541B1 KR0172541B1 KR1019950047402A KR19950047402A KR0172541B1 KR 0172541 B1 KR0172541 B1 KR 0172541B1 KR 1019950047402 A KR1019950047402 A KR 1019950047402A KR 19950047402 A KR19950047402 A KR 19950047402A KR 0172541 B1 KR0172541 B1 KR 0172541B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- photoresist
- metal wiring
- film
- insulating layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자 제조공정 중 다층 금속 배선 형성방법에 있어서, 기판상에 하부 금속 배선 마스크인 감광막 패턴을 사용하여 하부 금속 배선 패턴을 형성하는 단계; 상기 감광막 패턴이 형성된 전체구조 상부에 불순물이 도핑된 절연막을 형성하는 단계; 상기 불순물이 도핑된 절연막의 소정부위를 식각하여 하부 금속 배선 패턴과 감광막의 경계면에서 상기 불순물이 도핑된 절연막이 분리되도록 하는 단계; 상기 감광막을 제거하는 동시에 상기 감광막 상에 분리된 불순물이 도핑된 절연막을 제거하는 단계; 전체구조 상부에 제1금속층간 절연막을 형성하고, 다시 평탄화용 감광막을 형성하는 단계; 상기 감광막 및 제1금속층간 절연막의 소정부위까지 에치백하고, 다시 전체구조 상부에 제2층간 절연막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a multilayer metal wiring in a semiconductor device manufacturing process, the method comprising: forming a lower metal wiring pattern on a substrate by using a photoresist pattern as a lower metal wiring mask; Forming an insulating layer doped with impurities on the entire structure on which the photoresist pattern is formed; Etching a predetermined portion of the insulating layer doped with the impurity to separate the insulating layer doped with the impurity from an interface between the lower metal wiring pattern and the photoresist; Simultaneously removing the photoresist and removing an insulating layer doped with impurities separated from the photoresist; Forming a first interlayer insulating film on the entire structure, and then forming a planarizing photoresist film; And etching back to a predetermined portion of the photosensitive film and the first interlayer insulating film, and again forming a second interlayer insulating film on the entire structure.
Description
제1a도 내지 제1f도는 본 발명의 일실시예에 따른 다층 금속 배선 형성 공정도.1A to 1F are diagrams illustrating a process of forming a multilayer metal wiring according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 산화막1: silicon substrate 2: oxide film
3, 7 : 감광막 4 : 하부 금속 배선 패턴3, 7: photosensitive film 4: lower metal wiring pattern
5, 5a, 5b : BPSG막 6 : 제1금속층간 산화막5, 5a, 5b: BPSG film 6: First metal interlayer oxide film
8 : 제2금속층간 산화막8: oxide film between the second metal layers
본 발명은 반도체 소자 제조 공정 중 다층 금속 패턴 형성방법에 관한 것으로, 특히 고집적 반도체 소자의 평탄화 및 금속층간 절연막의 목적으로 사용되는 BPSG(Bor ophospho Silicate Glass), 또는 BSG 또는 PSG를 이용한 다층 금속 패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layer metal pattern during a semiconductor device manufacturing process, and in particular, to form a multilayer metal pattern using BPSG (Borophospho Silicate Glass), or BSG or PSG, which is used for the purpose of planarization of a highly integrated semiconductor device and an interlayer insulating film. It is about a method.
BPSG막은 산화막 증착시에 B나 P를 함유하는 반응물을 첨가하여 증착된 SiO2- P2O5- B2O3의 혼합 산화막으로서 금속 배선 이전의 배선층간 절연막으로 사용한다. 불순물을 첨가한 산화막으로 반도체 소자의 집적도가 높아짐에 따라 더욱 중요시되고 있다.The BPSG film is a mixed oxide film of SiO 2 -P 2 O 5 -B 2 O 3 deposited by adding a reactant containing B or P at the time of oxide film deposition and used as an interlayer insulating film before metal wiring. It is becoming more important as the degree of integration of a semiconductor device is increased with an oxide film containing impurities.
SiO2나 B2O3가 들어가면 열적 공정인 어닐(Aneeal)시 글래스의 용해 온도가 낮아지기 때문에 900℃이하의 온도에서 리플로우(Reflow) 처리를 해주더라도 BPSG막의 비스코스 플로우(Viscous flow)가 일어난 산화막이 평탄화 되므로서 차후 배선 재료의 증착 및 노광, 식각공정을 용이하게 만들어 줄뿐 아니라 금속 증착시 커버리지(Coverage)를 양호하게 해준다. BPSG막의 증착법은 사용 반응물에 따라 구분이 가능하나 대표적으로는 SiH4계 BPSG와 TEOS계 BPSG가 있다.When SiO 2 or B 2 O 3 enters, the melting temperature of the glass decreases during thermal annealing, so the oxide film in which the viscous flow of the BPSG film occurs even though the reflow treatment is performed at a temperature below 900 ° C. This planarization facilitates the subsequent deposition, exposure, and etching of the wiring material, as well as good coverage during metal deposition. The deposition method of BPSG film can be classified according to the reactants used, but there are representative SiH 4 -based BPSG and TEOS-based BPSG.
반도체 소자의 고집적화로 토폴로지가 악화되어 갭-필링(Gap-filling)에 효과적인 동시에 부분 및 전면 평탄화가 가능하고, 막 두께의 균일성은 물론, B/P 함유의 균일성 및 토폴로지를 보상해줄 수 있는 공정상의 개선이 절실하게 요구되고 있다.Highly integrated semiconductor devices deteriorate the topologies, which are effective for gap-filling and planarization of the part and the entire surface.The process can compensate for the uniformity of B / P content and topology as well as the uniformity of film thickness. There is an urgent need to improve the jacket.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 미세선폭의 높은 토폴로지를 이루는 기판 상에 보이드 없이 갭-필링(gap-filling)을 이루며 평탄화할 수 있는 다층 금속 배선 형성방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method for forming a multi-layer metal wiring that can be planarized without gap-filling (gap-filling) on a substrate having a high topology of fine line width. have.
상기 목적을 달성하기 위하여 본 발명은 반도체 소자 제조공정 중 다층 금속 배선 형성방법에 있어서, 본 발명은 반도체 소자 제조공정 중 다층 금속 배선 형성 방법에 있어서, 기판상에 하부 금속 배선 마스크인 감광막 패턴을 사용하여 하부 금속 배선 패턴을 형성하는 단계; 상기 감광막 패턴이 형성된 전체구조 상부에 불순물이 도핑된 절연막을 형성하는 단계; 상기 불순물이 도핑된 절연막의 소정부위를 식각하여 하부 금속 배선 패턴과 감광막의 경계면에서 상기 불순물이 도핑된 절연막이 분리되도록 하는 단계; 상기 감광막을 제거하는 동시에 상기 감광막 상에 분리된 불순물이 도핑된 절연막을 제거하는 단계; 전체구조 상부에 제1금속층간 절연막을 형성하고, 다시 평탄화용 감광막을 형성하는 단계; 상기 감광막 및 제1금속층간 절연막의 소정부위까지 에치백하고, 다시 전체구조 상부에 제2층간 절연막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a multilayer metal wiring in a semiconductor device manufacturing process, and the present invention provides a method for forming a multilayer metal wiring in a semiconductor device manufacturing process, using a photoresist pattern as a lower metal wiring mask on a substrate. Forming a lower metal wiring pattern; Forming an insulating layer doped with impurities on the entire structure on which the photoresist pattern is formed; Etching a predetermined portion of the insulating layer doped with the impurity to separate the insulating layer doped with the impurity from an interface between the lower metal wiring pattern and the photoresist; Simultaneously removing the photoresist and removing an insulating layer doped with impurities separated from the photoresist; Forming a first interlayer insulating film on the entire structure, and then forming a planarizing photoresist film; And etching back to a predetermined portion of the photosensitive film and the first interlayer insulating film, and again forming a second interlayer insulating film on the entire structure.
이하, 첨부된 도면 제1a도 내지 제1f도를 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1F.
먼저, 제1a도에 도시된 바와 같이, 산화막(2)이 증착된 실리콘 기판(1)상에 사진식각 공정으로 하부 금속 배선 패턴(4)을 형성한다. 이때, 사진식각 공정시 하부 금속 마스크로 사용된 감광막(3)은 제거하지 않는다.First, as shown in FIG. 1A, the lower metal wiring pattern 4 is formed on the silicon substrate 1 on which the oxide film 2 is deposited by a photolithography process. In this case, the photoresist film 3 used as the lower metal mask during the photolithography process is not removed.
다음으로, 제1b도에 도시된 바와 같이, 상기 전체구조 상에 BPSG막(5)을 증착한다.Next, as shown in FIG. 1B, a BPSG film 5 is deposited on the entire structure.
이어서, 제1c도에 도시된 바와 같이, 상기 BPSG막(5)을 습식 식각하여 하부 금속 배선 패턴(4)과 감광막(3)상에서 상기 BPSG막(5)이 절단되도록 식각하여 BPSG막(5a)과 BPSG막(5b)을 형성함으로써, 이후의 공정에 의해 감광막 상부의 BPSG막(5b)가 감광막 제거시 동시에 제거되도록 한다.Subsequently, as shown in FIG. 1C, the BPSG film 5 is wet-etched to be etched so that the BPSG film 5 is cut on the lower metal wiring pattern 4 and the photoresist film 3. And the BPSG film 5b are formed so that the BPSG film 5b on the photoresist film is removed at the same time when the photoresist film is removed by a subsequent process.
다음으로, 제1d도에 도시된 바와 같이, 상기 감광막(3)을 제거하면서 동시에 그 상부의 BPSG막(5b)을 제거하여 하부 금속 배선 패턴(4)의 상부를 노출시킨다.Next, as shown in FIG. 1D, the photoresist film 3 is removed while the upper BPSG film 5b is removed to expose the upper portion of the lower metal wiring pattern 4.
이어서, 제1e도에 도시된 바와 같이, 제1금속층간 산화막(6)을 증착하고 평탄화 에치백을 위한 감광막(7)을 형성한다.Subsequently, as shown in FIG. 1E, a first interlayer oxide film 6 is deposited and a photosensitive film 7 for planarization etch back is formed.
끝으로, 제1f도에 도시된 바와 같이, 상기 감광막(7) 및 제1금속층간 산화막(6)의 소정부위까지 에치백하고, 다시 제2층간 산화막(8)을 형성한다.Finally, as shown in FIG. 1F, the film is etched back to a predetermined portion of the photosensitive film 7 and the first metal interlayer oxide film 6, and the second interlayer oxide film 8 is formed again.
이후 비아 콘팩홀 및 상부 금속막을 형성하여 다층 금속 배선형성을 완료한다.After that, the via capacitor hole and the upper metal layer are formed to complete the formation of the multilayer metal interconnection.
상기와 같이 본 발명은 고집적 반도체 소자 제조시, 효과적인 갭필링을 제공하며, 부분은 물론 전면 평탄화에 효과적인 다층 금속 배선 형성방법을 제공하여 반도체 소자의 고집적화에 기여하는 효과가 있다.As described above, the present invention provides an effective gap filling in manufacturing a highly integrated semiconductor device, and provides a method of forming a multilayer metal wiring effective for planarization of a portion as well as a part, thereby contributing to high integration of a semiconductor device.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950047402A KR0172541B1 (en) | 1995-12-07 | 1995-12-07 | Method of forming multi-layer wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950047402A KR0172541B1 (en) | 1995-12-07 | 1995-12-07 | Method of forming multi-layer wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053519A KR970053519A (en) | 1997-07-31 |
| KR0172541B1 true KR0172541B1 (en) | 1999-03-30 |
Family
ID=19438258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950047402A KR0172541B1 (en) | 1995-12-07 | 1995-12-07 | Method of forming multi-layer wiring |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172541B1 (en) |
-
1995
- 1995-12-07 KR KR1019950047402A patent/KR0172541B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970053519A (en) | 1997-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100333382B1 (en) | Method for forming multi-level metal interconnection of semiconductor device | |
| KR0172541B1 (en) | Method of forming multi-layer wiring | |
| KR20000044892A (en) | Method for forming metal wiring of semiconductor device | |
| KR0124144B1 (en) | Semiconductor device including silicon ladder resin layer | |
| JPH10189709A (en) | Manufacturing method of integrated circuit device | |
| KR100367695B1 (en) | Method for forming via contact in semiconductor device | |
| KR100244713B1 (en) | Manufacturing method of semiconductor device | |
| KR100265835B1 (en) | A method for forming metal wire in semiconductor device | |
| KR100406733B1 (en) | manufacturing method of semiconductor device | |
| KR100249389B1 (en) | Method of fabricating via hole | |
| KR100365745B1 (en) | Contact hole formation method of semiconductor device | |
| KR100235960B1 (en) | Method of forming conducting line in semiconductor device | |
| KR100342976B1 (en) | Metal line of a semiconductor device and method of forming the same | |
| KR100248150B1 (en) | Contact hole formation method of semiconductor device | |
| KR100537424B1 (en) | Method for fabricating a semiconductor device | |
| KR100275127B1 (en) | Method of planarization multilayer metal line of semiconductor device | |
| KR100296132B1 (en) | Method for forming metal wiring of semiconductor device using large machine | |
| KR960006962B1 (en) | Method for manufacturing metal wiring of semiconductor device | |
| KR100262009B1 (en) | A method of fabricating semiconductor device | |
| KR100249018B1 (en) | Method of fabricating contact hole | |
| KR100198653B1 (en) | Semiconductor device metallisation method | |
| KR100338109B1 (en) | Metal wiring manufacturing method of semiconductor device | |
| KR950011554B1 (en) | Multilayer Metal Wiring Formation Method | |
| KR100203299B1 (en) | Interconnecting method of semiconductor device | |
| KR100328829B1 (en) | Manufacturing method for contact in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19951207 |
|
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19951207 Comment text: Request for Examination of Application |
|
| PG1501 | Laying open of application | ||
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19980828 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19981024 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 19981024 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20010918 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20020918 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20030919 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20040920 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20050922 Start annual number: 8 End annual number: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20060920 Year of fee payment: 9 |
|
| PR1001 | Payment of annual fee |
Payment date: 20060920 Start annual number: 9 End annual number: 9 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20080910 |