TWI235461B - Manufacturing method of flash memory - Google Patents

Abstract

The present invention is related to a manufacturing method of flash memory which includes forming a patterned tunneling dielectric layer, conductor layer and mask layer on a substrate to form a gate structure; forming a buried drain in the substrate; filling a insulating layer circumferentially around the gate structure and the surface level of the insulating layer lower than the surface level of the patterned conductor layer; forming a material layer on the insulating layer; removing the patterned mask layer; forming another pattered conductor layer on the patterned conductor layer of the gate structure and protruding over the surface of insulating layer; removing the material layer; forming a intergate dielectric layer on the substrate; forming a control gate on the intergate dielectric layer.

Description

1235461_ 5. Description of the invention (1) The technical field to which the invention belongs The present invention relates to a method for manufacturing a flash memory, and more particularly to a flash memory that increases the overlapping area between a floating gate and a control gate Manufacturing method. Prior art Flash memory devices have become a widely used memory device in personal computers and electronic devices due to their superior data retention characteristics. A typical flash memory device is generally designed to have a Stack-Gate structure, which includes a tunnel oxide layer, a polycrystalline silicon floating gate (F 1 〇ating Gate), a dielectric layer with a structure of Oxide-Ni tride-Oxide ·, and a polycrystalline silicon control gate (C ο for controlling data access) ntr ο 1 4 Gate) o In flash memory operation, the larger the gate-coupling ratio (GCR) between the floating gate and the control gate, the larger the operating voltage required for its operation. It will be lower, and the operation speed and efficiency of flash memory will be greatly improved. The methods for increasing the gate coupling ratio include increasing the contact area between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the floating gate and control. The dielectric constant (Dielectric Constant; k) of the dielectric layer between the gates. Increasing the area of overlap between the floating gate and the control gate will help increase the gate coupling rate. However, under the trend of integrated circuits continuously pursuing a high degree of integration, each memory cell occupied by flash memory elements The area must therefore be reduced. So how to make a high coupling rate in a limited chip area

9677 twf.p td Page 7 1235461_ V. Description of the invention (2) The flash memory is currently an extremely important subject. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a flash memory, which can increase the overlap area between the floating gate and the control gate, thereby improving the coupling rate of the components. According to the foregoing and other objectives, the present invention provides a method for manufacturing a flash memory. This method sequentially forms a tunneling dielectric layer, a conductor layer, and a mask layer on a substrate. Then, the tunneling dielectric layer, the mask layer and the conductor layer are patterned to form longitudinally arranged strips on the substrate, and then a buried drain region is formed in the substrate between the strips. The strips are then patterned to form a gate structure on the substrate. The gate structure includes a patterned tunneling dielectric layer, a patterned conductor layer, and a patterned mask layer. An insulation layer is then formed around the gate junction structure. The surface of the insulation layer is lower than the top surface of the patterned conductor layer, and a part of the surface around the gate structure is exposed. Thereafter, a material layer is formed on the insulating layer between the gate structures. The patterned mask layer is then removed to expose the top surface of the patterned conductor layer of the gate structure. Then, another patterned conductor layer is formed on the top surface of the patterned conductor layer of the gate structure. This patterned conductor layer is a material covering the top surface of the patterned conductor layer of the gate structure and extends to the periphery of the material. On the floor. In other words, the upper surface area of the patterned conductor layer is larger than the upper surface area of the patterned conductor layer of the gate structure, and is formed with the patterned conductor layer of the gate structure.

9677 twf.ptd Page 8 1235461___ 5. Description of the invention (3) The present invention is to reduce the height of the insulating layer around the gate structure, so that part of the sidewall surface of the conductor layer in the gate structure is exposed, and it is extended to the buried surface. The patterned conductor layer above the sink-type drain electrode increases the overlapping area between the floating gate and the control gate, thereby increasing the engagement rate of the components. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Embodiments 1A to 1 Figure L is a top view of a flash memory manufacturing process according to a preferred embodiment of the present invention. Figures 2A to 2L are cross-sectional views taken along lines I-Γ in Figures 1A to 1L. First, please refer to FIG. 1A and FIG. 2A at the same time, and provide a substrate 100, which is, for example, a silicon substrate. Then, a tunneling dielectric layer 102, a conductor layer 104, and a mask layer 106 are sequentially formed on the substrate 100. The material of the penetrating dielectric layer 102 is, for example, oxidized stone, and its thickness is, for example, about 50 to 100 angstroms. The formation method of the tunnel dielectric layer 102 is, for example, a thermal oxidation method or a low-pressure chemical vapor deposition method (LPCVD). The material of the conductive layer 104 is, for example, doped polycrystalline silicon. The formation method is, for example, a low-pressure chemical vapor deposition method, after depositing a polycrystalline silicon layer using silicon methane (S i 1 an e) as a gas source, and then performing a dopant implantation process to form it. Among them, the operating temperature of the deposition process is between 5 7 5 ° C and 65 0 ° C, and the operating pressure is about 0 · 3 t 〇 r r to 0.6 t 〇 r r

between. The material of the U cover curtain layer 106 is, for example, silicon nitride or silicon oxide. When the material is silicon nitride, for example, dichlorosilicon and ammonia are used as the reaction gas source,

% 77t.wf.ptd Page 9 1235461_ V. Description of the invention (4) It is formed by low pressure chemical vapor deposition. Please refer to Figure 1B and Figure 2B at the same time. A patterned photoresist layer 108 is formed on the mask layer 106. Then, using the photoresist layer 108 as a mask, the dielectric layer 102, the conductor layer 104, and the mask layer 106 are etched through to form a longitudinally arranged stripe 200 on the substrate 100. This stripe 2 0 0 includes a patterned tunnel dielectric layer 102a, a patterned conductor layer 104a, and a patterned mask layer 106a. Then, an ion implantation process is performed to form a buried Drain 110 in the substrate 100 between the strips 200. Please refer to Figure 1C and Figure 2C at the same time. Remove the aforementioned patterned photoresist layer 108. Then, another patterned photoresist layer (not shown) is formed on the patterned mask layer 10a. Then use this patterned photoresist layer as a mask, and then etch the strips 200 to form a gate structure 300 on the substrate 100. The gate structure 3 0 0 is composed of a patterned tunneling dielectric layer 10 2 b, a patterned conductor layer 1 0 4 b, and a patterned mask layer 1 0 6 b. Next, referring to FIG. 1D and FIG. 2D at the same time, an insulating layer 1 12 is formed on the substrate 100 to cover the gate structure 3 0 0 and fill the gap between the gate structures 3 0 0 . The material of the insulating layer 1 1 2 is different from the material of the cover layer 10 6 b with different etching selectivity. The material of the insulating layer 1 1 2 is, for example, silicon oxide, silicon nitride, or spin-on glass. The formation method is, for example, a high-density plasma chemical vapor deposition method (H D P-C V D) or a spin coating method. Next, referring to Figure 1E and Figure 2E at the same time, remove the insulating layer 1 1 2 covering the surface of the mask layer 1 0 6 b to expose the surface of the patterned mask layer 1 0 6 b. The lower insulating layer 1 1 2 a is located between the gate structures 300. Removal • Static masking layer 1 0 6 b The method of insulating layer 1 1 2 on the surface is, for example, chemical mechanical research

9677 twf.ptd Page 10 1235461 V. Description of the invention (5) Grinding method or back shoe carving method. Afterwards, please refer to Figure 1 F and Figure 2 F at the same time and remove part of the insulating layer 1 1 2 a so that the surface of the remaining insulating layer 1 1 2 b is lower than the top of the conductor layer 1 0 4 b Surface, so as to expose a part of the side wall surface around the conductive layer 104b. A method of removing a part of the insulating layer 1 1 2 a is, for example, a back-etching method. After that, please refer to Figure 1 G and Figure 2 G at the same time, and then form a material layer 1 1 4 on the insulating layer 1 1 a to cover the gate structure 3 0 0 and fill in the gate structure 3 0 0 Gap between. The material of the material layer 1 1 4 is, for example, borophosphosilicate glass (B P S G) or phosphosilicate glass (P S G), which has a different etching rate from the cover layer 1 06 b and the insulating layer 1.1 2 b. When the material layer 1 1 4 is borophosphosilicate glass, the formation method of borophosphosilicate glass is, for example, atmospheric pressure chemical vapor deposition method, and silane, phosphine, and hydrogen borohydride are used as reaction gas sources to react. The temperature is, for example, between 3 5 0 ° C and 4 5 Ο X :. Next, referring to the first and second drawings at the same time, remove the material layer 1 1 4 covered on the surface of the mask layer 1 0 6 b to expose the surface of the patterned mask layer 1 0 6 b. A material layer 1 1 a is located between the gate structures 300. Among them, the method of removing the material layer 1 1 4 on the surface of the mask layer 106 b is, for example, a chemical mechanical polishing method or a back-etching method. After that, please refer to Figure 1 I and Figure 2 I at the same time. The cover layer 106b is removed to expose the upper surface of the conductor layer 104b. The method of removing the mask layer 106b is, for example, a wet etching method. When the material of the mask layer 10 6 b is silicon nitride, the post-etching agent used for removing the mask layer 10 6 b is, for example, wall acid. Next, please refer to Figure 1 J and Figure 2 J at the same time. Another patterned conductor layer 1 1 6 is formed on the top surface of the pattern 4 conductor layer 1 0 4 b.

9677 twf.p td Page 11 1235461_ 5. Description of the invention (6) The body layer 1 1 6 covers the top surface of the patterned conductor layer 1 0 4 b, and extends to cover the material layer 1 1 4 a at its periphery. In other words, the upper surface area of the patterned conductor layer 116 is larger than the upper surface area of the patterned conductor layer 104b and the patterned conductor layer 104b constitutes a floating gate electrode 400. The step of forming the patterned conductor layer 1 16 includes forming a conductor material layer. The material of the conductor material layer is, for example, doped polycrystalline silicon, and covers the top of the patterned conductor layer 1 0 4 b and the material layer 1 1 4 a. On the surface. The method of forming the conductive material layer is, for example, a low pressure chemical vapor deposition method and then forming a patterned photoresist layer (not shown) on the conductive material layer. Then use this patterned photoresist layer as a mask and etch the conductor layer 1 1 6 to expose the top surface of the material layer 1 1 4 a. Please refer to Figure 1 K and Figure 2 K. Remove the material layer 1 1 4 a. The method of removing the material layer 1 1 4 a is, for example, the method of engraving the surname. Please refer to Figures 1 L and 2 L. An inter-gate dielectric layer 1 1 8 is formed on the substrate 100 to cover the sidewall of the patterned conductor layer 10 4 b and the sidewall and upper surface of the patterned conductor layer 1 16. The material of the inter-gate dielectric layer 1 1 8 includes silicon oxide / silicon nitride / silicon oxide (0 N 0). The inter-gate dielectric layer 1 1 8 is formed by, for example, forming an oxide layer by a thermal oxidation method, and then forming a silicon nitride layer and another oxide layer by a low pressure chemical vapor deposition method. Of course, the material of the inter-gate dielectric layer 1 18 can also be a silicon oxide layer or a silicon oxide / silicon nitride layer. Thereafter, a conductor layer 120 is formed on the inter-gate dielectric layer 1 18 as a control gate. The conductor layer 1 2 0 is, for example, a polycrystalline silicide metal (P ο 1 y c i d e) composed of a doped polycrystalline silicon layer 1 2 2 and a petrified metal layer 1 2 4.

9677twf. Xixianyuan is a gas source, and the formation method is, for example, a low-pressure chemical vapor deposition method. The subsequent completion of the flash memory process is well known to those skilled in the art and will not be repeated here. As mentioned above, the present invention The feature is that the floating gate is formed by two patterned conductor layers. The first conductor layer is located between the buried drain electrodes, which is reduced by the height of the surrounding insulating layer to make its part A portion of the sidewall surface is exposed. Another conductor layer is located on the first conductor layer and extends above the buried drain. The sidewall exposed by the first conductor layer and the second conductor layer extend to the buried portion. The upper part of the drain is used to increase the area of overlap between the floating gate and the control gate, thereby increasing the coupling rate of the device. Since the present invention does not increase the unit area of the memory cell, it can The coupling ratio of the components is increased by increasing the area between the floating gate and the control gate, so that the component accumulation can be increased. In the above-mentioned preferred embodiment, the conductive layer of a gate structure is used. The formation of another conductor layer is taken as an example to illustrate the spirit of the present invention. However, the present invention is not limited to the above-mentioned application, and two conductor layers or multiple conductor layers may be sequentially formed on a conductor layer of a gate structure. The method of sequentially forming two conductor layers on the conductor layer of the gate structure is as follows. Please refer to FIG. 3 and follow the method described in the above FIGS. 2A to 2J to form the second J figure. After the structure, the material layer 3 2 is filled in the gap between the patterned conductor layers 1 16. The surface south of the material layer 3 2 is lower than or substantially equal to the surface height of the patterned conductor layer 116 . Then the patterned conductor

9677twf.ptd Page 13 1235461_ 5. Description of the invention (8) Another patterned conductor layer 304 is formed on the layer 116. The patterned conductor layer 304 covers the patterned conductor layer 1 1 6 and extends to the peripheral material layer 3 0 2 on. Next, referring to FIG. 4, the material layer 1 4 a and the material layer 3 0 2 are removed to form a conductor layer 1 0 4 b with a gate structure and two other conductor layers 1 1 6 and 3 0 4 floating gate. Then, an inter-gate dielectric layer 1 18 is formed on the surface of the exposed floating gate, and a conductor layer 120 is formed on the inter-gate dielectric layer 1 18 as a control gate. The present invention can also repeat the steps of forming the material layer 3 0 2 and the conductor layer 3 0 4 on the conductor layer 10 4 b of a gate structure. Multiple conductors are sequentially formed to increase the floating gate and the control gate. The area of overlap between the poles further improves the coupling rate. In summary, the present invention is to reduce the height of the insulating layer around the gate structure, so that part of the sidewall surface of the conductor layer in the gate structure is exposed, and the patterned conductor layer above the buried drain is used to increase The overlapping area between the floating gate and the control gate can further improve the coupling rate of the components without increasing the chip area. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

9677t.wf.ptd Page 14 1235461_ Brief description of the drawings 1A to 1L are top views showing the manufacturing process of a flash memory according to the preferred embodiment of the present invention; 2A to 2 Figure L is a cross-sectional view taken along line I-Γ of Figures 1 A to 1 L; and Figures 3 and 4 are sectional views showing the manufacturing process of another flash memory according to the present invention. Symbols are not explained.1 0 0: substrate 1 102: tunneling oxide layers 102a, 102b: patterned tunneling oxide layers 104, 120: conductor layers 104a, 104b, 116, 304: patterned conductor layers Bu 1 06: Mask layer 106a, 106b: Patterned mask layer 1 0 8: Patterned photoresist layer 1 1 0 ... Buried drain 1 1 2, 1 1 2 a, 1 1 2 b: Insulation Layer 1 1 4, 1 1 4 a, 3 0 2: material layer 118 inter-gate dielectric layer 122 doped polycrystalline silicon layer 1 24 silicided metal layer 200 strip 300 gate structure 400 floating gate

9677twf.ptd Page 15

Claims (1)

T235461_ VI. Scope of patent application1. A method for manufacturing flash memory, including the following steps: sequentially forming a tunneling dielectric layer, a first conductor layer, and a cover layer on a substrate; performing a first Patterning process, defining the tunneling dielectric layer, the mask layer and the first conductor layer to form a strip on the substrate; forming a buried drain in the substrate between the strips A polar region; performing a second patterning process, defining the strip, and forming a gate structure on the substrate, the gate structure is composed of a patterned tunnel dielectric layer, a patterned mask layer, and a Formed by a patterned first conductor layer; forming an insulation layer on the substrate around the gate structure, the surface of the insulation layer being lower than the surface of the patterned first conductor layer 'exposes the patterned first conductor A part of the sidewall surface of the layer; forming a material layer on the insulating layer around the gate structure; removing the patterned mask layer; on the top surface of the patterned first conductor layer of the gate structure Forming a patterned second conductor layer, the The patterned second conductor layer covers the top surface of the patterned first conductor layer, and extends to cover the material layer on the periphery of the patterned first conductor layer, and forms a floating with the patterned first conductor layer. The gate; removing the material layer to expose a portion of the sidewall surface of the patterned first conductor layer; forming an inter-gate dielectric layer on the exposed surface of the floating gate; and the inter-gate dielectric A control gate is formed on the electrical layer. 9677twf. Pt.d Page 16 1235461 6. Application for Patent Scope 2 · The flash memory manufacturing method described in item 1 of the patent application scope, wherein a patterned second conductor layer is formed on the patterned first conductor layer After the conductor layer, before removing the material layer, the method further includes the following steps: (a) forming another material layer around the patterned second conductor layer, the surface height of the material layer being lower than or substantially equal to the patterning The surface height of the second conductor layer; (b) forming a patterned third conductor layer on the patterned second conductor layer, the patterned third conductor layer covering the patterned second conductor layer and extending to the On another material layer, and the patterned first, second and third conductor layers constitute the floating gate; and (c) removing the other material layer. 3. The method of manufacturing a flash memory as described in item 2 of the scope of the patent application, wherein the material of the material layer is different from the insulating layer in the etching rate. 4. The method for manufacturing a flash memory as described in item 2 of the scope of patent application, wherein the steps of forming the patterned third conductor layer and removing the other material layer further include repeating the above (a) to (c) step. 5. The method for manufacturing a flash memory as described in item 1 of the scope of the patent application, wherein the material of the material layer is different from the insulating layer in the etching rate. 6. The method for manufacturing a flash memory as described in item 5 of the scope of patent application, wherein the material of the insulating layer includes one of silicon oxide, silicon nitride, and spin-on glass. 7. Manufacturer of flash memory as described in item 5 of the scope of patent application 9677 twf.ptd Page 17 1235461___ 6. Method of applying for a patent, where the material of the material layer includes one of borophosphosilicate glass or phosphosilicate glass. 08 · Flash memory as described in the first item In a manufacturing method, the step of forming the insulating layer around the gate structure includes: forming an insulating material layer on the substrate to cover an upper surface of the gate structure and fill the periphery of the gate structure; removing The insulating material layer covered on the upper surface of the gate structure to expose the surface of the cover layer; and removing a portion of the insulating material layer so that the surface of the insulating material layer is between the patterned first guide. The insulating layer is formed between the bottom surface of the bulk layer and the top surface of the patterned first conductor layer. _ 9 The method for manufacturing a flash memory as described in item 8 of the scope of patent application, wherein the method of removing the insulating material layer covered on the upper surface of the gate structure is chemical mechanical polishing and etch back Law one of them. 10. The method for manufacturing a flash memory as described in item 8 of the scope of patent application, wherein the method for removing a part of the insulating material layer includes an etch-back method. 1 1. A method for manufacturing a flash memory includes the following steps: sequentially forming a patterned tunneling dielectric layer and a patterned first conductor layer on a substrate; between the patterned first conductor layer An embedded layer and a polar region are formed in the substrate, and an insulation layer is formed around the patterned first conductor layer, and a surface of the insulation layer is interposed between a bottom surface and a top surface of the patterned first conductor layer. Between " 9677 twf.p td Page 18 1235461__ VI. The scope of patent application forms a material layer on the insulating layer around the patterned first conductor layer; forms a pattern on the top surface of the patterned first conductor layer "Second conductor layer" The patterned second conductor layer covers the top surface of the patterned first conductor layer, and extends to the material layer on the periphery of the patterned first conductor layer, and is connected to the patterned first conductor layer. A conductor layer constitutes a floating gate; the material layer is removed to expose a portion of the sidewall surface of the patterned first conductor layer; an inter-gate dielectric layer is formed on the exposed surface of the floating gate And forming a control gate on the inter-gate dielectric layer. 1 2. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein after forming a patterned second conductor layer on the patterned first conductor layer and before removing the material layer, The method further includes the following steps: (a) forming another material layer around the patterned second conductor layer, and a surface height of the material layer is lower than or substantially equal to a surface south of the patterned second conductor layer; ( b) forming a patterned third conductor layer on the patterned second conductor layer, the patterned third conductor layer covers the patterned second conductor layer and extends to the other material layer, and the pattern Forming the first, second and third conductor layers to form the floating gate; and (c) removing the other material layer. 13. The method for manufacturing a flash memory as described in item 12 of the scope of the patent application 〇 The method, wherein the material of the material layer has a different etch rate from the insulating layer 9677 twf · p td Page 19 1235461 6. Those who apply for a patent. 14. The method for manufacturing a flash memory as described in item 12 of the scope of patent application, wherein the steps of forming the patterned third conductor layer and removing the other material layer further include repeating the above (a) to ( c) steps. 15 · The flash memory manufacturing method according to item 11 of the scope of patent application, wherein the material of the material layer has a different etching rate from the insulating layer. 16 · The flash memory manufacturing method as described in item 15 of the scope of patent application, wherein the material of the insulating layer includes one of silicon oxide, silicon nitride, and spin-on glass. 17 · The method for manufacturing a flash memory according to item 15 of the scope of patent application, wherein the material of the material layer includes one of borophosphosilicate glass or phosphosilicate glass. 18. The method for manufacturing a flash memory as described in item 11 of the scope of patent application, wherein the step of forming the insulating layer around the gate structure includes: forming an insulating material layer on the substrate to cover The upper surface of the gate structure and fills the periphery of the gate structure; removing the insulating material layer covered on the upper surface of the gate structure to expose the surface of the cover layer; and removing part of the insulating material Layer, so that the surface of the insulating material layer is interposed between the bottom surface of the patterned first conductor layer and the top surface of the patterned first conductor layer to form the insulating layer. 19. Manufacture of flash memory as described in item 18 of the scope of patent application 9677 t.wf. p td. Page 20-1235461 ___ VI. Patent Application Method 'where the method of removing the insulating material layer covered on the upper surface of the gate structure is the chemical mechanical polishing method and the back-contact engraving method. one. 2 〇 The method for manufacturing a flash memory as described in item 18 of the scope of patent application, wherein the method for removing a part of the insulating material layer includes an etch-back method. 9677twf.ptd Page 21