CN103972175B - Method for manufacturing damascene structure of NAND flash memory - Google Patents

Abstract

The invention discloses a manufacturing method of a mosaic structure of a NAND flash memory. A stop layer and a second dielectric layer are sequentially formed on the first dielectric layer in the substrate and on the contact plugs between the NAND strings. A patterned stop layer and a third dielectric layer having at least one first opening corresponding to the contact plug are sequentially formed on the second dielectric layer. And removing the third dielectric layer corresponding to the second opening and the second dielectric layer corresponding to the first opening by taking the patterned mask layer as a mask to form a groove and a dielectric window and expose the contact plug. Then, a conductive layer contacting the contact plug is formed in the trench and the via.

Description

Method for manufacturing damascene structure of NAND flash memory

technical field

The present invention relates to a manufacturing method of a volatile memory, and in particular to a manufacturing method of a damascene structure of a NAND flash memory.

Background technique

With the advancement of integrated circuit technology and the shrinking of component sizes, in order to overcome the increasingly smaller line width and prevent mis-alignment, self-alignment process design is usually adopted.

Taking NAND flash memory device as an example, in order to ensure the electrical connection, the bit line needs to cover the via window, and the via window must cover and be vertically aligned with the corresponding contact window, so usually multiple photolithography processes are required to form the above-mentioned structure, and requires high resolution, which easily increases the risk of misalignment.

Therefore, there is an urgent need for an interconnection manufacturing method of NAND flash memory that can simplify the process steps and avoid the misalignment problem.

Contents of the invention

The invention provides a method for manufacturing a damascene structure of NAND flash memory, which can simplify process steps and avoid misalignment.

The present invention also provides a method for manufacturing a damascene structure of NAND flash memory, which forms bit lines in simple steps while reducing the resistance value of the wires in the peripheral area.

The invention provides a method for manufacturing a mosaic structure of NAND flash memory. A substrate having an array of memory cells is provided, the memory cell array includes a plurality of NAND strings arranged along a direction, and in the direction, each NAND string includes a plurality of word lines and a plurality of floating gates located below the plurality of word lines pole, and two select transistors located across multiple word lines. A first dielectric layer covering the memory cell array is formed on the substrate. At least one contact plug contacting the substrate is formed between adjacent NAND strings. A termination layer and a second dielectric layer are sequentially formed on the first dielectric layer and the contact plug. A patterned termination layer is formed on the second dielectric layer, which has at least one first opening corresponding to the contact plug and exposes the second dielectric layer. A third dielectric layer is formed on the patterned stop layer and in the first opening. A patterned mask layer is formed on the third dielectric layer, which has at least one second opening corresponding to the first opening, and the second opening extends along the above direction and exposes the third dielectric layer. Using the patterned mask layer as a mask, remove the third dielectric layer exposed from the second opening to form a trench, and continue to remove the second dielectric layer exposed from the first opening to form a via window and expose termination layer. The exposed termination layer is removed, exposing the contact plug. A conductor layer in contact with the contact plug is formed in the trench and the via.

The present invention also provides a method for manufacturing the damascene structure of the NAND flash memory. Provide a substrate with a memory cell array and a peripheral region, and the peripheral region includes at least one transistor, and the memory cell array includes a plurality of NAND strings arranged along a direction, and in this direction, each NAND string includes a plurality of word lines and A plurality of floating gates located under the plurality of word lines, and two selection transistors located at both ends of the plurality of word lines. A first dielectric layer covering the transistors of the memory cell array and the peripheral area is formed on the substrate. At least one first contact plug contacting the substrate is formed between adjacent NAND strings. A termination layer and a second dielectric layer are sequentially formed on the first dielectric layer and the first contact plug. A patterned termination layer is formed on the second dielectric layer, which has at least one first opening corresponding to the first contact plug and at least one second opening located in the peripheral area, and exposes the second dielectric layer. A third dielectric layer is formed on the patterned stop layer and in the first and second openings. A patterned mask layer is formed on the third dielectric layer, which has at least one third opening corresponding to the first opening and extending along the above-mentioned direction, and at least one fourth opening corresponding to the second opening, and exposing the third dielectric layer. layer. Using the patterned mask layer as a mask, removing the third dielectric layer exposed from the third opening and the fourth opening to form a trench, and continuing to remove the second dielectric layer exposed from the first opening and the second opening layer to form a via and expose the stop layer. The exposed termination layer is removed to expose the first contact plug and the first dielectric layer in the peripheral area. A conductor layer in contact with the first contact plug is formed in the trench and the via.

Based on the above, the method for manufacturing the damascene structure of NAND flash memory proposed by the present invention utilizes a self-aligned double damascene (self aligned daul damascene) process to form bit lines and via plugs, thereby effectively reducing the complexity of process steps and Avoid misalignment. In addition, the manufacturing method of the damascene structure of NAND flash memory proposed by the present invention can simultaneously process the memory cell array and the peripheral area on the substrate, thus effectively reducing the process complexity and reducing the resistance value of the wires in the peripheral area.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

1 to 7C are flowcharts of manufacturing a damascene structure of a NAND flash memory according to a first embodiment of the present invention.

8A to 8G are cross-sectional views of the manufacturing process of the damascene structure of the NAND flash memory according to the second embodiment of the present invention.

9A to 9F are cross-sectional views of the manufacturing process of the damascene structure of the NAND flash memory according to the third embodiment of the present invention.

10A to 10D are cross-sectional views of the manufacturing process of the damascene structure of the NAND flash memory according to the fourth embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100, 200: Substrate

102, 202: memory cell array

104, 204: NAND string

106, 206: word line

107, 207: floating gate

108, 208: select transistor

109, 209: inter-gate dielectric layer

110, 210: gate oxide layer

111, 211: Partition wall

112, 212: first dielectric layer

114, 214, 314, 315: contact window plug

116, 216, 316: termination layer

118, 218, 318: second dielectric layer

122, 222, 322, 422: patterned termination layer

123, 125, 223, 225, 231, 233, 227, 323, 325, 331, 333, 327, 423, 425, 433, 427: opening

124, 224, 324, 424: third dielectric layer

126, 226, 326, 426: patterned mask layer

127: Groove

128, 228a, 228b, 328a, 328b, 428: vias

130, 230, 330, 430: conductor layer

203: Surrounding area

205: Transistor

205a: Grid

205b: gate dielectric layer

detailed description

1 to 7C are flowcharts of manufacturing a damascene structure of a NAND flash memory according to a first embodiment of the present invention.

First, referring to FIG. 1 , a substrate 100 having a memory cell array 102 thereon is provided, and the substrate 100 is, for example, a silicon substrate. In the B-B line direction, the memory cell array 102 is configured with a plurality of NAND strings 104, and each NAND string 104 includes a plurality of word lines 106, a floating gate 107 located below the word lines 106, and a plurality of word lines 106. Two selection transistors 108 at both ends, wherein the material of the word line 106 and the floating gate 107 is, for example, doped polysilicon. Between the word line 106 and the floating gate 107 there is an inter-gate dielectric layer 109 made of, for example, silicon oxide/silicon nitride/silicon oxide. In addition, a gate oxide layer 110 is formed between the substrate 100 and the memory cell array 102, and its material is, for example, silicon oxide, and its forming method includes thermal oxidation. In addition, although each NAND string 104 in FIG. 1 only shows two word lines 106, the present invention is not limited thereto.

Next, referring to FIG. 2 , a first dielectric layer 112 is formed on the substrate 100 to cover the memory cell array 102 . The material of the first dielectric layer 112 is, for example, silicon oxide, and its forming method includes performing a chemical vapor deposition process. Afterwards, a contact plug 114 contacting the substrate 100 is formed between two adjacent NAND strings 104 in the B-B line direction. The material of the contact plug 114 is, for example, metal tungsten, and its formation method is, for example, forming a contact opening (not shown) exposing a part of the substrate 100 in the first dielectric layer 112 and the gate oxide layer 110, and then The contact opening is filled with metal material to form the contact plug 114, but the invention is not limited thereto. In addition, before forming the first dielectric layer 112 , a spacer (spacer) 111 may also be optionally formed on the sidewall of the select transistor 108 , the material of which is, for example, silicon nitride. In this embodiment, the contact plug 114 is, for example, a bit line contact plug, and when the bit line contact plug is formed, a source line plug (not shown) of the NAND string 104 may also be formed. In addition, in FIG. 2 , although it is shown that there are five contact plugs 114 on the substrate 100 , the present invention is not limited thereto.

In addition, although the first dielectric layer 112 shown in FIG. 2 is higher than the partition walls 111 to cover the NAND strings 104, the present invention is not limited thereto; in other words, the top surface of the first dielectric layer 112 can be It is coplanar with the top surface of the partition wall 111 and just fills the gap between the NAND strings 104 .

After that, referring to FIG. 3 , a termination layer 116 and a second dielectric layer 118 are sequentially formed on the first dielectric layer 112 and the contact plug 114 . The material of the termination layer 116 is, for example, silicon nitride, and its formation method includes performing a chemical vapor deposition process. The second dielectric layer 118 is, for example, a silicon oxide layer, and its formation method includes performing a chemical vapor deposition process.

Then, referring to FIG. 4 , a patterned termination layer 122 is formed on the second dielectric layer 118 , which has at least one first opening 123 corresponding to the contact plug 114 and exposes a portion of the second opening corresponding to the first opening 123 . Dielectric layer 118 . The material of the patterned stop layer 122 is, for example, silicon nitride, and its formation method is, for example, depositing a layer of material on the second dielectric layer 118, and then performing a photolithographic etching process to form a layer of material in this material layer. The first opening 123 is formed.

5A, 5B and 5C, wherein FIG. 5A is a top view, FIG. 5B is a sectional view along the line B-B in FIG. 5A, and FIG. 5C is a sectional view along the line C-C in FIG. 5A. A third dielectric layer 124 is formed on the patterned stop layer 122 and in the first opening 123 . The third dielectric layer 124 is, for example, a silicon oxide layer, and its formation method includes performing a chemical vapor deposition process. Next, a patterned mask layer 126 is formed on the third dielectric layer 124, which has at least one second opening 125 corresponding to the first opening 123, and the second opening 125 is groove-shaped and exposes the corresponding second opening 125. part of the third dielectric layer 124 . The material of the patterned mask layer 126 is, for example, a photoresist material, and the second opening 125 is formed by a photolithography process. In other embodiments, the patterned mask layer 126 can also be a hard mask.

Then, please refer to FIG. 6A and FIG. 6B , which respectively show the same view of the next step in FIG. 5B and FIG. 5C . After using the patterned mask layer 126 as a mask to remove the part of the third dielectric layer 124 exposed from the second opening 125 to form the trench 127, continue to remove the part of the second dielectric layer exposed from the first opening 123. The layer 118 forms a via 128 and exposes a portion of the termination layer 116 corresponding to the first opening 123 . The removal method of part of the third dielectric layer 124 and part of the second dielectric layer 118 is, for example, a dry etching process.

7A, 7B and 7C, wherein FIG. 7A is a top view, FIG. 7B is a sectional view along the line B-B in FIG. 7A, and FIG. 7C is a sectional view along the line C-C in FIG. 7A. The exposed portion of the termination layer 116 is removed to expose the contact plug 114 , and the removal method of the portion of the termination layer 116 includes performing a dry etching process. Next, a conductive layer 130 is formed in the trench 127 and the via 128, and the conductive layer 130 is in contact with the contact plug 114, wherein the material of the conductive layer 130 is, for example, metal tungsten, and the forming method includes chemical vapor deposition. product technology. Then, the metal tungsten outside the trench 127 may be removed by a chemical mechanical polishing process (CMP). In addition, before forming the conductive layer 130 , the patterned mask layer 126 may be removed first, and the removal method includes performing a dry etching process. In this embodiment, the conductor layer 130 extending along the B-B line is used as a bit line of the NAND flash memory.

Based on the first embodiment, it can be seen that the above-mentioned manufacturing method of NAND flash memory sandwiches a layer of patterned stop layer 122 in the dielectric layer, and utilizes the high etching of the stop layer (such as silicon nitride) by the dielectric layer (such as silicon oxide) Select ratio, form the trench 127 and the via window 128 with a one-step etching process, and complete the filling of metal tungsten in one step, so it is a self-aligned dual damascene process, which effectively reduces the complexity of the process steps and avoids Quasi-miss.

8A to 8G are cross-sectional views of the manufacturing process of the damascene structure of the NAND flash memory according to the second embodiment of the present invention. It should be noted that the illustrations are only used for illustration, not to limit the present invention.

First, referring to FIG. 8A , a substrate 200 is provided. The substrate 200 is, for example, a silicon substrate, and it has a memory cell array 202 and a peripheral region 203, wherein the peripheral region 203 includes at least one transistor 205, and the transistor 205 is formed by a gate dielectric layer. 205b and the gate 205a on the gate dielectric layer 205b. In addition, in the cross-sectional direction, the memory cell array 202 is configured with a plurality of NAND strings 204, and each NAND string 204 includes a plurality of word lines 206, a plurality of floating gates 207 located below the word lines 206, and a plurality of floating gates 207 located under the word lines 206. The two selection transistors 208 at both ends of the word line 206 , wherein the material of the word line 206 and the floating gate 207 is, for example, doped polysilicon, can be formed together with the gate 205 a of the peripheral region 203 . An inter-gate dielectric layer 209 is further included between the word line 206 and the floating gate 207, and its material is, for example, silicon oxide/silicon nitride/silicon oxide. In addition, a gate oxide layer 210 is formed between the substrate 200 and the memory cell array 202, and its material is, for example, silicon oxide. Class craft formation. In addition, although each NAND string 204 in FIG. 8A only shows two word lines 206, and the peripheral area 203 only shows one transistor 205, but the present invention is not limited thereto.

Next, referring to FIG. 8B , a first dielectric layer 212 is formed on the substrate 200 to cover the memory cell array 202 and the transistor 205 in the peripheral region 203 . The material of the first dielectric layer 212 is, for example, silicon oxide, and its forming method includes performing a chemical vapor deposition process. In addition, before forming the first dielectric layer 212 , a spacer wall 211 may be optionally formed on the sidewalls of the select transistor 208 and the transistor 205 , the material of which is, for example, silicon nitride. In addition, although the first dielectric layer 212 shown in FIG. 8B is higher than the partition walls 211 to cover the NAND strings 204, the present invention is not limited thereto; in other words, the top surface of the first dielectric layer 212 can be It is coplanar with the top surface of the partition wall 211 and just fills the gap between the NAND strings 204 . Afterwards, a first contact plug 214 contacting the substrate 200 is formed between two adjacent NAND strings 204 in the cross-sectional direction. The material of the first contact plug 214 is, for example, metal tungsten, and its formation method is, for example, forming a contact opening (not shown) in the first dielectric layer 212 and the gate oxide layer 210 exposing part of the substrate 200 , Then, metal material is filled in the contact opening to form the first contact plug 214, but the invention is not limited thereto. In this embodiment, the first contact plug 214 is, for example, a bit line contact plug, and when the bit line contact plug is formed, a source line plug (not shown) of the NAND string 204 can also be formed. ).

After that, referring to FIG. 8C , a termination layer 216 and a second dielectric layer 218 are sequentially formed on the first dielectric layer 212 and the first contact plug 214 . The material of the termination layer 216 is, for example, silicon nitride, and its formation method includes performing a chemical vapor deposition process. The second dielectric layer 218 is, for example, a silicon oxide layer, and its formation method includes performing a chemical vapor deposition process.

Then, referring to FIG. 8D, a patterned stop layer 222 is formed on the second dielectric layer 218, which has at least one first opening 223 corresponding to the first contact plug 214 and at least one second opening located in the peripheral region 203. 231 , and expose a portion of the second dielectric layer 218 corresponding to the first opening 223 and the second opening 231 . The material of the patterned stop layer 222 is, for example, silicon nitride, and its formation method is, for example, depositing a layer of material on the second dielectric layer 218, and then performing a photolithographic etching process to form a layer of material in the material layer. A first opening 223 and a second opening 231 are formed. Afterwards, a third dielectric layer 224 is formed on the patterned stop layer 222 and in the first opening 223 and the second opening 231 . The third dielectric layer 224 is, for example, a silicon oxide layer, and its formation method includes performing a chemical vapor deposition process. In addition, although the second opening 231 in FIG. 8D is shown above the transistor 205 in the peripheral region 203 , the present invention is not limited thereto.

Next, referring to FIG. 8E, a patterned mask layer 226 is formed on the third dielectric layer 224, which has at least one third opening 225 corresponding to the first opening 223 and extending along the cross-sectional direction on the memory cell array 202, and There is at least one fourth opening 233 corresponding to the second opening 231 in the peripheral region 203 and exposing part of the third dielectric layer 224 . The material of the patterned mask layer 226 is, for example, a photoresist material, and the third opening 225 and the fourth opening 233 are formed by a photolithography process, but the invention is not limited thereto. In other embodiments, the patterned mask layer 226 can also be a hard mask. Wherein, the dotted line in Fig. 8E represents the contour of the patterned mask layer 226 in the direction parallel to the cross-section; Examples are shown in Figure 5A and Figure 5C.

Then, referring to FIG. 8F , using the patterned mask layer 226 as a mask, the part of the third dielectric layer 224 exposed from the third opening 225 and the fourth opening 233 is removed to form trenches on the memory cell array 202 and Form an opening 227 in the peripheral area 203, and continue to remove a part of the second dielectric layer 218 exposed from the first opening 223 and the second opening 231 to form a via 228a on the memory cell array 202 and form a via in the peripheral area 203. The layer window 228b exposes a portion of the termination layer 216 . The method for removing part of the third dielectric layer 224 and part of the second dielectric layer 218 is, for example, a dry etching process. Wherein, the trenches in the memory cell array 202 in FIG. 8F are parallel to the cross-sectional direction, such as the trenches 127 shown in FIG. 6B in the first embodiment.

Afterwards, referring to FIG. 8G , the exposed part of the termination layer 216 is removed to expose the first contact plug 214 , and the first dielectric layer 212 of the peripheral region 203 is also exposed. A method for removing part of the stop layer 216 includes performing a dry etching process. Next, a conductive layer 230 is formed in the trenches, openings 227 and vias 228a-b, and the conductive layer 230 is in contact with the first contact plug 214, wherein the material of the conductive layer 230 is metal tungsten, and it is formed The method includes performing a chemical vapor deposition process. Then, the metal tungsten outside the groove and the opening 227 can be removed by a chemical mechanical polishing process. In addition, before the conductive layer 230 is formed, the patterned mask layer 226 may be removed first, and the removal method includes performing a dry etching process. In this embodiment, the conductor layer 230 extending along the cross-sectional direction on the memory cell array 202 is used as a bit line of the NAND flash memory, and the conductor layer 230 in the peripheral region 203 can be used as an interconnection.

Likewise, in the second embodiment, the bit lines and the via plugs in contact with the contact plugs are formed by a self-aligned dual damascene process, thereby effectively reducing process complexity and avoiding misalignment. In addition, in the second embodiment, because the bit line and the interconnection of the NAND flash memory are produced in the same steps, not only does not increase the complexity of the process, but the resistance value can be reduced by increasing the depth of the interconnection.

9A to 9F are cross-sectional views of the manufacturing process of the damascene structure of the NAND flash memory according to the third embodiment of the present invention. Wherein, FIG. 9A shows the steps performed after the continuation of FIG. 8A. In addition, the same or similar components in the third embodiment and the second embodiment can be made using the same materials or methods, so details will not be repeated here.

First, referring to FIG. 9A , a first contact plug 314 contacting the substrate 200 is formed between two adjacent NAND strings 204 in the cross-sectional direction, and at least one side of the transistor 205 in the peripheral region 203 is formed at the same time. The second contact plug 315 of the substrate 200 is contacted. The material of the first contact plug 314 and the second contact plug 315 is, for example, metal tungsten, and the formation method thereof can refer to the above-mentioned embodiments. In this embodiment, the first contact plug 314 is, for example, a bit line contact plug, and when the bit line contact plug is formed, a source line plug (not shown) of the NAND string 204 can also be formed. ); the second contact plug 315 can be connected to the source/drain of the transistor 205 (not shown).

Next, referring to FIG. 9B , a termination layer 316 and a second dielectric layer 318 are sequentially formed on the first dielectric layer 212 , the first contact plug 314 and the second contact plug 315 . The material of the termination layer 316 is, for example, silicon nitride, and its formation method can refer to the above-mentioned embodiments. The second dielectric layer 318 is, for example, a silicon oxide layer, and its formation method can also refer to the above-mentioned embodiments.

Then, referring to FIG. 9C, a patterned stop layer 322 is formed on the second dielectric layer 318, which has at least one first opening 323 corresponding to the first contact plug 314 and a second contact plug corresponding to the peripheral region 203. Plug at least one fifth opening 331 of the plug 315 and expose a portion of the second dielectric layer 318 corresponding to the first opening 323 and the fifth opening 331 . The material of the patterned stop layer 322 is, for example, silicon nitride, and its formation method is, for example, depositing a layer of material on the second dielectric layer 318, and then performing a photolithographic etching process to form a layer of material in this material layer. A first opening 323 and a fifth opening 331 are formed.

Afterwards, a third dielectric layer 324 is formed on the patterned stop layer 322 and in the first opening 323 and the fifth opening 331 . The third dielectric layer 324 is, for example, a silicon oxide layer, and its formation method can refer to the above-mentioned embodiments.

Next, referring to FIG. 9D, a patterned mask layer 326 is formed on the third dielectric layer 324, which has at least one third opening 325 corresponding to the first opening 323 and extending along the cross-sectional direction on the memory cell array 202, and There is at least one sixth opening 333 corresponding to the fifth opening 331 in the peripheral region 203 and exposing part of the third dielectric layer 324 . The material and formation method of the patterned mask layer 326 can refer to the above-mentioned embodiments. Wherein, the dotted line in FIG. 9D represents the outline of the patterned mask layer 326 in the direction parallel to the cross-section; Examples are shown in Figure 5A and Figure 5C. In addition, the sixth opening 333 can not only extend in the direction through the page as shown in FIG. 9D , but also can be changed to extend in the cross-sectional direction according to design requirements.

Then, referring to FIG. 9E , using the patterned mask layer 326 as a mask, part of the third dielectric layer 324 exposed from the third opening 325 and the sixth opening 333 is removed to form trenches on the memory cell array 202 and Form the opening 327 in the peripheral region 203, and continue to remove the part of the second dielectric layer 318 exposed from the first opening 323 and the fifth opening 331 to form a via 328a on the memory cell array 202 and form a via in the peripheral region 203. The layer window 328b exposes a portion of the termination layer 316 . The method for removing part of the third dielectric layer 324 and part of the second dielectric layer 318 is, for example, a dry etching process. Wherein, the trenches in the memory cell array 202 in FIG. 9E are parallel to the cross-sectional direction, such as the trenches 127 shown in FIG. 6B in the first embodiment.

Afterwards, referring to FIG. 9F , the exposed part of the termination layer 316 is removed to expose the first contact plug 314 , and at this time the second contact plug 315 is also exposed. A method for removing part of the stop layer 316 includes performing a dry etching process. Next, a conductive layer 330 is formed in the trenches, openings 327 and vias 328a-b, and the conductive layer 330 is in contact with the first contact plug 314 and the second contact plug 315, and the material of the conductive layer 330 is compatible with For the forming method, reference may be made to the above-mentioned embodiments. In addition, before forming the conductive layer 330 , the patterned mask layer 326 may be removed first, and the removal method includes performing a dry etching process. In this embodiment, the conductor layer 330 extending along the cross-sectional direction on the memory cell array 202 serves as a bit line of the NAND flash memory, and the conductor layer 330 in the peripheral region 203 serves as an interconnection.

Likewise, in the third embodiment, the bit lines and the via plugs in contact with the contact plugs are formed through a self-aligned dual damascene process, thereby effectively reducing process complexity and avoiding misalignment. In addition, in the third embodiment, because the bit line and the interconnection of the NAND flash memory are manufactured using consistent steps, the process complexity will not be increased, thereby saving the process cost.

10A to 10D are cross-sectional views of the manufacturing process of the damascene structure of the NAND flash memory according to the fourth embodiment of the present invention. Wherein, FIG. 10A shows the steps performed after the continuation of FIG. 9B. In addition, the same or similar components in the fourth embodiment and the third embodiment can be made using the same materials or methods, so details are not repeated here.

First, referring to FIG. 10A, a patterned termination layer 422 is formed on the second dielectric layer 318, which has at least one first opening 423 corresponding to the first contact plug 314, and exposes a portion corresponding to the first opening 423. The second dielectric layer 318 . Afterwards, a third dielectric layer 424 is formed on the patterned stop layer 422 and in the first opening 423 .

Next, referring to FIG. 10B, a patterned mask layer 426 is formed on the third dielectric layer 424, which has at least one third opening 425 corresponding to the first opening 423 and extending along the cross-sectional direction on the memory cell array 202, and There is at least one seventh opening 433 corresponding to the second contact plug 315 in the peripheral region 203 and exposing part of the third dielectric layer 424 . Wherein, the dotted line in Fig. 10B represents the outline of the patterned mask layer 426 in the direction parallel to the section; Examples are shown in Figure 5A and Figure 5C. In addition, the seventh opening 433 can not only extend in the direction through the page as shown in FIG. 10B , but also can be changed to extend in the cross-sectional direction according to design requirements.

Then, referring to FIG. 10C , using the patterned mask layer 426 as a mask, a part of the third dielectric layer 424 exposed from the third opening 425 and the seventh opening 433 is removed to form trenches on the memory cell array 202 and An opening 427 is formed in the peripheral region 203 , and a portion of the second dielectric layer 318 exposed from the first opening 423 is continuously removed to form a via 428 on the memory cell array 202 , exposing a portion of the stop layer 316 . Wherein, the trenches in the memory cell array 202 in FIG. 10C are parallel to the cross-sectional direction, such as the trenches 127 shown in FIG. 6B in the first embodiment.

Afterwards, referring to FIG. 10D , the exposed part of the termination layer 316 is removed to expose the first contact plug 314 , and the second dielectric layer 318 of the peripheral region 203 is also exposed. Next, a conductive layer 430 is formed in the trench, the opening 427 and the via 428 , and the conductive layer 430 is in contact with the first contact plug 314 . In addition, before forming the conductive layer 430 , the patterned mask layer 426 can also be removed first. In this embodiment, the conductor layer 430 extending along the cross-sectional direction on the memory cell array 202 is used as a bit line of the NAND flash memory, and the conductor layer 430 in the peripheral region 203 can be used as an interconnection.

Likewise, in the fourth embodiment, the bit lines and the via plugs in contact with the contact plugs are formed by a self-aligned dual damascene process, thereby effectively reducing process complexity and avoiding misalignment. In addition, in the fourth embodiment, because the bit line and the interconnection of the NAND flash memory are produced in the same steps, the process complexity will not be increased, thereby saving the process cost.

In addition, the manufacturing method of the damascene structure of the NAND flash memory of the present invention can selectively use the second embodiment, the third embodiment and the fourth embodiment in combination with respect to the circuit design of the peripheral region.

To sum up, the method for manufacturing the damascene structure of the NAND flash memory proposed in the above embodiment adopts the self-aligned dual damascene process, and forms the trench and the via in one step, thereby forming the bit line and the contact with the contact plug. The via hole plug effectively reduces the complexity of the process steps and avoids misalignment. In addition, the manufacturing method of the damascene structure of NAND flash memory proposed in the above-mentioned embodiment can use consistent steps to manufacture the bit line and interconnection of NAND flash memory, thereby reducing the complexity of process steps and process cost, and can increase the interconnection of peripheral regions. Even the depth, and reduce its resistance.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention shall be defined by the scope of the appended patent claims.

Claims (19)

1. a manufacture method for the mosaic texture of nand flash memory, including:

Thering is provided a substrate, have a memory cell array, this memory cell array includes along a direction configuration Multiple NAND string, the most in the direction, respectively this NAND string include multiple wordline and be positioned at this Multiple floating grids below multiple wordline, and position is at two selection crystal at the two ends of the plurality of wordline Pipe；

Forming one first dielectric layer on this substrate, this first dielectric layer covers this memory cell array；

At least one contact window plug contacting this substrate is formed between neighbouring respectively this NAND string；

A stop layer is formed on this first dielectric layer and this contact window plug；

One second dielectric layer is formed on this stop layer；

Forming a patterning stop layer on this second dielectric layer, this patterning stop layer has connecing Touch at least one first opening of window connector and expose this second dielectric layer；

One the 3rd dielectric layer is formed on this patterning stop layer and in this first opening；

On the 3rd dielectric layer, form a patterned mask layer, have to should the first opening at least one Second opening, this second opening extends in the direction, and this second opening exposes the 3rd dielectric layer；

With this patterned mask layer as mask, remove the 3rd dielectric layer and shape exposed from this second opening Become a groove, and continue to remove this second dielectric layer exposed from this first opening and form an interlayer hole also Expose this stop layer；

Remove this stop layer exposed, make this contact window plug come out；And

Forming a conductor layer in this groove and this interlayer hole, this conductor layer contacts with this contact window plug.

2. the manufacture method of the mosaic texture of nand flash memory as claimed in claim 1, wherein this One dielectric layer, this second dielectric layer and the 3rd dielectric layer are silicon oxide layer.

3. the manufacture method of the mosaic texture of nand flash memory as claimed in claim 1, wherein this is whole Only the material of layer and this patterning stop layer is silicon nitride.

4. the manufacture method of the mosaic texture of nand flash memory as claimed in claim 1, is wherein formed The step of this conductor layer includes filling up this interlayer hole and forming an interlayer hole connector, and fills up this groove and shape Become a bit line.

5. the manufacture method of the mosaic texture of nand flash memory as claimed in claim 1, is wherein formed Also include before the step of this conductor layer removing this patterned mask layer.

6. the manufacture method of the mosaic texture of nand flash memory as claimed in claim 1, wherein in shape Before becoming this first dielectric layer, also include at least on the sidewall of respectively this selection transistor, forming an interval Wall.

7. the manufacture method of the mosaic texture of nand flash memory as claimed in claim 6, between being wherein somebody's turn to do The material in next door is silicon nitride.

8. a manufacture method for the mosaic texture of nand flash memory, including:

Thering is provided a substrate, have a memory cell array and a surrounding zone, wherein this surrounding zone includes at least One transistor, this memory cell array includes the multiple NAND string along a direction configuration, and in the direction On, respectively this NAND string includes multiple wordline and is positioned at the multiple floating grids below the plurality of wordline, with And position is at two selection transistors at the two ends of the plurality of wordline；

Forming one first dielectric layer on this substrate, this first dielectric layer covers this memory cell array and is somebody's turn to do This transistor of surrounding zone；

At least one first contact window plug contacting this substrate is formed between neighbouring respectively this NAND string；

A stop layer is formed on this first dielectric layer and this first contact window plug；

One second dielectric layer is formed on this stop layer；

Forming a patterning stop layer on this second dielectric layer, this patterning stop layer has should the At least one first opening of one contact window plug and at least one second opening being positioned at this surrounding zone, and expose This second dielectric layer；

One the 3rd dielectric is formed on this patterning stop layer and in this first opening and this second opening Layer；

On the 3rd dielectric layer, form a patterned mask layer, wherein have should the first opening and edge At least one the 3rd opening that the direction extends, and to should at least one the 4th opening of the second opening, and Expose the 3rd dielectric layer；

With this patterned mask layer as mask, remove expose from the 3rd opening and the 4th opening this Three dielectric layers and form a groove, and continue to remove expose from this first opening and this second opening this Two dielectric layers and form an interlayer hole and expose this stop layer；

Remove this stop layer exposed, make this first contact window plug come out and expose this surrounding zone This first dielectric layer；And

Forming a conductor layer in this groove with this interlayer hole, this conductor layer connects with this first contact window plug Touch.

9. the manufacture method of the mosaic texture of nand flash memory as claimed in claim 8, is wherein formed The step of this patterning stop layer includes making this second opening corresponding on this transistor of this surrounding zone.

10. the manufacture method of the mosaic texture of nand flash memory as claimed in claim 8, is wherein formed The step of this first contact window plug is included at least side formation of this transistor in this surrounding zone and connects Touch at least one second contact window plug of this substrate.

The manufacture method of the mosaic texture of 11. nand flash memories as claimed in claim 10, wherein shape The step becoming this patterning stop layer includes making this patterning stop layer to have should in this surrounding zone At least one the 5th opening of the second contact window plug.

The manufacture method of the mosaic texture of 12. nand flash memories as claimed in claim 11, wherein shape The step becoming this patterned mask layer includes making this patterned mask layer to have should in this surrounding zone At least one the 6th opening of the 5th opening.

The manufacture method of the mosaic texture of 13. nand flash memories as claimed in claim 10, wherein shape The step becoming this patterned mask layer includes making this patterned mask layer to have should in this surrounding zone At least one the 7th opening of the second contact window plug.

The manufacture method of the mosaic texture of 14. nand flash memories as claimed in claim 13, wherein with This patterned mask layer is mask, removes the 3rd dielectric layer exposed from the 7th opening and forms a ditch Groove.

The manufacture method of the mosaic texture of 15. nand flash memories as claimed in claim 8, wherein this One dielectric layer, this second dielectric layer and the 3rd dielectric layer are silicon oxide layer.

The manufacture method of the mosaic texture of 16. nand flash memories as claimed in claim 8, wherein this is whole Only the material of layer and this patterning stop layer is silicon nitride.

The manufacture method of the mosaic texture of 17. nand flash memories as claimed in claim 8, is wherein formed Also include before the step of this conductor layer removing this patterned mask layer.

The manufacture method of the mosaic texture of 18. nand flash memories as claimed in claim 8, wherein in shape Before becoming this first dielectric layer, also include at least shape on the sidewall of respectively this selection transistor and this transistor Become a spaced walls.

The manufacture method of the mosaic texture of 19. nand flash memories as claimed in claim 18, wherein should The material of spaced walls is silicon nitride.