CN100380628C - Method for manufacturing semiconductor element and method for manufacturing plug - Google Patents

Abstract

A method for manufacturing a semiconductor device is suitable for a substrate, wherein a first conductive structure and a first dielectric layer are formed on the substrate, and the first conductive structure is covered by the first dielectric layer. The method is described as follows: first, a second conductive structure is formed on the substrate beside the first conductive structure. And then, the second conductive structure is reduced, so that the upper surface of the second conductive structure is relatively lower than the upper surface of the first conductive structure. Then, a second dielectric layer is formed on the substrate, and the second dielectric layer covers the first conductive layer structure and the second conductive structure. Then, a via opening is formed in the second dielectric layer, and the via opening exposes the upper surface of the first conductive structure. Finally, a via plug is formed in the via opening.

Description

Manufacturing method of semiconductor element and manufacturing method of plug

technical field

The invention relates to a semiconductor process method, in particular to an interconnection manufacturing method suitable for the semiconductor element process.

Background technique

With the integration level of integrated circuits getting higher and higher, semiconductor elements are developing toward miniaturization, so the dimensions of components, such as wire width, gate size, and plug size, must be reduced to increase their integration level. However, with the miniaturization of the components, the difficulty of the process is also greatly increased, and the requirement for dimensional precision is also increased.

Existing photolithography and etching processes are used to form an exposed source/drain region or a gate above a storage element (such as a flash memory) or an interconnection line (such as a wire) in a dielectric layer. The contact window opening, or a via window opening that exposes the upper surface of the interconnection line, due to the improvement of component integration and the smaller and smaller component sizes, when there is an alignment problem in the photolithography process, this opening is formed. The steps (photolithography and etching process) are prone to errors, so that the opened openings are exposed, and the surface of other components adjacent to the intended exposed source/drain region, gate or interconnection line .

Please refer to FIG. 1 , which is a schematic cross-sectional view of a contact opening for an exposed gate and a contact opening for an exposed drain region formed above the trench flash memory. The existing method of forming contact openings to expose the drain region and the gate of the trench flash memory respectively includes, on the substrate 100 having a trench gate structure 102, sequentially forming a covering trench gate structure 102 A gate dielectric layer 104, a select gate 106 is formed on the gate dielectric layer 104 on the sidewall of the trench gate structure 102 and above the substrate 100, and a spacer is formed on the sidewall of the select gate 108. Subsequently, a drain region 110 is formed in the substrate 100 on both sides of the trench gate structure 102 and the select gate 106 . Afterwards, a dielectric layer 112 is formed on the substrate 100, followed by a photolithographic etching process, in the dielectric layer 112, a contact window opening 114 exposing the drain 110 and the trench gate 102 are formed. A contact window opening 116 .

As shown in FIG. 1, due to the shrinking of the device size, when the photolithography process has misalignment problems, or the alignment accuracy is insufficient, the opened contact window openings 114 and 116, in addition to exposing the predetermined exposed trench type The surface of the gate structure and the surface of the drain region also expose part of the surface 106a of the adjacent selection gate 106 . In this way, when contact plugs are subsequently formed in the contact openings 114 and 116, the formed contact plugs will be abnormally electrically connected to the exposed selection gate 106, causing leakage current or even abnormality of the device. electrical performance.

Contents of the invention

The object of the present invention is to provide a manufacturing method of a semiconductor element, so that the height of the conductive element not intended to be electrically connected to the upper conductive structure is lower than the conductive element intended to be electrically connected to the upper conductive structure. In this way, the problem of leakage current or abnormal electrical performance caused by abnormal conduction between the subsequently formed plug and the conductive element that is not intended to be electrically connected to the upper layer conductive structure can be avoided.

The invention provides a manufacturing method of a semiconductor element, the method includes: providing a substrate on which a first conductive structure has been formed, and forming a first dielectric layer on the first conductive structure. forming a second conductive structure and a spacer on the sidewall of the first conductive structure covered with the first dielectric layer, wherein the second conductive structure is located between the spacer and the first conductive structure and between the spacer and the base . removing the exposed part of the second conductive structure, so that an upper surface of the second conductive structure is lower than an upper surface of the first conductive structure, so as to form a first recess between the spacer and the first conductive structure, and The second conductive structure between the spacer and the base is retracted toward the sidewall of the first conductive structure to form a second recess. A second dielectric layer is formed on the substrate and fills up the first recess and the second recess. A via opening is formed in the second dielectric layer to expose the upper surface of the first conductive structure. A plug is formed in the via opening.

According to the method for manufacturing a semiconductor element described in a preferred embodiment of the present invention, wherein the method for removing part of the second conductive structure includes a wet etching process, and the wet etching process uses an etching solution comprising ammonia water-hydrogen peroxide solution, And the composition ratio of ammonia water, hydrogen peroxide and water is about 1-5:1:100-500, and the temperature of the ammonia water-hydrogen peroxide solution is, for example, 70-90°C. In addition, the material forming the second conductive structure has a different etching selectivity from the material of the first dielectric layer and the spacer. In addition, the material of the second conductive structure includes polysilicon, metal silicide or polysilicon/silicon tungsten.

The present invention proposes a method for manufacturing a contact plug in a trench flash memory process, which is suitable for a substrate having a trench flash memory. The trench flash memory includes a source/drain region located in the substrate, A trench gate structure located in the base and protruding from a surface of the base, a gate dielectric layer covering the trench gate structure, located on the side of the trench gate structure covered with the gate dielectric layer A selection gate and a spacer on the wall, wherein the selection gate is located between the spacer and the trench gate structure and between the spacer and the substrate, the method includes: removing the exposed part of the selection gate, making the selection An upper surface of the gate is relatively lower than an upper surface of the trench gate structure, so as to form a first recess between the spacer and the trench gate structure, and is located between the spacer and the substrate toward the selection gate. The direction of the sidewall of the trench gate structure shrinks inwards to form a second recess. On the substrate, a dielectric layer is formed to cover the trench flash memory and fill the first recess and the second recess. In the dielectric layer, a first contact opening and a second contact opening are formed, wherein the first contact opening exposes the source/drain region, and the second contact opening exposes the upper trench gate structure surface. A first contact plug and a second contact plug are respectively formed in the first contact opening and the second contact opening.

According to the method of manufacturing the plug according to the preferred embodiment of the present invention, wherein the method of removing part of the select gate includes a wet etching process, and the wet etching process uses an etching solution including ammonia water-hydrogen peroxide solution, and The composition ratio of ammonia water, hydrogen peroxide and water is about 1-5:1:100-500, and the temperature of the ammonia water-hydrogen peroxide solution is, for example, 70-90°C. In addition, the material forming the select gate has a different etching selectivity from the material of the gate dielectric layer and the spacer. In addition, the material of the select gate includes polysilicon, metal silicide or polysilicon/silicon tungsten.

The present invention proposes a method for manufacturing a plug, which is applicable to a substrate on which a first conductive structure and a first dielectric layer are formed, and the dielectric layer covers the first conductive structure. The method includes: A second conductive structure is formed above the base next to the conductive structure. The second conductive structure is shrunk so that an upper surface of the second conductive structure is relatively lower than an upper surface of the first conductive structure. A second dielectric layer is formed on the base and covers the first conductive layer structure and the second conductive structure. In the second dielectric layer, a required via opening is formed, and a via plug is formed.

According to the method of manufacturing the plug described in the preferred embodiment of the present invention, wherein the method for reducing the size of the second conductive structure includes a wet etching process, and the wet etching process uses an etching solution comprising ammonia water-hydrogen peroxide solution, and ammonia water, The composition ratio of hydrogen peroxide and water is about 1-5:1:100-500. In addition, the material forming the second conductive structure has a different etch selectivity than the material of the dielectric layer. In addition, the material of the second conductive structure includes polysilicon, metal silicide or polysilicon/silicon tungsten.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the preferred embodiments are exemplified below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a conventional contact opening for an exposed gate and a contact opening for an exposed drain region formed above a trench flash memory.

2A to 2D are cross-sectional views of a method of manufacturing a plug according to a preferred embodiment of the present invention, which is formed in a dielectric layer and electrically connected to components of trench flash memory.

3A to 3D are cross-sectional views of a method of manufacturing a plug according to a preferred embodiment of the present invention, which is formed in a dielectric layer and electrically connected to an underlying conductive structure.

simple notation

100, 300, 400: Base

102, 302: Trench gate structure

104, 304: gate dielectric layer

106, 306a, 306b: select gates

106a: Surface of the select gate

108, 308, 308a, 408, 408a: Spacers

110, 310: drain area

112, 311, 312, 404, 411, 412: dielectric layer

114, 116, 314, 316: contact window opening

424: opening

306, 406: conductive layer

307a, 307b, 407a, 407b: depression

326, 328: contact window plug

420, 406a, 406b: conductive structures

426: plug

Detailed ways

first embodiment

According to the present invention, a preferred embodiment is provided, applying the plug manufacturing method of the present invention to the process of trench flash memory. However, the present invention is not limited to be used only in the process of trench flash memory. The method of the present invention can be applied as long as a plug forms an electrical connection with one of the underlying adjacent components in the dielectric layer.

2A to 2D are cross-sectional views of a method of manufacturing a plug according to a preferred embodiment of the present invention, which is formed in a dielectric layer and electrically connected to components of trench flash memory.

2A, a substrate 300 with a trench gate structure 302 is provided, wherein the trench gate structure 302 may include a tunnel oxide layer (not shown), a floating gate (not shown) , an inter-gate dielectric layer (not shown) and a control gate. Next, a gate dielectric layer 304 is formed on the substrate 300 and covers the trench gate structure 302 , wherein the material of the gate dielectric layer 304 is, for example, silicon oxide. Next, a conductive layer 306 is formed on the gate dielectric layer 304 . The material of the conductive layer 306 is polysilicon or silicide, preferably polysilicon/silicontungsten. After that, an insulating layer (not shown) is formed on the conductive layer 306 , and then part of the insulating layer is removed to form a spacer 308 on the sidewall of the conductive layer 306 . The material of the spacer 308 is, for example, silicon nitride. It should be noted that the material forming the spacer 308 and the material forming the gate dielectric layer 304 have obvious difference in etching ratio with respect to the material forming the conductor layer 306 .

Referring to FIG. 2B , part of the conductive layer 306 and part of the spacer 308 are removed to expose the gate dielectric layer 304 above the trench gate structure 302 and part of the substrate 300 , and the selection gate 306 a and the spacer are formed. 308a. That is, the select gate 306 a is located between the spacer 308 a and the trench gate structure 302 , and between the spacer 308 a and the substrate 300 . Wherein, the method for removing part of the conductor layer 306 and part of the spacer 308 includes performing an anisotropic etching step.

Referring to FIG. 2C , an etching process is performed to remove part of the select gate 306 a to form a select gate 306 b with a lower height compared to the spacer 308 a and the upper surface of the trench gate 302 . At the same time, relative to the spacer 308 a , the selection gate 306 b located below the spacer 308 a shrinks inward toward the sidewall of the trench gate structure 302 . That is, an upper surface of the select gate 306b is relatively lower than an upper surface of the trenched gate structure 302, so as to form a recess 307a between the spacer 308a and the trenched gate structure 302, and is located at the spacer 308 a and the select gate 306 b of the substrate 300 are retracted toward the sidewall of the trench gate structure 302 to form a recess 307 b. Wherein, the etching step includes performing an isotropic wet etching process with ammonia water-hydrogen peroxide solution, wherein the composition ratio of ammonia water, hydrogen peroxide and water in the ammonia water-hydrogen peroxide solution is about 1-5:1 : 100-500, and the temperature of the ammonia water-hydrogen peroxide solution is preferably between 70-90°C. It should be noted that the method for removing part of the selection gate 306a here uses an etching method that has a relatively large etching selectivity for the material forming the selection gate 306b (that is, the material forming the conductive layer 306), Therefore, a portion of the select gate 306 a can be selectively removed to form the select gate 306 b without affecting the spacer 308 a and the exposed gate dielectric layer 304 .

Next, a drain region 310 is formed in the substrate 300 on both sides of the trenched gate structure 302 , the select gate 306 b and the spacer 308 a. Afterwards, a dielectric layer 311 is formed on the substrate 300 to fill the recesses 307a and 307b. The material of the dielectric layer 311 is, for example, silicon nitride. Next, a dielectric layer 312 is formed on the dielectric layer 311 .

Referring to FIG. 2D , a planarization process, photolithography and etching process are sequentially performed to form contact windows 314 and 316 in the dielectric layers 312 and 311 . The contact window 314 exposes the surface of the drain region 310 , and the contact window exposes the upper surface of the trenched gate 302 . After that, contact plugs 328 and 326 electrically connected to the trenched gate structure 302 and the drain region 310 are formed in the contact openings 314 and 316 .

In an embodiment of the present invention, the material of the gate dielectric layer 304 is, for example, silicon oxide, the material of the dielectric layer 311 is, for example, silicon nitride, and the material of the dielectric layer 312 is, for example, silicon oxide. When forming the contact window 316, for example, the dielectric layer 311 is used as the etch stop layer first, and part of the dielectric layer 312 is removed; then the gate dielectric layer 304 is used as the etch stop layer, and part of the dielectric layer 311 is removed; A portion of the gate dielectric layer 304 is then removed to expose the trenched gate structure 302 . For the adjacent selection gate 306b and the trench gate structure 302, the height of the select gate 306b is relatively low, so when the contact window opening 316 is opened to expose the upper surface of the trench gate structure 302, even light Misalignment occurs in the engraving process, causing the position of the contact window opening to shift, and the opened contact window opening 316 will not expose the select gate 306 b adjacent to the trench gate structure 302 .

Similarly, since the selection gate 306b retracts toward the sidewall of the trench gate structure 302 relative to the spacer 308a, when the contact opening 314 is opened to expose the upper surface of the drain region 310, even The misalignment of the photolithography process causes the position of the contact opening to shift, and the opened contact opening 314 will not expose the select gate 306 b adjacent to the drain region 310 . In this way, the contact plugs 326 and 328 subsequently formed in the contact openings 314 and 316 will not form abnormalities with components that are not intended to be electrically connected (such as the select gate 306b in this embodiment). electrical connection. Therefore, it can solve the existing problem of leakage current or abnormal electrical performance caused by abnormal electrical connection of adjacent components when the integration of components is improved, and the photolithography process is misaligned or the alignment accuracy is insufficient. In addition, in the trench flash memory, the insulation capability between the select gate and the trench gate structure can be improved.

In the above embodiments, the method for forming the plug 326 may also be formed by using a self-aligned contact window process.

second embodiment

According to the present invention, a preferred embodiment is provided, which applies the plug manufacturing method of the present invention to the interconnection process. However, the present invention is not limited to be used only in the interconnection process. The method of the present invention can be applied as long as a plug forms an electrical connection with one of the underlying adjacent components in the dielectric layer.

3A to 3D are cross-sectional views of a method of manufacturing a dual damascene plug formed in a dielectric layer and electrically connected to an underlying conductive structure according to a preferred embodiment of the present invention.

Referring to FIG. 3A , a substrate 400 having a conductive structure 420 is provided. Next, a dielectric layer 404 is formed on the substrate 400 and covers the conductive structure 420 , wherein the material of the dielectric layer 404 is, for example, silicon oxide. Next, a conductive layer 406 is formed on the dielectric layer 404. The material of the conductive layer 406 is polysilicon or silicide, preferably polysilicon/silicon tungsten. After that, an insulating layer (not shown) is formed on the conductive layer 406 , and then part of the insulating layer is removed to form a spacer 408 on the sidewall of the conductive layer 406 . The material of the spacer 408 is, for example, silicon nitride. It should be noted that the material forming the spacer 408 and the material forming the dielectric layer 404 have obvious difference in etching ratio compared to the material forming the conductor layer 406 .

Referring to FIG. 3B , a portion of the conductive layer 406 and a portion of the spacer 408 are removed to expose the dielectric layer 404 above the conductive structure 420 and a portion of the substrate 400 , and the conductive structure 406 a and the spacer 408 a are formed. That is, the conductive structure 406 a is located between the spacer 408 a and the conductive structure 420 and between the spacer 408 a and the substrate 400 . Wherein, the method for removing part of the conductor layer 406 and part of the spacer 408 includes performing an anisotropic etching step.

Referring to FIG. 3C , an etching process is performed to remove part of the conductive structure 406 a to form a conductive structure 406 b with a lower height compared to the spacer 408 a and the upper surface of the conductive structure 420 . At the same time, relative to the spacer 408 a , the conductive structure 406 b below the spacer 408 a shrinks inward toward the sidewall of the conductive structure 420 . That is, an upper surface of the conductive structure 406b is lower than an upper surface of the conductive structure 420, so as to form a recess 407a between the spacer 408a and the conductive structure 420, and make the conductive structure between the spacer 408a and the substrate 400 The structure 406b retracts toward the sidewall of the conductive structure 420 to form a recess 407b. Wherein, the etching step is performed, for example, by an isotropic wet etching process with ammonia water-hydrogen peroxide solution, wherein the composition ratio of ammonia water, hydrogen peroxide and water in the ammonia water-hydrogen peroxide solution is about 1-5:1 : 100-500, and the temperature of the ammonia water-hydrogen peroxide solution is preferably between 70-90°C, preferably 85°C. It is worth noting that the method for removing part of the conductive structure 406a here uses an etching method, which has a relatively large etching selectivity for the material forming the conductive structure 406b (that is, the material forming the conductive layer 406), so it can A portion of the conductive structure 406 a is selectively removed to form the conductive structure 406 b without affecting the spacers 408 a and the exposed dielectric layer 404 .

Next, a dielectric layer 411 is formed on the substrate 400 to fill the recesses 407a and 407b. The material of the dielectric layer 411 is, for example, silicon nitride. Next, a dielectric layer 412 is formed on the dielectric layer 411 .

Referring to FIG. 3D , an opening 424 is formed in the dielectric layers 412 and 411 . The opening 424 exposes the surface of the conductive structure 420 . After that, a plug 426 electrically connected to the conductive structure 420 is formed in the opening 424 .

In an embodiment of the present invention, the material of the dielectric layer 404 is, for example, silicon oxide, the material of the dielectric layer 411 is, for example, silicon nitride, and the material of the dielectric layer 412 is, for example, silicon oxide. When forming the opening 424, for example, the dielectric layer 411 is used as an etching stop layer to remove part of the dielectric layer 412; then the dielectric layer 404 is used as an etching stop layer to remove part of the dielectric layer 411; A portion of the dielectric layer 404 is removed to expose the conductive structure 420 . For the adjacent conductive structure 406b and conductive structure 420, the height of the conductive structure 406b is relatively low. Therefore, when the opening 424 is opened to expose the upper surface of the conductive structure 420, even if the photolithography process has misalignment problems, resulting in contact windows. The position of the opening is shifted, and the opened opening 424 will not expose another conductive structure 406 b adjacent to the conductive structure 420 . In this way, the plug 426 subsequently formed in the opening 424 will not form an abnormal electrical connection with an unintended electrical connection component (such as the conductive structure 406b in this embodiment). Therefore, it can solve the existing problem of leakage current or abnormal electrical performance caused by abnormal electrical connection of adjacent components when the integration of components is improved, and the photolithography process is misaligned or the alignment accuracy is insufficient.

In summary, the present invention has at least the following advantages:

1) In the trench flash memory process, the plug manufacturing method of the present invention uses the material of the selection gate, the material of the spacer and the gate dielectric layer, which have the characteristics of obvious difference in etching selectivity, and removes part of the selection gate. pole, so that the height of the formed selection gate is lower than that of the trenched gate structure, and relative to the spacer, the selection gate shrinks inward toward the sidewall of the trenched gate structure, so even when the subsequent When misalignment occurs in the photolithography process or the alignment accuracy is insufficient, the opening of the opened contact window is shifted, and the components that are not expected to form electrical connections will not be exposed. Therefore, the problem of leakage current or abnormal electrical performance caused by abnormal conduction can be solved, and the insulation capability between the select gate and the trench gate structure can be improved at the same time.

2) In the interconnection process of the plug manufacturing method of the present invention, the material of the conductive structure and the material of the dielectric layer and the spacer have the characteristics of obvious difference in etching selectivity, and part of the conductive structure is removed to make the formed conductive structure The height of the structure is lower than that of the conductive structure intended to form the electrical connection, and relative to the spacer, the conductive structure shrinks inward toward the sidewall of the conductive structure intended to form the electrical connection, so even when the subsequent photolithography process In the event of misalignment or insufficient alignment accuracy, the opened via openings are shifted without exposing components that are not intended to form electrical connections. Therefore, problems of leakage current or abnormal electrical performance caused by abnormal conduction can be solved.

3) In the plug manufacturing method of the present invention, the etching selectivity difference between the conductive material and the dielectric material is utilized, and the selected etching method has a large etching selectivity ratio for the conductive material, so that it is not predetermined and The height of the conductive elements that are electrically connected to the upper conductive structure is lower than the conductive elements that are intended to be electrically connected to the upper conductive structure. In this way, when vias or contact openings are subsequently formed in the dielectric layer, other conductive elements that are not intended to be formed with the upper conductive structure adjacent to the conductive elements that are intended to be electrically connected to the upper conductive structure will not be exposed. Electrically connected conductive elements. Therefore, it is possible to avoid the problem of leakage current or abnormal electrical performance caused by abnormal conduction between the subsequently formed plug and the conductive element that is not intended to be electrically connected to the upper layer conductive structure.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention It shall prevail as defined in the appended claims.

Claims (20)

1. A method of manufacturing a semiconductor element, comprising: forming a first conductive structure on a base; forming a first dielectric layer on the first conductive structure; forming a second conductive structure on the first conductive structure covered with the first dielectric layer and the substrate; forming a spacer on the second conductive structure and on both sides of the first conductive structure; removing a part of the second conductive structure so that an upper surface of the second conductive structure is lower than an upper surface of the first conductive structure to form a first recess between the spacer and the first conductive structure , and shrink the second conductive structure between the spacer and the base toward the sidewall of the first conductive structure to form a second recess; forming a second dielectric layer covering the second conductive structure and filling the first recess and the second recess; and A plug is formed in the second dielectric layer. 2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the step of removing a portion of the second conductive structure comprises using an isotropic etching process. 3. The method of manufacturing a semiconductor device as claimed in claim 2, wherein the isotropic etching process uses an etching solution comprising ammonia water-hydrogen peroxide solution. 4. The method for manufacturing a semiconductor device according to claim 3, wherein in the ammonia water-hydrogen peroxide solution, the composition ratio of ammonia water, hydrogen peroxide and water is 1-5:1:100-500. 5. The method for manufacturing a semiconductor device according to claim 3, wherein the temperature range of the ammonia water-hydrogen peroxide solution is 70-90°C. 6. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the material of the second conductive structure comprises polysilicon, metal silicide or polysilicon/silicon tungsten. 7. A method of manufacturing a semiconductor element, comprising: A substrate is provided, on which a trench flash memory has been formed, wherein the trench flash memory includes: a trench gate structure located in the base and protruding from a surface of the base; a gate dielectric layer covering the trench gate structure; a spacer located on the sidewall of the trenched gate structure covered with the gate dielectric layer; and a select gate located between the spacer and the trench gate structure and between the spacer and the substrate; removing a part of the exposed select gate so that an upper surface of the select gate is lower than an upper surface of the trenched gate structure to form a spacer between the spacer and the trenched gate structure a first recess, and the select gate located at the spacer and the substrate retracts toward the sidewall of the trench gate structure to form a second recess; and On the substrate, a dielectric layer is formed, the dielectric layer covers the trench flash memory and fills the first recess and the second recess. 8. The manufacturing method of semiconductor element as claimed in claim 7 also comprises: In the dielectric layer, a first contact opening is formed, wherein the first contact opening exposes source/drain regions; and In the first contact opening, a first contact plug is formed. 9. The manufacturing method of semiconductor element as claimed in claim 8, further comprising: forming a second contact opening in the dielectric layer, wherein the second contact opening exposes the upper surface of the trenched gate structure; and In the second contact opening, a second contact plug is formed. 10. The method of manufacturing a semiconductor device as claimed in claim 7, wherein the method of removing a part of the select gate comprises an isotropic etching process. 11. The method of manufacturing a semiconductor device as claimed in claim 10, wherein the isotropic etching process uses an etching solution comprising ammonia water-hydrogen peroxide solution. 12. The method for manufacturing a semiconductor device according to claim 11, wherein in the ammonia water-hydrogen peroxide solution, the composition ratio of ammonia water, hydrogen peroxide and water is 1-5:1:100-500. 13. The method for manufacturing a semiconductor device according to claim 11, wherein the temperature range of the ammonia water-hydrogen peroxide solution is 70-90°C. 14. The method of manufacturing a semiconductor device as claimed in claim 8, wherein the material of the selection gate comprises polysilicon, metal silicide or polysilicon/silicon tungsten. 15. A method for manufacturing a plug, which is applicable to a substrate, on which a first conductive structure and a first dielectric layer are formed, and the first dielectric layer covers the first conductive structure, the method comprising: forming a second conductive structure over the substrate next to the first conductive structure; shrinking the second conductive structure so that an upper surface of the second conductive structure is lower than an upper surface of the first conductive structure; forming a second dielectric layer over the base, the second dielectric layer covering the first conductive layer structure and the second conductive structure; In the second dielectric layer, forming a via opening; and In the via opening, a via plug is formed. 16. The method of manufacturing the plug as claimed in claim 15, wherein the method of shrinking the second conductive structure comprises a wet etching process. 17. The method of manufacturing the plug as claimed in claim 16, wherein the wet etching process uses an etching solution comprising ammonia water-hydrogen peroxide solution. 18. The method of manufacturing the plug according to claim 17, wherein in the ammonia water-hydrogen peroxide solution, the composition ratio of ammonia water, hydrogen peroxide and water is 1-5:1:100-500. 19. The manufacturing method of the plug according to claim 17, wherein the ammonia water-hydrogen peroxide solution has a temperature range of 70-90°C. 20. The method of manufacturing the plug according to claim 15, wherein the via opening exposes the upper surface of the first conductive structure.

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