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TW200504943A - Manufacturing method of flash memory - Google Patents

Manufacturing method of flash memory

Info

Publication number
TW200504943A
TW200504943A TW092119490A TW92119490A TW200504943A TW 200504943 A TW200504943 A TW 200504943A TW 092119490 A TW092119490 A TW 092119490A TW 92119490 A TW92119490 A TW 92119490A TW 200504943 A TW200504943 A TW 200504943A
Authority
TW
Taiwan
Prior art keywords
layer
forming
patterned
subtrate
gate structure
Prior art date
Application number
TW092119490A
Other languages
Chinese (zh)
Other versions
TWI235461B (en
Inventor
Kuang-Chao Chen
Jui-Lin Lu
Ling-Wuu Yang
Original Assignee
Macronix Int Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix Int Co Ltd filed Critical Macronix Int Co Ltd
Priority to TW92119490A priority Critical patent/TWI235461B/en
Publication of TW200504943A publication Critical patent/TW200504943A/en
Application granted granted Critical
Publication of TWI235461B publication Critical patent/TWI235461B/en

Links

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present invention is related to a manufacturing method of flash memory which includes forming a patterned tunneling dielectric layer, conductor layer and mask layer on a subtrate to form a gate structure; forming a buried drain in the subtrate; filling a insulating layer circumferentially around the gate structure and the surface level of the insulating layer lower than the surface level of the patterned conductor layer; forming a material layer on the insulating layer; removing the patterned mask layer; forming another pattered conductor layer on the patterned conductor layer of the gate structure and protruding over the surface of insulating layer; removing the material layer; forming a intergate dielectric layer on the subtrate; forming a control gate on the intergate dielectric layer.
TW92119490A 2003-07-17 2003-07-17 Manufacturing method of flash memory TWI235461B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW92119490A TWI235461B (en) 2003-07-17 2003-07-17 Manufacturing method of flash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW92119490A TWI235461B (en) 2003-07-17 2003-07-17 Manufacturing method of flash memory

Publications (2)

Publication Number Publication Date
TW200504943A true TW200504943A (en) 2005-02-01
TWI235461B TWI235461B (en) 2005-07-01

Family

ID=36637679

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92119490A TWI235461B (en) 2003-07-17 2003-07-17 Manufacturing method of flash memory

Country Status (1)

Country Link
TW (1) TWI235461B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103972175A (en) * 2013-01-25 2014-08-06 华邦电子股份有限公司 Method for manufacturing damascene structure of NAND flash memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103972175A (en) * 2013-01-25 2014-08-06 华邦电子股份有限公司 Method for manufacturing damascene structure of NAND flash memory
CN103972175B (en) * 2013-01-25 2016-12-28 华邦电子股份有限公司 Method for manufacturing damascene structure of NAND flash memory

Also Published As

Publication number Publication date
TWI235461B (en) 2005-07-01

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Legal Events

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