4S77twf.d〇c/0C6 Αί ^6641 4_B7__ 五、發明說明（/ ) 本發明是有關於一種資料傳輸線，且特別是有關於 一種連接於微處理器與晶片組之間的傳輸線。 (請先閱讀背面之注意事項再填寫本頁) 電腦的微處理器，或中央處理器（CPU)係透過晶片組 (ch 1 pse〇來與外界周邊進行資料的傳輸與命令的溝通。晶 片組上的輸出入腳透過資料傳輸邏輯匯流排連接到電腦主 機板上的微處理器插槽，微處理器上的印刷電路基板插上 主機板上的連接插槽，得以與晶片組之間進行資料的傳 輸。 經濟部智慧財產局員工消費合作社印製 目前應用於微處理器的常見傳輸邏輯匯流排規格大致 包括射擊傳輸線（Gunning Transceiver Logic，GTL+)匯流排 以及高速傳輸線（High Speed Transceiver Logic，HSTL)匯流 排等。GTL +匯流排爲英特爾（Intel)公司目前新一代微處理 器所採用，用來與外界介面傳輸資料的標準規格，適用的 微處理器包括奔騰級微處理器，如pentiumll、Pentium III、 Pentium Pro與Socket 370等等。而HSTL匯流排爲另一種 微處理器所採用，用來與外界介面傳輸資料的標準規格。 然而1因爲GTL+與HSTL匯流排爲兩種不同的規格，所 以使用GTL +匯流排的微處理器系列與使用HSTL匯流排 的微處理器系列便必須使用兩種不同的晶片組來控制微處 理器。4S77twf.d〇c / 0C6 Αί ^ 6641 4_B7__ 5. Description of the invention (/) The present invention relates to a data transmission line, and in particular to a transmission line connected between a microprocessor and a chipset. (Please read the precautions on the back before filling out this page) The microprocessor or central processing unit (CPU) of the computer communicates with the outside world through the chipset (ch 1 pse〇) for data transmission and command communication. Chipset The I / O pins on the board are connected to the microprocessor socket on the computer motherboard through the data transfer logic bus. The printed circuit board on the microprocessor is inserted into the connection socket on the motherboard to carry out data with the chipset. The specifications of the common transmission logic buses currently applied to microprocessors are printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics, which roughly include Gunning Transceiver Logic (GTL +) buses and High Speed Transceiver Logic (HSTL) Bus, etc. GTL + bus is adopted by Intel (Intel) company's new generation of microprocessors, used to transfer data to and from the external interface standard specifications, applicable microprocessors include Pentium-class microprocessors, such as pentiumll, Pentium III, Pentium Pro, Socket 370, etc. The HSTL bus is used by another microprocessor to Standard specifications for transmitting data through the external interface. However, because GTL + and HSTL buses are two different specifications, the microprocessor series using GTL + buses and the microprocessor series using HSTL buses must use two different types. Chipset to control the microprocessor.
第1圖與第2圖分別繪示使用GTL+匯流排與HSTL匯 流排的微處理器與晶片組資料傳輸匯流排的連接示意圖。 比較第1圖與第2圖可以發現兩種匯流排皆有以下的共同 點：端點電壓Vn.皆爲相同，如VTT=1.5V。參考電壓源VREF 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4B77twf.d〇c/006 Λ/ 4 6 6 4 1 4 Β7 五、發明說明（：> ) 則大約爲 1.0V 左右（當 V.n.= 1.5V)，即 VREF—2/3* νΊΤ 或 0.68 *Vn.。GTL+匯流排12與HSTL匯流22排皆使用相同尺 寸的連接插槽（connector)M、24 :不同的微處理器16、26 都有自己的印刷電路基板16a、26a，再藉由印刷電路基板 16a、26a插上主機板10a、20a上的連接插槽14、24與晶 片組10、20相連。 比較第1圖與第2圖可以發現其間的差異性在於傳輸 線（transmission line)匯流排的結構，GTL+與HSTL結構。 第1圖所繪示之GTL+傳輸線匯12流排結構是由一個或兩 個56歐姆的拉升（puU-up)電阻Rtl來拉升匯流排的電位， 同時此電阻Rn位於傳輸線端末，固具有終端（end-termmation)電阻的特性，可用來防止訊號回振（ring back)。 第2圖之HSTL結構的傳輸匯流排22則由兩個100歐姆的 拉升電阻Rlt來拉升傳輸邏輯匯流排的電位’此電阻並不 做爲終端電阻之用。此外，在第2圖之HSTL傳輸匯流排 22中接近晶片組20與微處理器26之輸出輸入(10)端更分 別包括一串聯電阻Rs，約22歐姆，其主要作爲減少傳輸 線之訊號振動（damping)之用。 由上述可以得知，GTL+與HSTL匯流排爲兩種不同的 傳輸邏輯匯流排規格，不同的微處理器則採用不同的傳輸 邏輯匯流排，而其所搭配的晶片組也就不相同。主機板上 的晶片組通常爲固定，如此一來使用者所能夠自選微處理 器的種類便受到限制。 因此’設計出一種晶片組’使其0旨夠減少相異傳輸邋 4 (請先Μ讀背面之注意事項再填寫本頁) 古0Figures 1 and 2 show the connection between the microprocessor and chipset data transmission bus using GTL + bus and HSTL bus, respectively. Comparing Figure 1 and Figure 2, it can be found that both buses have the following in common: the terminal voltage Vn. Is the same, such as VTT = 1.5V. Reference voltage source VREF 3 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4B77twf.d〇c / 006 Λ / 4 6 6 4 1 4 Β7 5. Description of the invention (: >) is about 1.0V (when Vn = 1.5V), that is, VREF-2 / 3 * νΊΤ or 0.68 * Vn. GTL + bus 12 and HSTL bus 22 both use the same connector M, 24: different microprocessors 16, 26 have their own printed circuit boards 16a, 26a, and then printed circuit board 16a , 26a are plugged into the connection slots 14, 24 on the motherboards 10a, 20a and connected to the chipset 10, 20. Comparing Figure 1 and Figure 2, we can see that the difference lies in the structure of the transmission line bus, the GTL + and HSTL structures. The GTL + transmission line bus 12 bus structure shown in Figure 1 uses one or two 56 ohm pull-up (puU-up) resistors Rtl to pull up the potential of the bus bar. At the same time, this resistor Rn is located at the end of the transmission line. The characteristics of the end-termmation resistor can be used to prevent the signal from ringing back. The transmission bus 22 of the HSTL structure in FIG. 2 has two 100 ohm pull-up resistors Rlt to pull up the potential of the transmission logic bus. This resistor is not used as a terminating resistor. In addition, in the HSTL transmission bus 22 shown in FIG. 2, the output (10) ends of the chipset 20 and the microprocessor 26 each include a series resistor Rs, about 22 ohms, which is mainly used to reduce the signal vibration of the transmission line ( damping). From the above, it can be known that GTL + and HSTL buses are two different specifications of transmission logic buses, different microprocessors use different transmission logic buses, and the chipsets they use are not the same. The chipset on the motherboard is usually fixed, which limits the type of microprocessors the user can choose. Therefore, ‘design a chipset’ to reduce the number of different transmissions 邋 4 (Please read the precautions on the back before filling this page) Ancient 0
本紙張义度適用中國國家標準（CNS)A4規格（210 X 297公釐） Λ7 B7 4577twf.doc/006The meaning of this paper applies to China National Standard (CNS) A4 (210 X 297 mm) Λ7 B7 4577twf.doc / 006
Jk£J\JLA 五、發明說明（多） 輯匯流排之間的差異性，晶片組便能夠支援不同的傳輸邏 輯匯流排。再者，藉此使用者也可以自由地選擇所需要的 微處理器。 本發明係提出一·種支援多種傳輸邏輯匯流排之輸出入 緩衝器，其可以自動測得插於主機板插槽的爲處理器種 類，藉以調整晶片組之輸出入腳位的電阻組態，以適合不 同微處理器所需的傳輸邏輯匯流排規格。 本發明係提出一種支援多種傳輸邏輯匯流排之輸出入 緩衝器，藉以調整晶片組之輸出入腳位的電阻組態，得以 使用同一晶片組來搭配不同的微處理器。 本發明f提出一種支援多種傳輸邏輯匯流排之輸出入 緩衝器，其內含可改善傳輸邏輯匯流排之訊號回振效應與 降低功率消耗。 本發明提出一種支援多種傳輸邏輯匯流排之輸出入緩 衝器，其簡述如下： 一種支援多種傳輸邏輯匯流排之輸出入緩衝器，輸出 入緩衝器經由傳輸線耦接到微處理器插槽。支援多種傳輸 邏輯匯流排之輸出入緩衝器至少包括：調變控制器。邏輯 控制電路，用以接收一微處理器偵測訊號。第一電晶體與 弟一電晶體，分別稱接於邏fe控制電路與輸出人緩衝器之 輸出入墊之間，第一與第二電晶體係由邏輯控制電路所控 制。第一電阻裝置，耦接於-端點電壓源與第一電晶體之 間，並且由調變控制器所控制。第二電阻裝置，耦接於端 點電壓源與第二電晶體之間’並且接收一控制訊號，以決 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） n n n n n n —I. I .^1 一 51 I tf - i I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 Λ7 B7 4577twf.d〇c/006 4 6 641 4 五、發明說明（l) 定該第二電阻裝置之導通。緩衝器，耦接至輸出入墊，用 以將來自輸出入墊之訊號電壓與參考電壓比較，輸出一輸 入電壓位準訊號給調變控制器，調變控制器並依據輸入電 壓位準訊號改變第一電阻裝置的阻値。 當微處理器偵測訊號爲第一準位時，如邏輯1狀態， 第--電晶體與第二電阻裝置爲導通狀態，藉以使該傳輸線 具有第一傳輸邏輯匯流排組態，如HSTL匯流排；當微處 理器偵測訊號爲第二準位時，如邏輯0狀態，第一、第二 電晶體與第一電阻裝置爲導通狀態，藉以使傳輸線具有第 二傳輸邏輯匯流排組態，如GTL+匯流排。 藉此，可以自動測得插於主機板插槽的爲處理器種 類，藉以調整晶片組之輸出入腳位的電阻組態，以適合不 同微處理器所需的傳輸邏輯匯流排規格。同時可以使用同 一晶片組來搭配使用不同傳輸匯流排規格之相異微處理 器。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第1圖繪不藉由GTL+傳輸邂輯匯流排結構連接晶片 組與微處理器之間的連結架構示意圖； 第2圖繪示藉由HSTL傳輸邏輯匯流排結構連接晶片 組與微處理器之間的連結架構示意圖；以及 第3圖繪示圖依據本發明之支援多種傳輸邏輯匯流排 之輸出入緩衝器，晶片組與微處理器之間的連結架構示意 vr-v ―〆 爸口 冬 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） 經濟部智慧財產局員工消費合作社印製 4577twf.doc/006 Λ/ -4^6 6 4 1 4-^- 五、發明說明（^ ) 圖； 第4圖繪示圖依據本發明之支援多種傳輸邏輯匯流排 之輸出入緩衝器之架構示意圖；以及 第5圖繪示圖依據本發明之支援多種傳輸邏輯匯流排 之輸出入緩衝器中調變控制器與電阻裝置降低訊號回振的 輸出波形。 標號說明： 10a主機板 10晶片組 12 GTL+匯流排 14微處理器插槽 16微處理器 16a微處理器之印刷電路基板 2〇a主機板 20晶片組 22 HSTL匯流排 24微處理器插槽 26微處理器 26a微處理器之印刷電路基板 100主機板 102傳輸線 104微處理器插槽 110晶片組 120輸出入緩衝器 122調變控制器 124邏輯控制電路 126輸出入墊 12 8緩衝器 130微處理器模組 132微處理器 實施例 請參照第3圖，其繪示利用本發明之支援多種傳輸邏 輯匯流排之輸出入緩衝器120,將主機板丨〇〇上之晶片組 7 \—r — — — — — ^ ·1111111 1 — -----I ^ (請先間讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4B77twf.doc/006 Λ7 4B77twf.doc/006 Λ7 B7Jk £ J \ JLA V. Description of the Invention (Multiple) The differences between the serial buses enable the chipset to support different transmission logic buses. Furthermore, the user can also freely select the required microprocessor. The invention proposes an input / output buffer that supports a variety of transmission logic buses, which can automatically detect the type of processor inserted in the motherboard slot, thereby adjusting the resistance configuration of the input / output pins of the chipset. To fit the specifications of the transmission logic bus required by different microprocessors. The invention proposes an I / O buffer supporting multiple transmission logic buses, so as to adjust the resistance configuration of the I / O pins of the chipset, so that the same chipset can be used to match different microprocessors. The present invention f proposes an input / output buffer that supports a variety of transmission logic buses. The buffers can improve the signal return effect of the transmission logic buses and reduce power consumption. The present invention provides an input / output buffer supporting multiple transmission logic buses, which is briefly described as follows: An input / output buffer supporting multiple transmission logic buses. The input / output buffers are coupled to a microprocessor socket via a transmission line. Supports multiple transmissions The input and output buffers of the logic bus include at least: a modulation controller. The logic control circuit is used for receiving a microprocessor detection signal. The first transistor and the first transistor are respectively connected between the logic control circuit and the input / output pad of the output buffer, and the first and second transistor systems are controlled by the logic control circuit. The first resistance device is coupled between the -terminal voltage source and the first transistor, and is controlled by a modulation controller. The second resistance device is coupled between the terminal voltage source and the second transistor and receives a control signal to determine the paper size. The Chinese national standard (CNS) A4 specification (210 X 297 mm) is applied. Nnnnnn —I I. ^ 1 51 I tf-i I (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ7 B7 4577twf.d〇c / 006 4 6 641 4 V. DESCRIPTION OF THE INVENTION (1) The conduction of the second resistance device is determined. A buffer, coupled to the input / output pad, for comparing the signal voltage from the input / output pad with a reference voltage, outputting an input voltage level signal to the modulation controller, and modulating the controller and changing the signal according to the input voltage level Resistance of the first resistance device. When the microprocessor detects that the signal is at the first level, such as a logic 1 state, the first transistor and the second resistance device are in a conducting state, so that the transmission line has a first transmission logic bus configuration, such as HSTL bus When the microprocessor detects that the signal is at the second level, such as a logic 0 state, the first and second transistors and the first resistance device are in a conducting state, so that the transmission line has a second transmission logic bus configuration. Such as GTL + bus. In this way, the type of processor inserted in the motherboard slot can be automatically detected, and the resistance configuration of the input and output pins of the chipset can be adjusted to fit the specifications of the transmission logic bus required by different microprocessors. At the same time, the same chipset can be used with different microprocessors with different transmission bus specifications. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies the preferred embodiments and the accompanying drawings to make detailed descriptions as follows: Brief description of the drawings: The first drawing is not borrowed Schematic diagram of the connection structure between the chipset and the microprocessor by the GTL + transmission bus structure; Figure 2 shows the schematic diagram of the connection structure between the chipset and the microprocessor by the HSTL transmission logic bus structure; and Figure 3 shows the input and output buffers supporting a variety of transmission logic buses according to the present invention. The connection structure between the chipset and the microprocessor indicates vr-v-daddy mouth (please read the precautions on the back first) (Fill in this page again) Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed to the Chinese National Standard (CNS) A4 (210x 297 mm) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4577twf.doc / 006 Λ / -4 ^ 6 6 4 1 4-^-V. Description of the invention (^) Figure; Figure 4 shows a schematic diagram of the architecture of the input and output buffers supporting multiple transmission logic buses according to the present invention; and Figure 5 FIG illustrates various transmissions logic output bus of the buffer and the resistor modulation controller means reduces the output signal waveform of the swing-back support according to the present invention. DESCRIPTION OF SYMBOLS: 10a motherboard 10 chipset 12 GTL + bus 14 microprocessor socket 16 microprocessor 16a microprocessor printed circuit board 20a motherboard 20 chipset 22 HSTL bus 24 microprocessor socket 26 Microprocessor 26a Microprocessor printed circuit board 100 Motherboard 102 Transmission line 104 Microprocessor socket 110 Chipset 120 I / O buffer 122 Modulation controller 124 Logic control circuit 126 I / O pad 12 8 Buffer 130 Microprocessing Please refer to FIG. 3 for an embodiment of the microprocessor module 132 microprocessor, which shows the use of the input / output buffer 120 of the present invention that supports multiple transmission logic buses, and the chipset 7 on the motherboard 丨 〇〇 — — — — ^ · 1111111 1 — ----- I ^ (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 4B77twf .doc / 006 Λ7 4B77twf.doc / 006 Λ7 B7
A 五、發明說明（乙） 110與微處理器模組130之間藉由傳輸線102的連結示意 圖。依據本發明之支援多種傳輸邏輯匯流排之輸出入緩衝 器120’如習知之作於主機板上的拉升電阻Rtt與串聯電 阻Rs便可以省略1而可以達到支援GTL+或HSTL傳輸邏 輯匯流排之功能。在整體的架構上，在緩衝器120的外部 與傳輸線102之間，也可以視實際情形在串接一電阻RS。 如上所述，因爲微處理器中作爲資料傳輸的腳位多達 一百多隻，拉升電阻RU與串聯電阻Rs省略，便可以省下 主機板的製作成本與降低主機板上接線的複雜度。接著， 便將詳述本發明之支援多種傳輸邏輯匯流排之輸出入緩衝 器是如何達到支援支援GTL+或HSTL傳輸邏輯匯流排之 功能，而省下拉升電阻RU與串聯電阻Rs的製作佈局。 請參考第4圖，其繪示圖依據本發明之支援多種傳輸 邏輯匯流排之輸出入緩衝器之架構示意圖。 本發明之支援多種傳輸邏輯匯流排之輸出入緩衝器 120，經由傳輸線102接到微處理器插槽104支援多種傳輸 邏輯匯流排之輸出入緩衝器120至少包括：調變控制器 122。邏輯控制電路124用以接收一微處理器偵測訊號K7， 當微處理器模組130藉由其上的印刷電路基板插於微處理 器插槽104時，將自動產生-微處理器偵測訊號K7給邏 輯控制電路124，用以告知目前的微處理器種類。第一電 晶體MN1與第二電晶體MN2,分別耦接於邏輯控制電路114 與輸出入緩衝器之輸出入墊116,第一與第二電晶體MN1、 MN2係由邏輯控制電路112控制，並依據微處理器偵測訊 本紙張尺度適用中國囤家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ^-° Γ 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 4577twf.d〇c/006 Αί 4 6 6 4 1 4 Β7 五、發明說明（q) 號K7來控制電晶體MN1與MN2的導通與否。第一與第 二電晶體MN1、MN2可以NMOS電晶體來實施。’ 第一電阻裝置PR1，耦接於一端點電壓源v.n.與第一 電晶體ΜΝ1之間’並且由調變控制器丨12控制其導通與 否，端點電壓源Vri.在此例中可以爲1.5V。電阻裝置pri 可以由NMOS電晶體所構成。第二電阻裝置RNU於端點 電壓源Vri.與第二電晶體MN2之間，並且接收一控制訊號 PU，其可以用來決定第二電阻裝置RNU之導通。電阻裝 置RNU的等效阻値約爲100歐姆左右，端視所需的傳輸 邏輯匯流排規格來決定°電阻裝置RNU可以由PMOS或 NMOS電晶體所構成。或是由一電阻與一 pm〇S電晶體串 接所構成，此電阻的阻値可以約爲80歐姆。 緩衝器118，鍋接至輸出入塾116，用以將來自輸出 入墊116之訊號電壓VIN與參考電壓VREF比較，輸出輸 入電壓位準訊號V給調變控制器丨12。調變控制器1丨2並 依據輸入電壓位準訊號V改變第一電阻裝置PRi的阻値^ 上述之電阻裝置PR1、RNU與電晶體MN1、MN2的阻値設 計均可以依據實際的傳輸邏輯匯流排規格來加以設計。 當微處理器偵測訊號K7爲第一準位時，例如邏輯1 狀態，第一電晶體MN1與第二電阻裝置RNU爲導通狀態， 藉以使傳輸線102具有第一傳輸邏輯匯流排組態。假如RNU 阻値設計約爲100歐姆，而輸出的等效阻値爲22歐姆時， 則爲-種HSTL規格之傳輸邏輯匯流排。當微處理器偵測 訊號K7爲第二準位時，例如邏輯〇狀態，第一、第二電 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） J. (請先閱讀背面之注音？事項再填寫本頁) 言A 5. Description of the invention (B) A schematic diagram of the connection between the 110 and the microprocessor module 130 through the transmission line 102. According to the present invention, the input and output buffers 120 'supporting a variety of transmission logic buses, such as the pull-up resistors Rtt and series resistors Rs made on the motherboard, can be omitted by 1 and can support GTL + or HSTL transmission logic buses. Features. On the overall architecture, a resistor RS can also be connected in series between the outside of the buffer 120 and the transmission line 102 according to the actual situation. As mentioned above, because there are more than a hundred pins for data transmission in the microprocessor, the pull-up resistor RU and the series resistor Rs are omitted, which can save the production cost of the motherboard and reduce the complexity of the wiring on the motherboard. . Next, how the input / output buffers supporting multiple transmission logic buses of the present invention can achieve the function of supporting GTL + or HSTL transmission logic buses will be described in detail, and the production layout of the pull-down resistor RU and the series resistor Rs will be omitted. Please refer to FIG. 4, which is a schematic diagram illustrating an architecture of an input / output buffer supporting multiple transmission logic buses according to the present invention. The input / output buffer 120 of the present invention which supports multiple transmission logic buses is connected to the microprocessor socket 104 via the transmission line 102. The input / output buffer 120 which supports multiple transmission logic buses at least includes a modulation controller 122. The logic control circuit 124 is used to receive a microprocessor detection signal K7. When the microprocessor module 130 is inserted into the microprocessor socket 104 through the printed circuit board thereon, it will be automatically generated-microprocessor detection The signal K7 is provided to the logic control circuit 124 to inform the current microprocessor type. The first transistor MN1 and the second transistor MN2 are respectively coupled to the logic control circuit 114 and the input / output pad 116 of the input / output buffer. The first and second transistors MN1 and MN2 are controlled by the logic control circuit 112, and According to the microprocessor detection, the paper size of the paper applies the Chinese storehouse standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) ^-° Γ Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Consumption Cooperative Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs. Consumption Cooperative Printed by the Employees Cooperative Cooperative. 4577twf.d〇c / 006 Αί 4 6 6 4 1 4 B7 V. Description of Invention (q) No. K7 to control the conduction of transistors MN1 and MN2. The first and second transistors MN1, MN2 may be implemented as NMOS transistors. 'The first resistor device PR1 is coupled between a terminal voltage source vn and the first transistor MN1' and its conduction is controlled by a modulation controller 12 and the terminal voltage source Vri. In this example, it can be 1.5V. The resistance device pri may be composed of an NMOS transistor. The second resistance device RNU is between the terminal voltage source Vri. And the second transistor MN2, and receives a control signal PU, which can be used to determine the conduction of the second resistance device RNU. The equivalent resistance of the resistance device RNU is about 100 ohms. The end depends on the required specifications of the transmission logic bus. The resistance device RNU can be composed of PMOS or NMOS transistors. Or it consists of a resistor in series with a pMOS transistor. The resistance of this resistor can be about 80 ohms. The buffer 118 is connected to the input / output unit 116 to compare the signal voltage VIN from the input / output pad 116 with the reference voltage VREF, and outputs the input voltage level signal V to the modulation controller 12. Regulating the controller 1 and 2 and changing the resistance of the first resistance device PRi according to the input voltage level signal V ^ The resistance design of the above-mentioned resistance devices PR1, RNU and transistors MN1, MN2 can be combined according to the actual transmission logic Design specifications. When the microprocessor detects that the signal K7 is at the first level, for example, the logic 1 state, the first transistor MN1 and the second resistance device RNU are in the conducting state, so that the transmission line 102 has the first transmission logic bus configuration. If the RNU resistance design is about 100 ohms, and the equivalent resistance of the output is 22 ohms, then it is a kind of HSTL specification transmission logic bus. When the microprocessor detects that the signal K7 is at the second level, such as a logic 0 state, the paper size of the first and second papers applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) J. (Please first Read the phonetic on the back? Matters need to fill in this page)
4 6 6mwf .doc/0 0 6 Λ7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（分） 晶體MN1、MN2與第一·電阻裝置PR1爲導通狀態，藉以 使傳輸線102具有第二傳輸邏輯匯流排組態，例如GTU 規格之傳輸邏輯匯流排。 以下在本實施例中，將以常被利用的GTL +與HSTL 匯流排來做爲說明例子。 參考第4圖，當使用HSTL傳輸邏輯匯流排的微處理 器系列產品插入連接插槽104時，假設此時定義偵測的微 處理器偵測訊號K7爲邏輯1狀態。依據此訊號K7，使得 電阻裝置RNU與電晶體MN1導通，成爲緩衝器120中的 主要工作元件。MN1導通時的等效電阻被設計成與第2圖 中的串聯電阻Rs與輸出入緩衝器的導通電阻之總和組値 相等，此時便可以將主機板上的Rs電阻省略。此外，電 阻器RNU係設計成接近100歐姆的電阻元件，做爲拉升 電阻之用。電阻器RNU在經過適當的補償後可以讓電阻 値落在傳輸邏輯匯流排規格可接受的範圍之內。藉此，便 等效於第2圖中的HSTL匯流排結構，主機板上的拉升電 阻RU與Rs便可以省略不製作。 參考第4 _，當使用GTL+傳輸邏輯匯流排的微處理 器系列產品插入連接插槽104時，假設此時定義偵測的微 處理器偵測訊號K7爲邏輯0狀態。依據此訊號K7，使得 電阻裝置PR1與電晶體MN1、MN2導通，成爲緩衝器120 中的主要工作元件。此時電阻裝置RNU則爲關閉狀態。 電阻裝置PR1與電晶體MN1、MN2的等效阻値可以設計 成與第1圖之習知GTL+傳輸邏輯匯流排結構ΰ如此’便 n .^1 .^1 ^^1 I .^1 n la ϋ etf Met _n I ^' 一 J -¾¾^. <請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4577twf.d<466Δ1Δ /006 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（q) 可以省去第1圖中主機板上拉升兼終端電阻Ru。 由上述可以得知’當微處理機模組130插入微處理器 插槽104時’所產生的微處理器偵測訊號K7會傳給輸出 入緩衝器120之邏輯控制電路丨24,藉此得以判斷使用者 所使用的微處理器種類。同時，輸出入緩衝器120會在電 阻裝置PR1、RNU與電晶體MN1、MN2中選擇適當的元件 來導通，以產生適合的傳輸邏輯匯流排組態。故本發明之 支援多種傳輸邏輯匯流排之輸出入緩衝器，至少可以支援 兩種以上相異的傳輸邏輯匯流排。 第4圖中之調變控制器丨22在選用使用GTL+傳輸邏 輯匯流排的微處理器系列時也會開始作動，其用以改善接 收GTL+傳輸邏輯匯流排訊號的回振效應以及減少功率消 耗。 電阻裝置PR1可以使用PMOS電晶體所構成。當輸出 入墊126之電壓爲1.5V到1.0V之間，由調變控制器122 輸出0V使得電阻PR1完全導通，維持電阻値爲100Ω到 200Ω，當輸出入墊126逐漸下降到1.0V以下，使得做爲 電阻PR1之PMOS電晶體之閘極電壓逐漸慢慢上升，可視 爲等效電阻提高阻値，直到五至十奈秒後，做爲電阻PR1 之PMOS電晶體才完全不導通。 利用電阻PR1這種具有主動式關閉特性，對回振效β 能夠有效降低到0.4V以下，如第5圖所繪示本發明在GTL+ 組態下輸出入緩衝器120所輸出波形，在回振效應下，第 -反彈點Α之電壓（0.4V)已經非常接近穩態電壓 ---------------------訂---------線· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 X 297公釐） 經濟部智慧財產局員工消费合作杜印製 Λ ^577twf.doc/006 A/ 46 6414__β7__ 五、發明說明（a;) V〇i.(0.2.V)。 綜上所述，利用本發明之支援多種傳輸邏輯匯流排之 輸出入緩衝器，來作爲晶片組與微處理器之間藉由傳輸線 的連結，與習知之技術至少具有以下的功效與優點： 利用本發明之支援多種傳輸邏輯匯流排之輸出入緩衝 器，可以自動測得插於主機板插槽的爲處理器種類，藉以 調整晶片組之輸出入腳位的電阻組態，以適合不同微處理 器所需的傳輸邏輯匯流排規格。 利用本發明之支援多種傳輸邏輯匯流排之輸出入緩衝 器，藉以調整晶片組之輸出入腳位的電阻組態，得以使用 同一晶片組來搭配不同的微處理器。 本發明之支援多種傳輸邏輯匯流排之輸出入緩衝器， 其支援使用不同規格傳輸邏輯匯流排的微處理器’使主機 板的設計與生產不需要分別爲不同的微處理器投入硏發人 力與時間。 本發明之支援多種傳輸邏輯匯流排之輸出入緩衝器’ 因爲等效於拉升電阻、終端電阻與串聯電阻等之組件係形 成於晶片組內之輸出入緩衝器，因此可以省下習知在主機 板上所裝設的大量電阻，使主機板的佈局設計可以更加簡 化，同時也可以降低成本。 綜上所述，雖然本發明已以較佳實施例揭露如上’然 其並非用以限定本發明，任何熟習此技藝者’在不脫離本 發明之精神和範圍內，當可作各種之更動與潤飾’因此本 發明之保護範圍當視後附之申請專利範圍所界定者爲準。 -------------^ -.^-11-----訂--------- 線— ( (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（2]0 X 297公釐）4 6 6mwf .doc / 0 0 6 Λ7 B7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (minutes) The crystals MN1, MN2 and the first resistance device PR1 are in a conducting state, so that the transmission line 102 has the second Transmission logic bus configuration, such as GTU specification transmission logic bus. In this embodiment, the GTL + and HSTL buses that are often used will be taken as examples for illustration. Referring to Fig. 4, when a microprocessor series product using the HSTL transmission logic bus is inserted into the connection slot 104, it is assumed that the detection signal K7 of the microprocessor which is defined at this time is a logic 1 state. According to this signal K7, the resistor RNU and the transistor MN1 are turned on, and become the main working element in the buffer 120. When MN1 is turned on, the equivalent resistance is designed to be the same as the sum of the series resistance Rs and the on-resistance of the input and output buffers in Figure 2. In this case, the Rs resistance on the motherboard can be omitted. In addition, the resistor RNU is designed as a resistance element close to 100 ohms, which is used to pull up the resistor. The resistor RNU can make the resistor fall within the acceptable range of the transmission logic bus specifications after proper compensation. This is equivalent to the HSTL bus structure shown in Figure 2. The pull-up resistors RU and Rs on the motherboard can be omitted and not made. Referring to the fourth _, when a microprocessor series product using GTL + transmission logic bus is inserted into the connection slot 104, it is assumed that the microprocessor detection signal K7 defined for detection at this time is a logic 0 state. According to this signal K7, the resistance device PR1 is turned on with the transistors MN1 and MN2, and becomes the main working element in the buffer 120. At this time, the resistance device RNU is turned off. The equivalent resistance of the resistor device PR1 and the transistors MN1 and MN2 can be designed to be the same as the conventional GTL + transmission logic bus structure in Figure 1. So 'n. ^ 1. ^ 1 ^^ 1 I. ^ 1 n la ϋ etf Met _n I ^ 'One J -¾¾ ^. < Please read the notes on the back before filling out this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 4577twf.d < 466Δ1Δ / 006 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (q) It is possible to omit the pull-up and termination resistor Ru on the main board in Figure 1. From the above, it can be known that the microprocessor detection signal K7 generated when the microprocessor module 130 is inserted into the microprocessor socket 104 will be transmitted to the logic control circuit 24 of the input / output buffer 120, thereby enabling Determine the type of microprocessor used by the user. At the same time, the input / output buffer 120 selects appropriate components from the resistor devices PR1, RNU and transistors MN1, MN2 to be turned on, so as to generate a suitable transmission logic bus configuration. Therefore, the input / output buffers supporting multiple transmission logic buses of the present invention can support at least two different transmission logic buses. The modulation controller 22 in Figure 4 will also start to operate when the microprocessor series using GTL + transmission logic bus is selected, which is used to improve the return effect of receiving GTL + transmission logic bus signals and reduce power consumption. The resistance device PR1 can be formed using a PMOS transistor. When the voltage of the input / output pad 126 is between 1.5V and 1.0V, the modulation controller 122 outputs 0V so that the resistor PR1 is completely turned on and the resistance 値 is maintained at 100Ω to 200Ω. When the input / output pad 126 gradually drops below 1.0V, The gate voltage of the PMOS transistor used as the resistor PR1 gradually rises gradually, which can be considered as the equivalent resistance to increase the resistance. The PMOS transistor used as the resistor PR1 does not turn on completely after five to ten nanoseconds. The use of the resistor PR1 has an active shutdown characteristic, which can effectively reduce the return effect β to less than 0.4V. As shown in FIG. 5, the output waveform of the input / output buffer 120 under the GTL + configuration of the present invention is reflected in Under the effect, the voltage at the -rebound point A (0.4V) is very close to the steady-state voltage. -Line · (Please read the precautions on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 (2) 0 X 297 mm 577twf.doc / 006 A / 46 6414__β7__ 5. Description of the invention (a;) Voi. (0.2.V). In summary, using the input and output buffers of the present invention supporting a variety of transmission logic buses as the connection between the chipset and the microprocessor through the transmission line, and the conventional technology have at least the following effects and advantages: The input and output buffers of the present invention supporting multiple transmission logic buses can automatically detect the type of processor inserted in the motherboard board slot, thereby adjusting the resistance configuration of the input and output pins of the chipset to suit different microprocessing Specifications of the transmission logic bus required by the processor. By using the input and output buffers of the present invention that support multiple transmission logic buses, the resistance configuration of the input and output pins of the chipset can be adjusted to use the same chipset to match different microprocessors. The present invention supports multiple input and output buffers of transmission logic buses, which supports the use of microprocessors of different specifications for transmission logic buses, so that the design and production of the motherboard do not need to invest in different labor and resources for different microprocessors. time. The input-output buffer of the present invention supporting a variety of transmission logic buses' Because components equivalent to pull-up resistors, termination resistors, and series resistors are formed in the input-output buffers in the chipset, the conventional knowledge can be saved. The large number of resistors installed on the motherboard can make the layout design of the motherboard more simplified and reduce the cost. In summary, although the present invention has been disclosed in the preferred embodiment as above, 'but it is not intended to limit the present invention, any person skilled in the art' can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching 'Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application. ------------- ^-. ^-11 ----- Order --------- Line — ((Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (2) 0 X 297 mm