DE19953842A1 - Data line for supporting several transmission logic buses e.g. connecting a microprocessor and chip set using one-output intermediate store having coordinating control - Google Patents

Abstract

The one-output intermediate store has a coordinating control, a logical control circuit for receiving a microprocessor type signal, NMOS transistors in which a connection of every transistor is connected with the one-output pad of the intermediate store while the other is grounded. The intermediate store receives signals and compares it with a reference voltage, an output voltage is sent to the coordinating control so that the resistance element is adjusted accordingly. An Independent claim is also included for a main circuit board structure.

Description

The present invention relates to a data transmission line. The present In particular, the invention relates to a data transmission line for connecting a Microprocessor and a chipset.

Generally, a microprocessor or a central processing unit (CPU) within a personal computer capable of using peripheral devices of a chipset to communicate. The chipset is an intermediate component for Exchange of data and control signals. The chipset has I / O ports which are coupled to a data transmission bus, the bus becoming a Connection leads above a main circuit board. Hence any one Microprocessor that is plugged into the connector, able to connect directly to the Communicate chipset.

Currently, the two most important bus specifications include gunning transmit Receive logic (GTL +) and high speed send-receive logic (HSTL). GTL + is a standard specification developed by INTEL for data transfer between a new generation of their microprocessors and external interfaces was created. The GTL + Bus is for high-speed microprocessors suitable, for example for the Pentium II, Pentium III, the Pentium Pro and the base 370. On the other hand, the HSTL bus is an alternative specification made by some microprocessors. The GTL + bus and the HSTL bus are in the Did two different types of specifications. Therefore, a chipset should be used to interfacing with a microprocessor using a GTL + bus, while another chipset is to be used to interface with one To form a microprocessor using an HSTL bus.

Figure 1 is a schematic diagram showing a GTL + data bus connecting a microprocessor to a chipset. Figure 2 is a schematic diagram showing an HSTL bus connecting another microprocessor to a chipset. A few similarities can be found between the transmission buses shown in Figures 1 and 2. The connection voltages V _TT are identical for both, for example V _TT = 1.5 V. The reference _voltages V _REF are also identical for both at approximately 1.0 V (if V _TT = 1.5 V), or V _REF = 2 / 3.V _TT or 0.68.V _TT . Both the GTL + bus 12 and the HSTL bus 22 use the same type of connectors 14 and 24 , which have identical dimensions. A microprocessor 16 with its own circuit board 16 a is shown in Fig. 1. The circuit board 16 a is connected to the connection 14 above the main circuit board in such a way that the microprocessor 16 is connected to the chipset 10 . Similarly, a microprocessor 26 with its own circuit board 26 a is shown in FIG. 2. The circuit board 26 a is connected to the connection 24 above the main circuit board in such a way that the microprocessor 26 is connected to the chipset 20 .

A comparison of the GTL + bus with the HSTL bus shows that their main difference lies in the arrangement of the transmission lines. The GTL + transmission line 12 in Fig. 1 has one or two terminating resistors R _{tt of} about 56 ohms to increase the level of the bus voltage. Since the resistor R _{tt is} also arranged near the end of the transmission line, the resistor also serves as a terminating resistor which is suitable for preventing a signal return. On the other hand, the HSTL transmission line 22 in FIG. 2 has two terminal resistances R _tt of approximately 100 ohms in order to increase the level of the bus voltage. The resistors R _tt do not serve as terminating resistors. The HSTL transmission line 22 further includes a series resistance R _S of approximately 22 ohms between the chipset 20 and the input / output (I / O) connections of the microprocessor 26 . Resistor R _S mainly serves as a damper for transmission signals.

The above-mentioned description explains that the GTL + bus and the HSTL bus are such are configured to two specifications from two different microprocessor To yield types. As a result, different chipsets have to be used. There a chipset usually installed by the manufacturer on the motherboard is one Selection of microprocessors for the user limited.  

The invention provides a chipset that supports various Transmission buses is suitable, so that a user in the selection of the type of Microprocessor is free.

The invention provides an input-output buffer that is used to detect the type a microprocessor is suitable, which in the connection on a Main circuit board is inserted. First is the type of microprocessor known, then a suitable resistor can automatically be connected to the input / output Connections of a chipset are connected to the transmission bus of this to operate a special type of microprocessor.

The invention also provides an input-output buffer for adjustment the size of the resistor is suitable, which at the input-output terminals of a Chipset is connected. The same chipset can therefore be used to operate different types of microprocessors are used, each one have different transmission bus specification.

The invention also provides an I / O cache, the special one Has circuits that reduce unwanted returns from one Transmission bus and are suitable for reducing power consumption.

To achieve these and other benefits and in accordance with the goal of this Invention as illustrated and described in detail herein provides the invention an input-output buffer that supports multiple transmission buses suitable is. The I / O cache is through multiple transmission lines with different connections of a connector of a microprocessor connected. The I / O cache includes a coordinating controller; a logic control circuit for receiving a microprocessor type signal from a microprocessor; a first transistor and a second transistor in which a connection of each transistor with an input-output pad of the input-output Buffer is coupled while another connector is grounded and one Control terminal of each transistor is coupled to the logic control circuit; a first resistance element with three connections, a connection with a  Connection voltage source is coupled, while another connection with a Connection of the first transistor is coupled, and a control connection of the first Resistor element is coupled to the coordinating controller; a second Resistor element with three connections, one connection with a Connection voltage source is coupled, while another connection with a Connection of the second transistor is coupled; one control port of the second Resistance element is able to receive a control signal, so that the electrical conductivity of the second resistance element can be set; and a buffer with three connections, one connection with the input Output pad is coupled, one connector with the reference voltage and one Connection is coupled to the coordinating control. The cache receives a signal from the input pad and compares the signal with the Reference voltage to generate an output voltage. The output voltage will sent to the coordinating controller so that the resistance of the first Resistance element is set accordingly.

When the detection signal from the microprocessor is at a first voltage level is, for example with a logical status of "1", then both remain the first Transistor and the second resistor conductive. The transmission line is configured for example according to the HSTL bus specification. However, if that Detection signal from the microprocessor is at a second voltage level, for example with a logic status of "0", then all remain, the first transistor, the second transistor and the first resistor are conductive. The transmission line is configured for example according to the GTL + bus specification.

It is clear that the foregoing general description as well as the following detailed description are exemplary and further explanation of this Invention as claimed should deliver.

The accompanying drawings are attached to provide a better understanding of the invention to deliver, and they are incorporated and form part of this description Drawings explain embodiments of the invention and serve, together with the description to explain the basics of the invention. In the drawings is  

Fig. 1 is a schematic diagram showing a GTL + -Datenübertragungsbus connecting a microprocessor to a chipset;

Figure 2 is a schematic diagram showing an HSTL communication bus connecting another microprocessor to a chipset;

Fig. 3 is a schematic diagram showing interconnections of the present invention between an input-output buffer, a chipset and a microprocessor;

Fig. 4 is a schematic diagram showing, according to the invention, the internal connections between different elements within the input-output buffer; and

Fig. 5 originates a schematic diagram showing an output waveform with a reduced return signal from the combined function of coordinating control and the resistors within the input-output buffer.

The following is a detailed discussion of the currently preferred embodiments of the Invention reference made, which exemplifies in the accompanying drawings become. Wherever possible, the same reference numbers will be used in both Drawings as well as used in the description to point to the same or similar Point out parts.

FIG. 3 is a schematic diagram and shows the connection lines according to the invention between an input / output buffer, a chipset and a microprocessor. As shown in FIG. 3, an input-output buffer 120 within a chipset 110 above a motherboard 100 is connected to a microprocessor module by means of transmission lines 102 . According to the invention, the usual terminal resistance R _tt and the series resistance R _S , which normally belong to a circuit on a motherboard, are eliminated. Nonetheless, chipset 120 is capable of supporting both GTL + and HSTL transmission logic buses.

In addition, a resistor R _S (not shown) can be added between an output of the buffer 120 and the transmission line 102 depending on the current need.

Since a microprocessor for data transmission can have over a hundred connections, the removal of the terminating resistor R _tt and the series resistor R _S saves manufacturing costs and reduces the complexity of the connecting lines on the main board. The following is a detailed description of a layout of the I / O cache that supports both the GTL + and HSTL transfer logic buses.

Fig. 4 is a schematic diagram showing the internal connections according to the invention between different elements within the input-output buffer.

The input-output buffer 120 according to the invention is connected by means of the transmission lines 102 to a microprocessor connector 104 . The input-output buffer 120 includes a coordinating controller 122 , a logic control circuit 124 , a first one. Transistor. MIN1, a second transistor MN2, an input-output pad 126 , a first controllable resistor PR1, a second controllable resistor RNU and a buffer 128 . The logic control circuit 124 has an input connection for receiving a microprocessor type signal K7 when a specific microprocessor type is inserted into the connector plug 104 . The logic control circuit 124 can identify the microprocessor type from this signal K7, so that the input / output buffer can respond accordingly. The first transistor MN1 and the second transistor MN2 are coupled to the logic control circuit and the input-output pad. Both the first transistor MN1 and the second transistor MN2 are controlled by the logic control circuit 124 . The passage of the transistors MN1 and MN2 can be opened or closed depending on the signal K7. The first and second transistors MN1 and MN2 can be NMOS transistors, for example.

The first resistor PR1 is coupled to a supply voltage source V _TT and one end of the first transistor MN1. The conductivity of the first resistor PR1 can be changed with signals from the coordinating controller 122 to a control connection of the resistor PR1. For example, a voltage of approximately 1.5 V can be applied to the terminal voltage source V _TT and the resistor PR1 can be an NMOS transistor. The second resistor RNU is coupled to a supply voltage source V _TT and to one end of the second transistor MN2. The second resistor RNU also has a third connection for receiving a control signal PU, which is suitable for controlling the conductivity of the resistor RNU itself. The equivalent resistance of the second resistor RNU is approximately 100 ohms and depends on the specification of the transmission bus. Resistor RNU can be implemented using either a PMOS or an NMOS transistor. Alternatively, the resistor RNU can be implemented using a resistor and a PMOS transistor that are connected in series to each other and to the resistor with a resistance value of about 80 ohms.

The latch 128 has two input ports and one output port. One of the input terminals is connected to the input-output pad 126 for receiving a signal voltage V _IN . The other input terminal is connected to the reference _voltage V _REF . The signal voltage V _IN is compared to the reference voltage to generate a voltage signal V. The voltage signal V is sent to the coordinating controller 122 , so that the resistance value of the first resistor PR1 can be adjusted accordingly. In general, the resistance value of the resistors PR1, RNU and the transistors MN1, MN2 can be designed according to the current specification of the individual logic bus to be supported.

When the microprocessor type signal K7 received by the logic control circuit 124 is at a first potential such as a logic status of "1", the passages of both the first transistor MN1 and the second resistor RNU are conductive. Transmission line 102 will operate in accordance with the specification of the first type of transmission bus. Indeed, if the RNU resistor is rated at about 100 ohms while the equivalent resistor is rated at about 22 ohms, then the first type of transmission bus is an HSTL bus. On the other hand, when the signal K7 received by the logic control circuit 124 is at a second potential such as a logic status of "0", the passages of the first transistor MN1, the second transistor MN2 and the first resistor PR1 all leading. The transmission line 102 will function in accordance with the specification of the second type of transmission bus, for example a GTL + bus.

The following are the two main transmission bus specifications, including the GTL + bus and the HSTL bus used to implement these To explain the invention.

As shown in FIG. 4, when a microprocessor operating with an HSTL bus specification is plugged into connector 104 , a signal is sent to microprocessor type connector K7 of logic control circuit 124 . Provided that a logic status of "1" represents a microprocessor using an HSTL bus, resistor RNU and transistor MN1 are switched to be conductive. The resistor RNU and the transistor MN1 become the main working components of the input-output latch 120 . The resistance value of the transistor MN1 in the conductive state is designed such that it is approximately equal to the sum of the series resistance R _S and the resistance value when the input-output buffer is conductive, as shown in FIG. 2. Therefore, the resistor R _S on the main board is no longer needed. In addition, the resistor RNU can be designed to have a resistance value of approximately 100 ohms and to serve as a terminal resistor. After a suitable setting, the resistance RNU can drop in the range required by the bus specification. Therefore, a circuit equivalent to the HSTL bus in FIG. 2 is formed on the main board without the need for a terminating resistor R _TT and a series resistor R _S.

Similarly, as shown in FIG. 4, when a microprocessor operating with a GTL + bus specification is plugged into connector 104 , a signal is sent to microprocessor-type connector K7 of logic control circuit 124 . Provided that a logic status of "0" represents a microprocessor using a GTL + bus, resistor PR1 and transistors MN1 and MN2 are turned on. Therefore, resistor PR1 and transistors MN1 and MN2 will be conductive and will become the main operational components of I / O latch 120 . The resistor RNU is now closed. The combined resistance value of the resistor PR1 and the transistors MN1 and MN2 can be designed such that it is equal to the resistance value, as seen with the GTL + bus in FIG. 1. Therefore, the terminating and terminating resistor R _TT on the main board is no longer required.

In short, when the microprocessor module 130 is plugged into the connector 104 , a signal is sent to the connector K7 of the logic control circuit 124 , which informs about the type of microprocessor used. In response, some components selected from the group consisting of resistors PR1 and RNU and transistors MN1 and MN2 are made conductive and create a suitable environment for operating a microprocessor. Therefore, the I / O cache can support at least these two types of transfer logic buses by generating a microprocessor type signal K7. In addition, when the GTL + transmission logic configuration is selected, the coordinating controller 122 is activated to reduce returns in the circuit and reduce power consumption.

The resistor PR1 can be implemented using a PMOS transistor. When the voltage of the input-output pad 126 is a voltage of about 1.0 V to 1.5 V, the coordinating controller outputs an output signal of 0 V, so that the resistor PR1 is at a resistance value of 100 to 200 ohms is leading. As soon as the voltage at the input-output pad 126 drops to a voltage below 1.0 V, the control voltage of the PMOS transistor, which serves as a resistance element PR1, gradually increases. As a result, the equivalent resistance value of the PMOS transistor also increases. After five to ten nano seconds, the PMOS transistor appears to become non-conductive.

The use of an actively switchable resistor of the type PR1 has the advantage that signal returns are regulated down to a voltage of less than about 0.4 V. Fig. 5 is a graph showing an output waveform of an input output latch with the GTL + bus configuration, showing a return reduction. As shown in Fig. 5, the peak voltage (0.4 V) at point A of the first return is still quite close to the basic voltage V _OL (0.2 V).

In summary, the I / O cache of this invention includes at least the following advantages:

• 1. The I / O cache is capable of the microprocessor type detect that is plugged into the connector on the main circuit board is. Once the type of microprocessor is recognized, the appropriate size can be chosen the resistance value at the input / output connections of the chipset can be connected to the transmission bus for this particular type of Operate microprocessor.
• 2. Since the I / O cache is able to size the Resistance value on the input-output connections of the chipset connected, different types of Microprocessors use the same circuit board.
• 3. Since the same chipset can be used in microprocessor systems that have different bus specifications, is the design and production the main circuit board easier.
• 4. As equivalent terminating resistors, connecting resistors and series resistors compiled within the I / O cache on the chipset many resistors can be omitted, which is usually a common one Main circuit board can be assigned. That is why the manufacturing cost reduced and is the complexity of the line connections on one Main circuit board greatly simplified.

It is clear to those skilled in the art that various modifications to the Structure of the present invention can be made without the scope or to leave the idea of the invention. In view of the above, it is intended  that the present invention the modifications and variations of this invention with the proviso that they fall within the scope of the following claims and their equivalents fall.

Claims (19)

1. An I / O buffer that can support multiple transmission buses, the I / O buffer being connected to a microprocessor connector by transmission lines, and comprising:
coordinating control;
a logic control circuit for receiving a microprocessor type signal;
a first transistor and a second transistor coupled to the logic control circuit and an input-output pad of the input-output latch, both the first and second transistors being controlled by the logic control circuit;
a first resistance element coupled to a terminal voltage source and a terminal of the first transistor, the first resistance element being controlled by the coordinating controller;
a second resistance element coupled to a terminal voltage source and a terminal of the second transistor, the second resistance element also being able to receive an external control signal for determining its conductivity status; and
a latch for receiving a signal voltage, an input terminal connected to a reference voltage, and wherein the signal voltage is compared to the reference voltage to generate an output voltage for the coordinating controller, whereupon the coordinating controller then the resistance value of the first resistance element according to the output voltage of the Cache changed,
wherein when the microprocessor detection signal is at a first voltage level, the first transistor and the second resistance element are conductive so that the transmission line follows the specification of a first transmission bus, whereas when the microprocessor detection signal is at a second voltage level that the first transistor, the second transistor, and the first resistance element are all conductive so that the transmission line follows the specification of a second transmission bus. 2. An output latch according to claim 1, wherein the first transistor and the second transistor is NMOS transistors. 3. An output buffer according to claim 1, wherein the equivalent Resistance value of the second resistance element is approximately 100 ohms. 4. An output buffer according to claim 1, wherein the second Resistor element is realized using an NMOS transistor. 5. An output buffer according to claim 1, wherein the second Resistor element using a PMOS transistor and a Resistance is realized. 6. An output latch according to claim 5, wherein the resistance value of the Resistance element is about 80 ohms. 7. An output latch according to claim 1, wherein a voltage of about 1.5 V is applied to the supply voltage source. 8. An output latch according to claim 6, wherein a voltage of about 1.0 V is applied to the reference voltage connection of the buffer. 9. An output latch according to claim 1, wherein a microprocessor Detection signal at a logic level "1" indicates that the first  Transmission logic bus a high-speed transmit-receive logic (HSTL) bus simulated. 10. An output latch according to claim 1, wherein a microprocessor Detection signal at a logic level of "0" indicates that the second Transmission logic bus a gunning send-receive logic (GTL +) bus simulated. 11. Main circuit board structure, comprising:
a microprocessor connector ready to insert a microprocessor so that a microprocessor type signal is generated when the microprocessor is inserted into the connector;
a chipset having an I / O latch, the I / O latch receiving the microprocessor type signal and being able to adjust the chipset to operate with a transmission bus specification suitable for operating the microprocessor; and
a transmission line structure to couple the chipset's I / O cache to the microprocessor connector. 12. The main circuit board structure of claim 11, wherein the input-output latch further comprises:
coordinating control;
a logic control circuit for receiving a microprocessor type signal;
a first transistor and a second transistor, respectively, coupled to the logic control circuit and an input-output pad of the input-output latch, both of the first and second transistors being controlled by the logic control circuit;
a first resistance element coupled to a terminal voltage source and a terminal of the first transistor, the first resistance element being controlled by the coordinating controller;
a second resistance element, which is coupled to a connection voltage source and a connection of the second transistor, wherein the second resistance element can also receive an external control signal for determining its conductivity status; and
a latch for receiving a signal voltage, an input terminal connected to a reference voltage, and wherein the signal voltage is compared to the reference voltage to generate an output voltage for the coordinating controller, whereupon the coordinating controller then the resistance value of the first resistance element according to the output voltage of the Cache changed,
wherein when the microprocessor detection signal is at a first voltage level, the first transistor and the second resistance element are conductive so that the transmission line follows the specification of a first transmission bus, whereas when the microprocessor detection signal is at a second voltage level that the first transistor, the second transistor, and the first resistance element are all conductive so that the transmission line follows the specification of a second transmission bus. 13. The main circuit board structure of claim 12, wherein the first transistor and the second transistor are NMOS transistors. The main circuit board structure of claim 12, wherein the equivalent Resistance value of the second resistance element is approximately 100 ohms.   15. The main circuit board structure according to claim 12, wherein the first and the second resistance element are selected from a group consisting of PMOS transistors and NMOS transistors. 16. The main circuit board structure of claim 12, wherein a voltage of about 1.5 V is applied to the supply voltage source. 17. The main circuit board structure of claim 16, wherein a voltage of about 1.0 V is applied to the reference voltage connections of the buffer becomes. The main circuit board structure of claim 12, wherein a microprocessor Detection signal at a logic level of "1" indicates that the first Transmission logic bus a high speed transmission logic (HSTL) - Bus simulated. 19. The main circuit board structure of claim 12, wherein a microprocessor Detection signal at a logic level of "0" indicates that the second Transmission logic bus a gunning send-receive logic (GTL +) bus simulated.