DE19953842B4 - To support multiple transfer logic buses, appropriate I / O buffer - Google Patents

Abstract

An output buffer (120) capable of supporting a plurality of transmission buses, the input-output buffer (120) connected to a microprocessor connector (104) through transmission lines (102), and comprising:
a coordinating controller (122);
a logic control circuit (124) for receiving a microprocessor-type signal;
a first transistor (MN1) and a second transistor (MN2) coupled to the logic control circuit (124) and an input-output pad (126) of the input-output latch (120), both the first and second the second transistor (MN1, MN2) is controlled by the logic control circuit (124);
a first resistance element (PR1) coupled to a terminal voltage source and a terminal of the first transistor (MN1), the first resistance element being controlled by the coordinating controller (122);
a second resistance element (RNU) coupled to a terminal voltage source and a terminal of the second transistor (MN2), the second resistance element also being capable of receiving an external control signal to determine its conductivity status; and
a cache memory (128) for receiving a ...

Description

The The present invention relates to an input-output buffer according to claim 1 and a main circuit board structure according to claim 11, this input-output buffer according to claim 1 has.

in the Generally, it is a microprocessor or central processing unit (CPU) within a personal computer capable of using peripheral devices to communicate by means of a chipset. The chipset is a Intermediate device for exchanging data and control signals. The chipset has I / O ports on, which is connected to a data transfer bus are coupled, the bus to a port above a Main circuit board leads. Therefore, any microprocessor that is plugged into the port is able to communicate directly with the chipset.

Currently, the two most important bus specifications include Gunning Transceiver Logic (GTL +) and High Speed Transceiver Logic (HSTL). GTL + is a standard specification created by INTEL for data transfer between a new generation of its microprocessors and external interfaces. The GTL + bus is suitable for high-speed microprocessors such as the Pentium II, Pentium III, Pentium Pro, and socket 370 , On the other hand, the HSTL bus is an alternative specification used by some microprocessors. The GTL + bus and the HSTL bus are in fact two different types of specifications. Therefore, a chipset should be used to interface with a microprocessor using a GTL + bus while using another chipset to interface with a microprocessor using an HSTL bus.

1 Figure 16 is a schematic diagram showing a GTL + data bus connecting a microprocessor to a chipset. 2 Figure 4 is a schematic diagram showing an HSTL bus connecting another microprocessor to a chipset. Between the transfer buses, the in 1 and 2 a few similarities can be found. The terminal voltages V _TT are identical for both, for example, V _TT = 1.5 V. Also, the reference _voltages V _REF are identical for both at about 1.0 V (when V _TT = 1.5 V), or V _REF = 2 / 3 · V _TT or 0.68 · V _TT . Both, the GTL + bus 12 and the HSTL bus 22 use the same type of connectors 14 and 24 that have identical dimensions. A microprocessor 16 with his own circuit board 16a is in 1 shown. The circuit board 16a is at the connection 14 above the main circuit board connected such that the microprocessor 16 with the chipset 10 connected is. Similar is in 2 a microprocessor 26 with his own circuit board 26a shown. The circuit board 26a is at the connection 24 above the main circuit board connected such that the microprocessor 26 with the chipset 20 connected is.

A comparison of the GTL + bus with the HSTL bus shows that their difference lies mainly in the arrangement of the transmission lines. The GTL + transmission line 12 in 1 has one or two terminating resistors R _{tt of} about 56 ohms to increase the level of the bus voltage. In addition, since the resistor R _{tt is located} near the end of the transmission line, the resistor also serves as a terminating resistor capable of preventing a signal retrace. On the other side, the HSTL transmission line points 22 in 2 two terminating resistors R _tt of about 100 ohms to increase the level of the bus voltage. The resistors R _tt are not used as terminating resistors. The HSTL transmission line 22 also includes between the chipset 20 and the I / O ports of the microprocessor 26 a series resistance R _S of about 22 ohms. The resistor R _S serves mainly as a damper for transmission signals.

The mentioned above Description explains that the GTL + bus and the HSTL bus are configured to two Specifications of two different types of microprocessor. As a result, must different chipsets to be used. As a chipset usually is installed by the manufacturer on the motherboard is a choice of the microprocessors for limited the user.

EP 0 574 991 A1 discloses a data processing system having a mainboard provided with a socket for installation of any type of microprocessor of the same family, the family microprocessors being incompatible with the specific functions of the predetermined microprocessor pins.

WO 93/08532 A2 discloses a microcomputer system including a motherboard with EISA daughterboard sockets and a processor board. The processor board BIOS program is stored on the motherboard in flash memory. A permanent BIOS program, also located on the motherboard, has program code for a routine to check if the BIOS in flash memory is suitable for a particular type of processor board.

US 4,287,563 A discloses a microppro processor interface circuit, which makes it possible to use single peripheral and memory device with at least two different types of microprocessor. The interface includes a latch which latches the state of a control signal provided to the peripheral / storage device by the microprocessor.

in the The prior art gives rise to the problem that the various Standards for different transmission buses Different types of microprocessor require each are bound to one of these standards. This problem is going through the present invention according to claim 1 and according to claim 11 solved, the present invention provides an input-output buffer and a main circuit board structure with this input-output buffer which provides various transfer buses supported and thus this binding of microprocessor type to the respective bus standard picks up, leaving a user in the selection of the type of microprocessor free is.

The The invention provides an input-output buffer for detection of the type of microprocessor used in the terminal is plugged into a main circuit board. Is the type of Once known microprocessor, then automatically a matching Resistor connected to the input / output terminals of a chipset be to the transfer bus operate this special type of microprocessor.

The The invention also provides an input-output buffer that for adjusting the size of the resistor which is connected to the input-output terminals of a chipset is. The same chipset can therefore be used to operate different Types of microprocessors are used, each having a different transmission bus specification.

The The invention also provides an input-output buffer which is special Circuits having the purpose of reducing unwanted returns from a transmission bus and are suitable for lowering the power consumption.

to Achieve these and other benefits and in line with the goal of this invention as illustrated and described in detail herein is the invention provides an input-output buffer, the for support several transmission buses suitable is. The input-output buffer is through several transmission lines with different connections connected to a connector of a microprocessor. The input-output buffer includes a coordinating controller; a logical control circuit for receiving a microprocessor-type signal from a microprocessor; a first transistor and a second transistor, in which one terminal of each transistor with an input-output pad the input / output buffer is coupled while another connection is grounded and a control terminal of a each transistor is coupled to the logic control circuit; a first resistor element with three terminals, wherein a terminal with a terminal voltage source is coupled while another terminal is coupled to a terminal of the first transistor, and a Control terminal of the first resistive element with the coordinating control is coupled; a second resistance element with three terminals, wherein a terminal is coupled to a terminal voltage source, while another terminal having a terminal of the second transistor is coupled; wherein a control terminal of the second resistive element is able to receive a control signal, so that the electrical conductivity the second resistance element can be adjusted; and one Buffer with three connections, wherein a terminal is coupled to the input-output pad, wherein one terminal with the reference voltage and one terminal with the coordinating control is coupled. The cache receives Signal from the input pad and compares the signal to the reference voltage, to generate an output voltage. The output voltage becomes too sent to the coordinating controller so that the resistance of the first resistance element is set accordingly.

If the detection signal from the microprocessor at a first voltage level is, for example, at a logical status of "1", then Both the first transistor and the second resistor remain conductive. The transmission line is for example, according to the HSTL bus specification configured. However, if the detection signal from the microprocessor at a second voltage level, for example at a logical status of "0", then stay all, the first transistor, the second transistor and the first resistance conductive. The transmission line is configured according to the GTL + bus specification, for example.

The accompanying drawings are attached to provide a better understanding of Invention, and they are incorporated and make up a part of this description. The drawings illustrate embodiments of the invention and serve, together with the description, for explanation the basics of the invention. In the drawings is

1 a schematic diagram showing a GTL + Datenübertragungsbus according to the prior art connecting a microprocessor to a chipset;

2 a schematic diagram showing a HSTL data transfer bus according to the prior art, which connects another microprocessor with a chipset;

3 a schematic diagram showing the connection lines between an input-output buffer, a chipset and a microprocessor;

4 a schematic diagram showing the internal connections between various elements within the input-output buffer according to the invention; and

5 12 is a schematic diagram showing an output waveform having a reduced return signal resulting from the combined function of the coordinating controller and the resistors within the input / output buffer of the present invention.

in the The following will be in detail on the present preferred embodiments of the invention, by way of example in the accompanying Drawings explained become. Wherever possible the same reference numbers will be used both in the drawings as well Also used in the description to refer to the same or similar To point out parts.

3 Fig. 12 is a schematic diagram showing the connection lines between an input-output buffer, a chipset, and a microprocessor. As in 3 is an input / output buffer 120 within a chipset 110 above a motherboard 100 with a microprocessor module via transmission lines 102 connected. According to the invention, the usual terminal resistance R _tt and the series resistance R _{S are} eliminated, which normally belong to a circuit on a motherboard. Nonetheless, the chipset is 120 able to support both GTL + and HSTL transmission logic buses. In addition, a resistor R _S (not shown) may be connected between an output of the latch, depending on the current need 120 and the transmission line 102 to be added.

Since a microprocessor can have hundreds of ports for data transmission, the removal of the terminal resistor R _tt and the series resistor R _S saves manufacturing costs and reduces the complexity of the interconnect lines on the motherboard. The following is a detailed description of a layout of the input-output buffer that simultaneously supports the GTL + and the HSTL transfer logic buses.

4 Figure 3 is a schematic diagram showing the internal connections between various elements within the input / output buffer of the present invention.

The input-output buffer according to the invention 120 is by means of the transmission lines 102 with a microprocessor connector 104 connected. The input-output buffer 120 includes a coordinating controller 122 , a logical control circuit 124 , a first transistor MN1, a second transistor MN2, an input-output pad 126 , a first controllable resistor PR1, a second controllable resistor RNU and a latch 128 , The logical control circuit 124 has an input port for receiving a microprocessor-type signal K7 when a particular type of microprocessor enters the connector 104 is plugged in. From this signal K7, the logical control circuit 124 identify the microprocessor type so that the I / O buffer can respond accordingly. The first transistor MN1 and the second transistor MN2 are coupled to the logic control circuit and the input-output pad, respectively. Both the first transistor MN1 and the second transistor MN2 are controlled by the logic control circuit 124 controlled. The passages of the transistors MN1 and MN2 may be opened or closed depending on the signal K7. The first and second transistors MN1 and MN2 may be, for example, NMOS transistors.

The first resistor PR1 is coupled to a terminal voltage source V _TT and one end of the first transistor MN1. The conductivity of the first resistor PR1 can be controlled by signals from the coordinating controller 122 be changed to a control terminal of the resistor PR1. For example, a voltage of about 1.5V may be applied to the terminal voltage source V _TT , and the resistor PR1 may be an NMOS transistor. The second resistor RNU is coupled to a terminal voltage source V _TT and to one end of the second transistor MN2. The second resistor RNU also has a third terminal for receiving a control signal PU, which is suitable for controlling the conductivity of the resistor RNU itself. The equivalent resistance of the second resistor RNU is about 100 ohms and depends on the specification of the transfer bus. The resistor RNU may be implemented using either a PMOS or an NMOS transistor. Alternatively, the resistor RNU may be implemented using a resistor and a PMOS transistor connected in series with each other and with the resistor having a resistance of about 80 Ohm are connected.

The cache 128 has two input ports and one output port. One of the input terminals is with the input-output pad 126 connected to receive a signal voltage V _IN . The other input terminal is connected to the reference _voltage V _REF . The signal voltage V _IN is compared with the reference voltage to generate a voltage signal V. The voltage signal V becomes the coordinating control 122 is sent, so that the resistance of the first resistor PR1 can be adjusted accordingly. In general, the resistance of resistors PR1, RNU and transistors MN1, MN2 can be designed according to the current specification of the single logic bus to be supported.

If the microprocessor type signal K7, that of the logic control circuit 124 is at a first potential such as a logic state of "1", the passages of both, the first transistor MN1 and the second resistor RNU, are conductive. The transmission line 102 will work according to the specification of the first type of transfer bus. If the RNU resistor is rated at about 100 ohms while the equivalent resistor is rated at about 22 ohms, then the first type of transfer bus is indeed an HSTL bus. On the other hand, if the signal K7, that of the logic control circuit 124 is received, at a second potential is like a logic state of "0", the passages of the first transistor MN1, the second transistor MN2 and the first resistor PR1 all conductive. The transmission line 102 will work according to the specification of the second type of transmission bus, for example a GTL + bus.

in the Following are the two main transmission bus specifications, including the GTL + bus and the HSTL bus, used to the embodiments to explain this invention.

If, as in 4 a microprocessor operating with an HSTL bus specification is shown in the connector 104 is plugged, then a signal to the microprocessor-type terminal K7 of the logic control circuit 124 sent. Provided that a logic state of "1" represents a microprocessor using an HSTL bus, the resistor RNU and the transistor MN1 are switched to be conductive. The resistor RNU and the transistor MN1 become the main operating components of the input-output buffer 120 , The resistance of the transistor MN1 in the conductive state is designed to be approximately equal to the sum of the series resistance R _s and the resistance value when the input-output buffer is conductive, as in FIG 2 will be shown. Therefore, the resistance R _S on the motherboard is no longer needed. In addition, the resistor RNU can be designed to have a resistance of about 100 ohms and to serve as a terminal resistor. After appropriate adjustment, the resistor RNU may fall within the range required by the bus specification. That is why one to the HSTL bus in 2 equivalent circuit without the need for a terminal resistor R _TT and a series resistor R _{S formed} on the motherboard.

Similarly, as in 4 shown a signal when a microprocessor working with a GTL + bus specification, in the connector 104 is plugged to the microprocessor-type terminal K7 of the logic control circuit 124 sent. Provided that a logic state of "0" represents a microprocessor using a GTL + bus, the resistor PR1 and the transistors MN1 and MN2 are turned on. Therefore, the resistor PR1 and the transistors MN1 and MN2 will be conductive and become the main operating components of the input-output buffer 120 , The resistor RNU is now blocked. The combined resistance of the resistor PR1 and the transistors MN1 and MN2 may be designed to be equal to the resistance value as in the GTL + bus in FIG 1 seen, is. Therefore, the terminating resistor R _TT on the motherboard is no longer needed.

In short, if the microprocessor module 130 in the connector 104 is plugged, then a signal to the terminal K7 of the logic control circuit 124 sent informing about the type of the used microprocessor. In response, some components selected from the group consisting of resistors PR1 and RNU and transistors MN1 and MN2 are turned on and generate a suitable environment for operating a microprocessor. Therefore, by generating a microprocessor-type signal K7, the I / O buffer can support at least these two types of transfer logic buses. In addition, when the GTL + transmission logic configuration is selected, the coordinating control is 122 to reduce feedback in the circuit and reduce power consumption.

The resistor PR1 can be realized using a PMOS transistor. When the voltage of the input-output pad 126 is a voltage of about 1.0V to 1.5V, then the coordinating controller outputs an output signal of 0V, such that the resistor PR1 is conductive at a resistance of 100 to 200 ohms. Once the voltage on the input-output pad 126 falls to a voltage below 1.0 V, gradually increases the control voltage of the PMOS transistor, which serves as a resistance element PR1. As a result, the equivalent resistance of the PMOS transistor also grows. After five to ten nanoseconds, the PMOS transistor appears to be nonconductive.

The use of an actively switchable resistor type PR1 has the advantage that signal returns are regulated down to a voltage of less than about 0.4V. 5 FIG. 12 is a graphical representation of an output waveform from an input-output latch having the GTL + bus configuration and showing some retrace reduction. FIG. As in 5 The peak voltage (0.4V) at point A of the first return is still quite close to the fundamental voltage V _OL (0.2V).

• 1. Der Ein-Ausgabe-Zwischenspeicher ist in der Lage den Mikroprozessor-Typ zu erfassen, der in dem Anschlussstecker auf der Hauptschaltungsplatine eingesteckt ist. Ist der Typ des Mikroprozessors einmal erkannt, dann kann die geeignete Größe des Widerstandwertes an den Ein-Ausgabe-Anschlüssen des Chipsatzes angeschlossen werden, um den Übertragungsbus für diesen bestimmten Typ von Mikroprozessor zu betreiben.
• 2. Da der Ein-Ausgabe-Zwischenspeicher in der Lage ist, die Größe des Widerstandwertes, der an den Ein-Ausgabe-Anschlüssen des Chipsatzes angeschlossen ist, einzustellen, können unterschiedliche Typen von Mikroprozessoren die gleiche Schaltungsplatine verwenden.
• 3. Da der gleiche Chipsatz bei Mikroprozessor-Systemen verwendet werden kann, die unterschiedliche Busspezifikationen besitzen, ist die Auslegung und die Produktion der Hauptschaltungsplatine einfacher.
• 4. Da gleichwertige Endwiderstände, Anschlusswiderstände und Serienwiderstände innerhalb des Ein-Ausgabe-Zwischenspeichers auf dem Chipsatz zusammengestellt werden, können viele Widerstände entfallen, die normalerweise einer üblichen Hauptschaltungsplatine zugeordnet werden. Deshalb sind die Herstellungskosten vermindert und ist die Komplexität der Leitungsverbindungen auf einer Hauptschaltungsplatine stark vereinfacht.

In summary, the input / output buffer according to the invention contains at least the following advantages:

• 1. The input-output buffer is capable of detecting the type of microprocessor plugged into the connector on the main circuit board. Once the type of microprocessor has been recognized, the appropriate size of resistance value can be connected to the chipset's I / O port to operate the transfer bus for that particular type of microprocessor.
• 2. Since the input-output buffer is capable of adjusting the size of the resistance value connected to the input-output terminals of the chipset, different types of microprocessors may use the same circuit board.
• 3. Since the same chipset can be used with microprocessor systems having different bus specifications, the design and production of the main circuit board is simpler.
• 4. Since equivalent terminating resistances, terminal resistances and series resistances are assembled within the input / output buffer on the chipset, many resistors normally associated with a common main circuit board can be eliminated. Therefore, the manufacturing cost is reduced and the complexity of the line connections on a main circuit board is greatly simplified.

Claims (18)

Input / output buffer ( 120 ), which can support a plurality of transmission buses, wherein the input-output buffer ( 120 ) with a microprocessor connector ( 104 ) through transmission lines ( 102 ) and comprising: a coordinating controller ( 122 ); a logical control circuit ( 124 ) for receiving a microprocessor-type signal; a first transistor (MN1) and a second transistor (MN2) connected to the logic control circuit (MN1) 124 ) and an input / output pad ( 126 ) of the input / output buffer ( 120 ), both of the first and second transistors (MN1, MN2) being connected by the logic control circuit ( 124 ) to be controlled; a first resistance element (PR1) coupled to a terminal voltage source and a terminal of the first transistor (MN1), the first resistance element being provided by the coordinating controller (PR1); 122 ) is controlled; a second resistance element (RNU) coupled to a terminal voltage source and a terminal of the second transistor (MN2), the second resistance element also being capable of receiving an external control signal to determine its conductivity status; and a cache ( 128 ) for receiving a signal voltage, wherein an input terminal is connected to a reference voltage (V _REF ), and wherein the signal voltage is compared with the reference voltage (V _REF ) to generate an output voltage for the coordinating control, whereupon the coordinating controller then sets the resistance value When the microprocessor detection signal is at a first voltage level, the first transistor (MN1) and the second resistive element are conductive, so that the transmission line follows the specification of a first transmission bus, whereas then when the microprocessor detection signal is at a second voltage level, the first transistor (MN1), the second transistor (MH2) and the first resistive element are all conductive so that the transmission line ( 102 ) follows the specification of a second transmission bus. Input / output buffer ( 120 ) according to claim 1, wherein the first transistor (MN1) and the second transistor (MN2) are NMOS transistors. Input / output buffer ( 120 ) according to claim 1, wherein the equivalent resistance of the second resistive element is about 100 ohms. Input / output buffer ( 120 ) according to claim 1, wherein the second resistive element is realized using an NMOS transistor. Input / output buffer ( 120 ) according to claim 1, wherein the second resistive element is realized by using a PMOS transistor and a resistor. Input / output buffer ( 120 ) according to claim 5, wherein the resistance of the resistive element is about 80 ohms. Input / output buffer ( 120 ) according to claim 1, wherein a voltage of about 1.5 V is applied to the terminal voltage source. Input / output buffer ( 120 ) according to claim 6, wherein a voltage of about 1.0 V is applied to the reference voltage terminal of the buffer. Input / output buffer ( 120 ) according to claim 1, wherein a microprocessor detection signal at logic level "1" indicates that the first transmission logic bus is simulating a high speed transmit-receive logic (HSTL) bus. Input / output buffer ( 120 ) according to claim 1, wherein a microprocessor detection signal at a logic level of "0" indicates that the second transmission logic bus is simulating a running transmit-receive-logic (GTL +) bus. Main circuit board structure, comprising: a microprocessor connector ( 104 ), ready for insertion of a microprocessor, so that a microprocessor-type signal (K7) is generated when the microprocessor in the connector ( 104 ) is inserted; a chipset with an input-output buffer ( 120 ) according to one of the claims 1 to 10, wherein the input-output buffer ( 120 ) can pick up the microprocessor type signal and set the chipset to operate with a transmission bus specification suitable for operating the microprocessor; and a transmission line structure to connect the input-output buffer ( 120 ) of the chipset to couple with the microprocessor connector. Main circuit board structure according to claim 11, wherein the first transistor (MN1) and the second transistor (MN2) NMOS transistors are. Main circuit board structure according to claim 11, wherein the equivalent resistance of the second resistive element is about 100 ohms. Main circuit board structure according to claim 11, wherein the first and second resistive elements are of a group selected are, consisting of PMOS transistors and NMOS transistors. Main circuit board structure according to claim 11, a voltage of about 1.5V to the terminal voltage source is created. Main circuit board structure according to claim 15, wherein a voltage of about 1.0 V to the reference voltage terminals of Caching is created. Main circuit board structure according to claim 11, being a microprocessor detection signal at a logic level of "1" indicates that the first transfer logic bus a high-speed transmission logic (HSTL) bus simulated. Main circuit board structure according to claim 11, being a microprocessor detection signal at a logic level of "0" indicates that the second transfer logic bus simulates a Gunning transmit-receive-logic (GTL +) bus.