4 6 20 9 5 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（1 ) (技術領域） 本發明關於半導體製造技術，特別關於使用金突起之 覆晶接合適用之有效技術。 (背景技術） 依發明人檢討結果，搭載多數半導體晶片之模組製品 等半導體裝置（例如MCM ( Multi-Chip-Module )等）中 ，爲提升半導體晶片之實裝密度，多採用將半導體晶片面 朝下實裝於晶片支持基板的覆晶接合方式。 該覆晶接合中，半導體晶片與實裝之晶片支持基板間 之電連接有使用異方性導電樹脂（異方性導電薄膜、異方 性導電片、異方性導電膜、異方性導電糊、或ACF ( Anisotropic Conductive Film )之情形。 使用異方性導電樹脂之覆晶接合，係於半導體晶片之 '表面電極形成突起電極之金突起，之後，於晶片支持基板 黏貼異方性導電樹脂，俾於其上使突起電極及與其對應之 晶片支持基板之配線部介在有異方性導電樹脂呈面對，之 後進行熱壓接合以使半導體晶片與晶片支持基板介由異方 性導電樹脂做電連接。 又|晶片支持基板係採可以微細間距形成配線部之半 添加法形成，因此配線部之斷面形狀成凸形（梯形），於 角部形成傾斜面β 因此，配線部上部之連接面之寬小於底部寬1對安裝 於半導體晶片之金突起之配線部之配置餘裕變小爲其問題 本纸張&度適用令國國家標準（CNS)A4規格（210*297公窠> -4- -------— 1C---I ^ 1111111 ίιιιιί — — — (請先閲讀背面之注意事項再填寫本頁) 462095 ^ Α7 Β7 五、發明說明（2 ) 〇 (請先Μ讀背面之注意事項再填寫本頁) 又，配線部之連接面端部附近配置突起電極時，對半 導體晶片加壓時，突起電極有從配線部之連接面端部滑落 之況，結果突起電極與配線部間產生位移，造成電氣特 性餘裕度降低或與鄰接配線間之短路現象等問題。 又·造成半導體裝置良率降低等問題。 又，以突起進行覆晶接合，係揭示於例如特開昭6 2 -49636號公報'特開平10-107077號公報 、及特開平5- 1 2 9 3 70號公報。係揭示於配線部（ 包含平坦部）連接面形成凹溝或貫通槽或貫通孔，於配線 部之連接面定位突起之技術。 但是，覆晶接合時，對半導體晶片熱壓接合時，係於 半導體晶片施加特定何重*故而對突起之定位僅靠形成於 配線部之凹溝或貫通槽或貫通孔是不可靠的。又，突起使 用焊錫突起時，因焊錫流動導致鄰接配線部間之短路成爲 問題。 經濟耶智慧財產局員工消費合作社印划代 本發明目的在於提供一種可防止覆晶接合中突起電極 與晶片支持基板之配線部間之位移所導致電氣特性降低之 同時，可提升覆晶接合之信賴性的半導體裝置極其製造方 法。 本發明另一目的在於提供可提升覆晶接合之良率的半 導體裝置極其製造方法。 以下依圖面說明本發明之目的及特徵。 本紙張尺度適用中囷國家標準（CNS)A4規格（210 X 297公釐〉-5- 4 6 20 95 經濟部智慧財產局員工消費合作社印製 A7 _B7 五、發明說明（3 ) (發明之揭示） 本發明之半導體裝置，係具有：於主面形成有露出之 多數表面電極的上述半導體晶片：用於支持上述半導體晶 片，具備電連接上述半導體晶片之上述表面電極的配線部 ，於上述配線部之連接面形成有凹部的晶片支持基板：藉 由上述配線部之上述凹部被定位，介於上述半導體晶片之 上述表面電極與上述晶片支持基板之上述配線部之連接面 間用於連接上述表面電極與上述配線部的突起電極；及配 置於上述突起電極與配線部之連接處之周圍，用於保持上 述突起電極與配線部間之連接的異方性導電樹脂；上述突 起電極係藉由上述配線部之上述凹部被定位於上述配線部 之上述連接面。 本發明之半導體裝置，係具有：於主面形成有露出之 多數表面電極的上述半導體晶片：用於支持上述半導體晶 片，具備電連接上述半導體晶片之上述表面電極的配線部 及形成於其周圍的絕緣層，由上述配線部之設置面起之高 度形成低於上述絕緣層的晶片支持基板；連接較上述絕緣 層低之上述配線部之連接面，介於上述半導體晶片之上述 表面電極與上述晶片支持基板之上述配線部之連接面間用 於連接上述表面電極與上述配線部的突起電極：及配置於 上述突起電極與配線部之連接處之周圍，用於保持上述突 起電極與配線部間之連接的異方性導電樹脂；上述突起電 極，係藉由上述絕緣層被定位於上述配線部之上述連接面 本紙張瓦度適用中國國家標準<CNS)A4規格（210 x 297公釐）-6- n f tt I n f— I ·1^-eJI I I (锖先閱讀背面之注意事項再填寫本頁) 4 620 9 5 A7 _____ B7 五、發明說明（4 ) <請先閲讀背面之注意事項再填寫本頁) 又’本發明之半導體裝置，係具有：於主面形成有露 出之多數表面電極的上述半導體晶片；用於支持上述半導 體晶片’具備電連接上述半導體晶片之上述表面電極的配 線部及形成於其周圍的絕緣層，由上述配線部之設置面起 之高度形成低於上述絕緣層之同時，於上述配線部之連接 面形成有凹部的晶片支持基板；藉由較上述絕緣層低之上 述配線部之上述凹部被定位，介於上述半導體晶片之上述 表面電極與上述晶片支持基板之上述配線部之連接面間用 於連接上述表面電極與上述配線部的突起電極；及配置於 上述突起電極與配線部之連接處之周圍，用於保持上述突 起電極與配線部間之連接的異方性導電樹脂：上述突起電 極，係藉由上述配線部之上述凹部及上述絕緣層被定位於 上述配線部之上述連接面》 依此則覆晶接合時之半導體晶片壓接時，安裝於半導 體晶片之突起電極，係經由較配線部高之絕緣層導引配置 於配線部之連接面上|又，突起電極之前端附近插入連接 面凹部，故而藉_絕緣層及連接面之凹部可確實將突起電極 定位於連接面上。 經濟部智慧財產局員工消費合作社印製 結果，可防止突起電極與配線部間之位移，實現半導 體裝置之電氣特形提升及覆晶接合之接合信賴性。 又，本發明之半導體裝置之製造方法，係具有：準備 在主面形成有多數表面電極之半導體晶片的工程：準備具 備可電連接上述半導體晶片之上述表面電極的配線部’並 於上述配線部之連接面形成有凹部之晶片支持基板的工程 本纸張尺度適用+國國家標準（£^5)六4規格（210 * 297公釐） 4 6 2 0 9 ί7 Α7 Β7 五、發明說明（5) (請先Μ讀背面之注意事項再填寫本頁> :於上述半導體晶片之上述表面電極設突起電極的工程； 於上述晶片支持基板之晶片支持面配置異方性導電樹脂的 工程：使上述半導體晶片之上述主面與上述晶片支持基板 之上述晶片支持面介由上述異方性導電樹脂面對配置的工 程：對上述半導體晶片或晶片支持基板之任一方或兩者加 壓以使上述突起電極突破上述異方性導電樹脂的工程：藉 上述配線部之上述凹部定位上述突起電極據以定位上述晶 片支持基板及上述半導體晶片並連接上述配線部及上述突 起電極的工程：及使上述異方性導電樹脂硬化，藉上述異 方性導電樹脂保持上述突起電極與配線部間之連接以使上 述半導體晶片覆晶接合於上述晶片支持基板的工程。 經濟部智慧財產局員工消f合作社印*Jff 又，本發明之半導體裝置之製造方法，係具有：準備 在主面形成有多數表面電極之半導體晶片的工程；準備具 備可電連接上述半導體晶片之上述表面電極的配線部及形 成於其周圍之絕緣層，且由該配線部之設置面起之高度低 於上述絕緣層之晶片支持基板的工程；於上述半導體晶片 之上述表面電極設突起電極的工程；於上述晶片支持基板 之設有上述配線部之晶片支持面配置異方性導電樹脂的工 程：使上述半導體晶片之上述主面與上述晶片支持基板之 上述晶片支持面介由上述突起電極及異方性導電樹脂面對 配置的工程；對上述半導體晶片或晶片支持基板之任一方 或兩者加壓以使上述突起電極突破上述異方性導電樹脂的 工程：於上述絕緣層.及較其低之上述配線部所形成之段差 部藉上述絕緣層導引、定位上述突起電極後，定位上述晶 本纸張又度適用中國國家標準（CNS)A4規格（210 * 297公釐）-8- 462095 A7 B7 五、發明說明（6) (請先閱讀背面之注意事項再填寫本頁) 片支持基板及上述半導體晶片並連接上述配線部及上述突 起電極的工程；及使上述異方性導電樹脂硬化*藉上述異 方性導電樹脂保持上述突起電極與配線部間之連接以使上 述半導體晶片覆晶接合於上述晶片支持基扳的工程。 經濟部智慧財產局員工消費合作社印製 又，本發明之半導體裝置之製造方法，係具有：準備 在主面形成有多數表面電極之半導體晶片的工程；準備具 備可電連接上述半導體晶片之上述表面電極的配線部及形 成於其周圍之絕緣層，且由該配線部之設置面起之高度低 於上述絕緣層之同時，於上述配線部之連接面形成有凹部 之晶片支持基板的工程；於上述半導體晶片之上述表面電 極設突起電極的工程：於上述晶片支持基板之設有上述配 線部之晶片支持面配置異方性導電樹脂的工程；使上述半 導體晶片之上述主面與上述晶片支持基板之上述晶片支持 面介由上述突起電極及異方性導電樹脂面對配置的工程； 對上述半導體晶片或晶片支持基板之任一方或兩者加壓以 使上述突起電極突破上述異方性導電樹脂的工程；於上述 絕緣層及較其低之上述配線部所形成之段差部藉上述絕緣 層導引、定位上述突起電極後，藉上述配線部之上述凹部 定位上述突起電極據以定位上述晶片支持基板與上述半導 體晶片並連接上述配線部及上述突起電極的工程；及使上 述異方性導電樹脂硬化，藉上述異方性導電樹脂保持上述 突起電極與配線部間之連接以使上述半導體晶片覆晶接合 於上述晶片支持基板的工程。 本纸張尺度適用中國國家標準（CNS)A4規格（210x297公蓳）-9- 4620 9 5 A7 B7 五、發明說明（7 ) (發明之實施形態） (請先閱讀背面之沒意事項再填寫本頁》 以下，實施形態中必要以外同一或同樣之部分之說明 省略其重複說明。 又，以下實施形態中說明方便上，必要時分割成多數 部分或實施形態說明，但除特別明示以外，其等並非無關 係者，而是一方具另一方之一部分或全部之變形例、詳細 補足說明等之關係。 又，以下實施形態中，言及要素之數（包含個數、數 値、量、範圍等）時，除特別明示及原理上明顯限定特定 數以外，並未限定特定之數，而是特定數以上亦可》 以下依圖面說明本發明實施形態。又，實施形態說明 全圖中，具同一機能之構件者附加同一符號並省略重複說 明。 本發明實施形態1係式於圖1之半導體裝置（記億卡 _)之構造圖，圖2係覆晶接合部之圖，圖3 - 8係半導體 裝置之製造方法之圖。 經濟部智慧財產局員工消費合作社印*'< 圖1之本發明實施形態1之半導體裝置，係將4個記 憶晶片之半導體晶片藉覆晶接合方法實裝於薄形卡片基板 2 (晶片支持基板）形成記憶卡2 0。 亦即，記億卡2 0，係使用異方性導電樹脂（ ACF，Anisotropic Conductive Film ;亦稱異方性導電黏帶、 異方性導電片、或異方性導電薄膜等）將各個半導體晶片 1覆晶接合於1片薄卡片基板2形成之卡片製品。 記憶卡2 0，如圖4所示係由：於主面1 a形成有半 本紙張反度適用中國國家標準（CNSM4規格（210 X 297公釐）-10- 經濟部智«.財產局員工消費合作社印製 20 9 5 A7 ___B7___ 五、發明說明（8 ) 導體積體電路，且露出於主面1 a之同時形成有鋁構成之 多數電極lb (表面電極）的半導體晶片1 ;及支持半導 體晶片1且具電連接半導體晶片1之電極1 b的圖2所示 配線部2b及形成於其周圍之絕緣層2c·配線部2b之 由設置面2 d起之高度低於絕緣層2 c之同時，於配線部 2 b之連接面2 e形成有凹部2 ί的卡片基板2 ;及由較 絕緣層2 c低之配線部2 b之凹部2 f定位，介於半導體 晶片1之電極1 b與卡片基板2之配線部2 b之連接面 2 e間用於連接電極lb與配線部2 b之金突起4 (突起 電極）；及配置於金突起4與配線部2b之連接處之周圍 ·，且保持金突起4與配線部2b間連接的ACF3構成； 覆晶接合時，金突起4藉由圖2之配線部2 b之連接面 2 e之凹部2 f及絕緣層2 c被定位連接於絕綠層2 c之 連接面2 e。 亦即，圖1之記憶卡20，係於1片卡片基板2上， 分別介由ACF 3電連接之4個半導體晶片1以裸晶片狀 態被施予覆晶接合。 圖2之突起電極之金突起4，係藉標準接合技術（藉 導線接合裝置使用金線於半導體晶片1之電極1b形成突 起電極之技術）於半導體晶片1之電極1 a上接合形成者 ，此亦稱導線突起（但是，上述突起電極，非藉標準接合 技術形成之突起，而藉電鍍等形成亦可）。 又，實施形態1之卡片基板2之各配線部2 b上，在 與金突起4之連接面2 e上形成圖2之凹部2 f。於各配 本紙張及度適用中國國家標準（CNS>A4規格（210*297公芨）-11 · - ϋ ί— n - n - - l^i .. I u · I n ϋ -#-r»J« a— n ϋ k— n >. (請先M讀背面之注意事項再填寫本頁》 4 620 9 5 A7 _B7 五、發明說明（9 ) (請先閲讀背面之沒帝>事項再填寫本頁) 線部2 b周圍形成較該配線部2 b高之絕緣層2 c (表示 設置有配線部2 b之設置面2 d起之絕緣層2 c之高度大 於配線部2 b之高度，以下述及配線部2 b及絕緣層2 c 之高度關係時，均指由該設置面2d起之距離）《 該絕緣層2 c係阻劑膜，例如由環氧榭脂形成。 因此，實施形態1之記憶卡2 0之卡片基板2，如圖 5所示，設有對應半導體晶片1之各電極1 b配置之配線 部2 b及於其周圍形成較高之絕緣層2 c · 又，配線部2 b與絕緣層2 c間之設置面2 d起之高 度關係，如圖5所示，以配線部2 b之連接面2 e之最高 處之高度爲L，絕緣層2 c之高度爲Μ，配線部2 b之凹 部2 f之底部爲N時，有L<M'N<L、及N<M之關 係。 以下，說明卡片基板2之配線部2 b之形成方法。 配線部2 b之形成使用全添加法》 亦即，如圖5所示，於核心基板2 a表面形成加高層 之薄膜絕緣層2 h，再於其上層形成電鍍阻劑膜之絕緣層 2 c 〇 經濟部智慧財產局員工消費合作社印*'*找 之後，於絕緣層2 c使特定圖型（相當於配線部2 b 之圖型）曝光後，蝕刻上述圖型形成圖5 ( b )所示圖型 領域2 j 。再於圖型領域2 j電鍍埋入（成長）配線部 2b。 此時，蝕刻形成之圖型領域2 j中，上述電鍍層由絕 緣層2 c之內壁2 i起成長，故和配線部2 b之連接面 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）-12- A7 4 620 9 5 __B7_______ 五、發明說明（1(5 ) 2 e之中央附近比較內壁2 i附近較高，因此配線部2 b 之連接面2 e之中央附近形成凹部2 f。 晶片支持基板係以全添加法形成，故可形成微細圖型 ，如實施形態1所示，可形成記憶卡用卡片基板2作爲晶 片支持基板。 如圖（b )所示，於配線部2 b之連接面2 e之中央 附近形成有凹部2 f ，因此可製造周圍之絕緣層2 c較配 線部2 b高之晶片支持基板之卡片基板2。 又，配線部2 b係由鎳層或銅層構成，配線部2 b之 最上層連接面2 e上形成有金層。 A C F 3，如圖6所示，係由例如熱硬化性樹脂及其 所含鎳粒子等導電粒子3 a構成，導電粒子3 a係挾持於 半導體晶片1之電極1b上形成之金突起4與卡片基板2 之配線部2 b間作爲兩者之電連接用。但不介由導電粒子 3 a使金突起4與配線部2 b直接接觸藉上述熱硬化性樹 脂或其他接合材保持兩者之接觸狀態亦可。 又，A C F 3具有，加壓時樹脂被壓退，多數導電粒 子3 a結集於此之特性，因此，介由導電粒子3 a可電連 接金突起4與配線部2 b。 又，實施形態1之記憶卡2 0上，如圖1所示，於卡 片基板2之表面端部並列設置多數連接端子2 g (外部端 子）作爲與外部裝置之電連接。 又，依圖1之實施形態1之記憶卡2 0 ·覆晶接合時 之半導體晶片1之壓接時，半導體晶片1之電極1 b上安 本纸張瓦度適用中國國家標準（CNS)A4規格（210*297公爱）-13- I - ----- ---—I — C * — — — 1 — - I ^ · I I I I I I - i (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工湞費合作社印製 20 9 5 A7 _____B7__ 五、發明說明（11) 裝資突起電極之金突起4 ’經由形成較配線部2 b高之絕 緣層2 c導引、配置於配線部2 b之連接面2 e上。 亦即，絕緣層2 c作爲導引將金突起4導引至配線部 2b之連接面2 el。 又’金突起4之前端附近插入連接面2 e之凹部2 f ’因此藉絕緣層2 c與連接面2 e之凹部2 f可將金突起 4確實定位於連接面2 e上。 半導體晶片1加壓時，因金突起4之按壓使核心基板 2 a上之薄膜絕緣層2 h亦下沈，配線部2 b之連接面 2 e與絕緣層2 c間之段差更大，如圖5 ( b )所示之圖 型領域2 j可確實將圖4之金突起4定位。 因此，金突起4與配線部2 b間之位移可防止，記憶 卡2 0 (半導體裝置）之電氣特性提升及覆晶接合之連接 信賴性提升可實現。 又’金突起4與配線部2 b間之位移可防止，故而鄰 接配線部2 b間之短路亦可防止，結果記憶卡2 0之良率 可提升。 以下，依圖3之流程圖說明實施形態1之記億卡2 0 (半導體裝置）之製造方法。 首先，準備步驟s 1之半導體晶片1 p亦即，準備形 成有特定記憶體電路，且於主面1 a形成有多數電極1 b 之圖4之半導體晶片1。 其次，於步驟S 2準備晶片支持基板之卡片基板2。 亦即，準備具有對應半導體晶片1之電極1 b且可與其做 -- I ϋ ϋ ϋ I I I ^ n I J n I I n n n tr n. 1 (請先閲it背面之注t事項再填寫本頁) 本纸張又度適用中國國家標準（CNS)A4規格（210x297公t ) * 14 - 4 6 2 0 ^5 Λ„ Α( Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（12) 電連接之配線部2 b及形成於其周圍之絕緣層2 c，且配 線部2 b之設置面2 d起之高度較絕緣層2 c低之卡片基 板2。 亦即，如圖5 ( a ) 、（ b )所示，準備各配線部 2 b之高度低於其周圍形成之絕緣層2 c，且於連接面 2 e之略中央附近形成有凹部2 f之卡片基板2。 之後，於步驟S3形成金突起4，於半導體晶片1之 各電極1 b設突起電極之金突起4。 實施形態1之金突起4，係藉標準接合技術於半導體 晶片1之電極1 b上接合形成之導線突起，但亦可藉標準 技術以外之電鍍技術等形成金突起4 » 之後，於步驟S4進行ACF 3之黏貼》 亦即，如圖6所示•於卡片基板2之晶片支持面2 k 配置異方性導電樹脂之ACF3。 實施形態1使用之ACF3，係薄膜狀。 又，依實裝之半導體晶片1之數及配置以1對1之對 應配置同數之ACF3 » 之後，於步驟S 5進行晶片搭載，亦即由A C F 3之 上方|使半導體晶片1之主面1 a與卡片基板2之晶片支 持面2k介由ACF3面對配置。 亦即，使各半導體晶片1之主面1 a與卡片基板2之 晶片支持面2 k面對，於4個AC F 3上將4個半導體晶 片1面朝下實裝。 之後，如圖7 (a) 、（： b)所示，由半導體晶片1 請 先 閱 讀 背 & 之 注 項 再 填 寫 本 頁 訂 線 本纸張尺度適用令國國家標準（CNS)A4規格（210 * 297公釐）-15- 6 2 0 9 5 A7 B7 經濟部智慧財產局負工消費合作社印製 五、發明說明（13) 之主面1 a之相反側之面之背面1 c側對半導體晶片1施 加荷重，將金突起4押入A C F 3內》 又’金突起4押入AC F 3內時’於卡片基板2施加 荷重亦可’或於半導體晶片1及卡片基板2兩者施加荷重 亦可。 又’繼續施加荷重，如圖7所示，藉金突起4突破 ACF3，使貫通ACF3。 之後，於半導體晶片1施加荷重，俾於卡片基板2之 絕緣層2 c及較其低之配線部2 b所形成之段差部之圖型 領域2j (參照圖5(b))，藉絕緣層2c導引金突起 4之同時，使金突起4押入圖型領域2j 。 此時，因荷重使薄膜絕緣層2 h下沈，配線部2 b亦 下沈，上述段差部之圖型領域2 j之深度便更深，故而金 突起4之於配線部2 b上之導引可確實進行。 依此可進行金突起4之定位。 又，將金突起4之前端附近配置（進入）於配線部 2b之連接面2e之凹部2f ，則如圖8 (a) 、 （b) 所示，配線部2 b與金突起4之定位可確實進行，結果， 於卡片基板2與半導體晶片1正確定位狀態下可連接配線 部2b與金突起4。 又，實施形態1中，對半導體晶片1繼續施加荷重， 介由半導體晶片1加熱A C F 3以進行覆晶接合。亦即， 於步驟S 6進行晶片熱壓接將半導體晶片1固定於卡片基 板2 。 本纸張瓦度適用中國國家標準（CNSM4規格（210 X 297公« ) -16- J---------!!·*」 κ ϋ ϋ n^ttJI art t 線 (請先閱讀背面之注意事項再填寫本頁) 462095 A7 B7 五、發明說明（14) (請先閱讀背面之江意事項再填寫本頁) 此時，由待加熱之半導體晶片1之背面1 c側起藉未 圖式之加壓塊（亦稱加熱塊）對半導體晶片1施加特定荷 重，以進行半導體晶片1之熱壓接。 又，藉上述加壓塊對半導體晶片1之背面1 c施加特 定荷重時，安裝於半導體晶片1之金突起4即壓潰 A C F 3之熱硬化性樹脂呈面朝卡片基板2之配線部2 b 之連接面2 e |之後於半導體晶片1之電極1 b與配線部 2b間挾持ACF3中之導電粒子3a，使金突起4接觸 配線部2 b之連接面2 e。 結果，半導體晶片1之金突起4與卡片基板2之配線 部2 b介由AC F 3中之導電粒子3 a做電連接。 又，藉上述施加特定荷重狀態之施加塊加熱半導體晶 片1 ，則A C F 3中之熱硬化性樹脂硬化，據此半導體晶 片1之電極1 b與卡片基板2之配線部2 b間之接續可由 硬化之ACF3保持。 結果，金突起4之於卡片基板2之配線部2 b之連接 面2 e之定位可確實進行以實現覆晶接合。 依此結束圖1之記憶卡2 0之組裝。 烴濟部智慧財產局員工消費合作社印製 依實施形態1之記億卡20(半導體裝置）之製造方 法，覆晶接合時，設於半導體晶片1之電極1 b上之金突 起4，與卡片基板2之配線部2 b間之位移可防止，因此 記憶卡2 0 (半導體裝置）之電氣特性提升及覆晶接合之 信賴性提升可實現。 又，金突起4與配線部2 b間之位移可防止|故而鄰 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐）-17· 經濟部智慧財產局員工消費合作社印製 620 9 5 A7 __B7____ _ 五、發明說明（15 ) 接配線部2 b間之短路亦可防止，記憶卡2 0之良率可提 升。 以下，依圖9之半導體裝置（FBGA ( Fine-pitch Ball Grid Array ))之構造，及圖10之FBGA之組裝圖 說明本發明實施形態2 = 圖9之實施形態2之半導體裝置之FBGA30，和 實施形態1之記憶卡2 0同樣'係由半導體晶片1以覆晶 接合組裝而成。 FBGA30，和實施形態1說明之圖2之晶片支持 基板之卡片基板2同樣，具備具圖2之配線部2 b及形成 於其周圍之絕緣層2 c的晶片支持基板之BGA基板5， 於該B GA基板5如圖9所示藉覆晶接合搭載有半導體晶 片1。 又，於FBGA30，於BGA基板5之晶片支持面 5 a之相反側之面設有多數焊錫突起6作爲外部端子。 於B G A基板5，和實施形態1同樣，形成有圖2所 示配線部2 b及絕緣層2 c，配線部2 b係較形成於其周 圍之絕緣層2 c高，於配線部2 b之連接面2 e形成有凹 部2 f。 在半導體晶片1之電極1b上安裝之金突起4與配線 部2b之連接處之周圍配置ACF3，藉ACF3保持金 突起4與配線部2b間之連接* 因此，覆晶接合時，於B GA基板5之晶片支持面 5a上配置ACF3，之後，介由ACF3進行熱壓接以 本纸張尺度適用中國國家標準（CNS〉A4規格（210 X 297公釐）-18- -----I-------i I II II I ^ — null! (請先閱讀背面之注項再填寫本I ) 462095 A7 B7 五、發明說明（16) 連接半導體晶片1及BGA基板5 » ί諝先閲讀背面之注意事項再填寫本頁) 又’覆晶接合時’和實施形態1同樣，半導體晶片1 之電極1 b上安裝之金突起4，係藉配線部2 b及絕緣層 2 c所形成段差部及凹部2 f被定位於配線部2 b之連接 面2 e。因此，和實施形態1之記億卡2 0同樣，半導體 晶片1與B GA基板5間之定位可確實進行。 結果，FBGA3 0可得焊錫突起實施形態1之記億 卡2 0同樣之效果。 以下，依圖9及圖1 0說明實施形態2之 FBGA30之製造方法。 F B GA 3 0之製造方法，基本上僅於圖3之步驟 S 1 —步驟S 6之工程加上F B GA 3 0之外部端子安裝 工程。 首先，如圖10(a)所示，準備在主面la形成有 多數電極lb之半導體晶片1，進行各電極lb之突起形 成。 此處，使用導線接合裝置對半導體晶片1之鋁之各電 極1 b，進行金線之導線突起（亦稱標準突起）之形成。 經濟部智慧財產局負工消費合作社印製 之後，如圖10(b)所示•於BGA基板5之晶片 支持面5a配置ACF3。 如圖1 0 ( c )所是由背面側1 c對半導體晶片1加 壓1使金突起4突破ACF3，據以使金突起4及配線部 2 b連接。 此時，和實施形態1之記億卡2 0同樣，如圖7所示 本紙張&度適用中國國家橾準（CNS)A4規格（210 * 297公釐）-19 - 經濟部智慧財產局員工消費合作社印製 20 9 5 A7 _______B7 五、發明說明（17 ) ’藉較配線部2 b高之絕緣層2 c將金突起4導引至配線 部2 b上，再藉連接面2 e之凹部2 f將金突起4定位於 連接面2 e。 依此，金突起4可正確定位於配線部2 b，結果，半 導體晶片1與B GA基板5間可確實定位。 又，加熱ACF 3使硬化，藉ACF 3保持金突起4 與配線部2 b間之連接。 之後，於圖10(d)之BGA基板5之晶片支持面 5 a之相反側之面，藉轉印法形成多數焊錫突起6作爲外 部端子。 依此即可組成圖9之實施形態2之FBGA30。 實施形態2之FBGA30 (半導體裝置）得到之效 果，係和實施形態1之記憶卡2 0同樣。 以上係依實施形態具體說明本發明•但本發明不限於 該實施形態，在不脫離其要旨下可做各種變更。 例如，實施形態1、2中，係於晶片支持基板之配線 部2b之連接面2e形成凹部2f ，但只需配線部2b之 連接面2 e形成較其周圍形成之絕緣層2 c爲低即可，凹 部2 f不形成於連接面2 e亦可。 亦即，只要配線部2 b形成較其周圍之絕緣層2 c低 ，配線部2 b之連接面2 e可爲大略平坦之面》 此情形下，於凹部2 f埋入導體材料，由後面硏磨連 接面2 e即可。 又，如圖11(a) 、 （b) 、 （c)之變形例之卡 本纸張又度適用中國國家標準（CNS)A4規格（210 X 297公釐）-20- — — — — — — — — — —— — — ^ i — — — — — — ^ ·1111111 (请先閱讀背面之注意事項再填寫本頁) A7 462095 B7_____ 五、發明說明（18 ) 片基板2所示（B GA基板5亦同樣），於配線部2 b之 連接面2 e形成凹部2 f，則於配線部2 b周圍不形成絕 緣層2 c亦可β 但是，於金突起4與配線部2 b之連接處周圍，須配 置ACF3，藉ACF3保持金突起4與配線部2b間之 連接。 又，依圖11之配線部2b之形狀，可得和圖5之卡 片基板2同樣之效果。 圖1 2之變形例之半導體裝置，係例如形成半導體機 體電路時之邏輯模擬器用模組製品之模擬器40，係於主 基板之模組基板7正反面實裝4個圖9之FBGA3 0。 亦即，實裝於圖1 2之模組基板7之FBGA3 0， 係具備具絕緣層2 c所包圍高度較低之配線部2 b的 BGA基板5，於該BGA基板5進行覆晶接合時，可以 實施形態2說明之同樣構造、方法進行組裝。 又，於模組基板7之正面側（背面側亦可），除 F B GA 3 0以外亦實裝有與外部裝置連接之連接器7 a 及多數晶片電容器7 b等元件。 又，圖1 3之半導體裝置（模組製品），係和圖1 2 之模組製品之模擬器4 0同樣之模擬器5 0，係將 F BGA 3 0僅實裝於模組基板7之單面之例。 圖12及圖13之半導體裝置（模擬器40、50等 之模組製品），可得和實施形態1同樣之效果。 又’圖14(a) 、 （b)之變形例之半導體裝置， 本纸張尺度適用中國國家標準（CMSM4規格（21〇χ 297公爱）-21 - n ϋ n ·1 ϋ H ϋ I * n n n ii.^-BJI n I n n n I n I (請先M讀背面之注意事項再填寫本頁) 經濟部智慧时產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 462095 A7 B7 五、發明說明（19) 係多晶片模組6 0，係藉和實施形態1同樣之覆晶接合在 模組基板8之單面（晶片支持面8 a )實裝多數之不同大 小之半導體晶片1之同時，於同一面藉回流等實裝晶片電 容器7 b或晶片電阻等小型電子元件。 於晶片支持面8 a之相反側之面搭載有多數焊錫突起 6作爲外部端子。 又，圖14之多晶片模組60，係將CPU ( Central Processing Unit )、記憶體、類比/數位混載、A N D、 NAND、E〇R、OR緩衝器等半導體晶片1混載者， 同時將晶片電容器7 b等小型電子元件及焊錫突起6兩者 分開配置者。 依此，進行覆晶接合時，多數半導體晶片1可以一次 進行壓接處理，覆晶接合之作業性可提升。 又|圖1 5、1 6係將半導體晶片1實裝於實裝基板 _ 9 (晶片支持基板）時之定位相關變形例，如圖1 5 ( a )、（b)所示，於半導體晶片1之電極lb對應地設置 突起用溝3 b，使用該突起用溝3 b進行覆晶接合時之半 導體晶片1之定位。 亦即，準備圖16 (a)之半導體晶片1、設有圖 16 (b)之突起用溝3b的ACF3，及設有圖16 ( c)之第1辨識電極9 a、第2辨識電極9 b、第1目標 標誌9c及第2目標標誌9d的實裝基板9，將ACF3 搭載於實裝基板9之前分別辨識各個位置（座標）之同時 ，分別導出目標標誌與辨識電極間之位置關係。 本紙張尺度適用中囤囷家標準<CNS)A4規格（210x 297公釐）-22- I n n n I I 0 n |> ί ϋ I— n Βΐ n I n tl . <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 462095 五、發明說明（20) 之後，如圖16 (d)所示’辨識突起用溝3b ’判 斷其與第1目標標誌9 c及第2目標標誌9 d間之位置關 係並將A C F 3實裝於實裝基板9。 依此則可將特定之突起用溝3 b定位於實裝基板9之 第1辨識電極9 a及第2辨識電極9 b上’將A C F 3搭 載於實裝基板9。 之後，於ACF3之突起用溝3b ’如圖15 (a) 、（b)所示，使半導體晶片1之金突起4陷入’即可介 由ACF 3確實進行半導體晶片1與實裝基板9間之定位 〇 又，圖1 7之其他實施形態，係將BGA型，且外部 端子爲焊錫突起6之半導體封裝10實裝於配線基板11 之定位方法。準備設有實施形態1說明之配線部2 b及絕 緣層2c的配線基板11·於該配線基板11藉焊錫回流 實裝半導體封裝10時，於配線部2b之凹部2 f (參照 圖2 )及配線部2 b周圍藉形成較其爲高之絕緣層2 c來 定位焊錫突起6。 亦即，半導體晶片1被組裝之同時，具備作爲外部端 子之多數焊錫突起6的BGA型半導體封裝1〇;及支持 該半導體封裝1 0之同時，具備與半導體封裝1 0之焊錫 突起6電連接之配線部2 t)及形成於其周圍之絕緣層2 c ，而且於配線部2 b之連接面2 e形成有上述凹部2 f的 配線基板1 1者；藉配線部2 b之上述凹部2 f及絕緣層 2 c將半導體封裝1 0之焊錫突起6定爲於配線部2 b之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）-23 - ϋ ϋ I n I'*l · 1 n ϋ ·1 一s， 1« a— I Kfk n I 線 {請先Mtt背面之注意事項再填寫本頁) ^62095 Α7 Β7 五、發明說明（21) 連接面2 e者。 (請先閱讀背面之注意事項再填寫本頁) 依此則突起電極不限於圖2之金突起4，即使是焊錫 突起6於回流實裝時亦可進行焊錫突起6之定位。 產業上之可利用性 如上述，本發明之半導體裝置及其製造方法，極適用 於覆晶接合方式，適用於B GA封裝貨記憶卡中之覆晶接 合’特別是更適用於模擬器或晶片元件混載之多晶片模組 等。 (圖面之簡單說明） 圖1(a):本發明實施形態1之半導體裝置之一例 之記憶卡構造之平面圖。 圖1(b):本發明實施形態1之半導體裝置之一例 之記億卡構造之側面圖。 圖2:圖1之半導體裝置之覆晶接合部構造之部分擴 大斷面圖。 經濟部智慧財產局員工消費合作社印製 圖3:圖1之半導體裝置之組裝順序之一例之製成流 程圖。 圖4:圖1之半導體裝匱組裝工程中之半導體晶片構 造之斷面圖。 圖5:圖1之半導體裝置組裝工程中之晶片支持基板 構造圖，（a)爲部分斷面圖，（b)爲配線部之擴大部 分斷面圖。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公Μ ) -24- 烴濟部智慧財產局員工消費合作社印製 d 620 9 5 __B7_ 五、發明說明（22) 圖6:圖1之半導體裝置組裝工程中異方性導電樹脂 黏貼時之構造部分斷面圖。 圖7:圖1之半導體裝匱組裝工程中晶片搭載時之構 造圖，（a )爲部分斷面圖，（b )爲金突起及配線部之 擴大部分斷面圖。 圖8:圖1之半導體裝置組裝工程中晶片熱壓接十隻 構造圖，（a)爲部分斷面圖，（b)爲連接部之擴大部 分斷面圖。 圖9:本發明實施形態2之半導體裝置之一例之 FBGA之構造圖，（a)爲外觀斜視圖，（b)爲斷面 圖。 圖10(a) 、 （b) 、 （c) 、 （d):對應圖9 之F B GA之組裝工程之構造之一例之斷面圖。 圖11:實施形態1之半導體裝置使用之晶片支持基 板之變形例之基板構造圖，（a)爲部分斷面圖，（b) 爲配線部之擴大部分斷面圖，（c)爲晶片熱壓接後之部 分斷面圖。 圖12:本發明另一實施形態之半導體裝置之模組製 品構造圖，（a)爲平面圖，（b)爲（a)之A — A線 斷面圖。 圖13:圖12之模組製品之變形例構造斷面圖》4 6 20 9 5 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the Invention (1) (Technical Field) The present invention relates to semiconductor manufacturing technology, and particularly to an effective technology applicable to flip-chip bonding using gold protrusions. (Background Art) According to the inventor's review results, in semiconductor devices (such as MCM (Multi-Chip-Module)) equipped with most semiconductor wafers, in order to increase the density of semiconductor wafers, the semiconductor wafer surface is often used. A flip-chip bonding method for mounting on a wafer support substrate face down. In this flip-chip bonding, an anisotropic conductive resin (anisotropic conductive film, an anisotropic conductive sheet, an anisotropic conductive film, an anisotropic conductive paste) is used for the electrical connection between the semiconductor wafer and the mounted wafer support substrate. Or ACF (Anisotropic Conductive Film). The flip-chip bonding using anisotropic conductive resin is based on the formation of gold bumps on the surface electrode of the semiconductor wafer. Then, the anisotropic conductive resin is pasted on the wafer support substrate. (2) The protruding electrode and the corresponding wiring support part of the wafer support substrate are faced with an anisotropic conductive resin thereon, and then thermocompression bonding is performed so that the semiconductor wafer and the wafer support substrate are electrically charged through the anisotropic conductive resin. The wafer support substrate is formed by a semi-additive method that can form the wiring portion at a fine pitch, so the cross-sectional shape of the wiring portion is convex (trapezoidal), and the inclined surface β is formed at the corner. Therefore, the connection surface at the upper portion of the wiring The width is less than the width of the bottom. The pair of wiring margins of the gold protrusions mounted on the semiconductor wafer becomes smaller. This is a problem. National Standard (CNS) A4 Specification (210 * 297 Gong > -4- -------— 1C --- I ^ 1111111 ίιιιί — — — (Please read the precautions on the back before filling this page) 462095 ^ Α7 Β7 V. Description of the invention (2) 〇 (Please read the precautions on the back before filling this page) Also, when a protruding electrode is arranged near the end of the connection surface of the wiring part, when the semiconductor wafer is pressed, the protruding electrode It may slip off from the end of the connection surface of the wiring portion, resulting in displacement between the protruding electrode and the wiring portion, causing problems such as a reduction in electrical characteristic margin or short-circuiting with adjacent wiring. Also, problems such as a decrease in the yield of the semiconductor device The flip chip bonding with protrusions is disclosed in, for example, Japanese Patent Application Laid-Open No. 6 2 -49636, Japanese Patent Application Laid-Open No. 10-107077, and Japanese Patent Application Laid-Open No. 5- 1 2 9 3 70. It is disclosed in the wiring section. (Contains flat parts.) The technology of forming recesses, through-grooves, or through-holes on the connection surface and positioning protrusions on the connection surface of the wiring portion. However, when flip-chip bonding is used, the semiconductor wafer is subjected to a specific method during thermal compression bonding Heavy It is unreliable for positioning only by the grooves or through-grooves or through-holes formed in the wiring section. When solder bumps are used for protrusions, short circuits between adjacent wiring sections due to solder flow become a problem. Economic and intellectual property bureau staff consumption The objective of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the reduction in electrical characteristics caused by displacement between a protruding electrode and a wiring portion of a wafer supporting substrate during chip-on-chip bonding and improve the reliability of chip-on-chip bonding. Another object of the present invention is to provide a semiconductor device and a manufacturing method of the semiconductor device that can improve the yield of flip-chip bonding. The purpose and features of the present invention will be described below with reference to the drawings. This paper size applies the China National Standard (CNS) A4 specification (210 X 297 mm> -5- 4 6 20 95 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _B7 V. Description of the invention (3) (Disclosure of the invention The semiconductor device of the present invention includes: the semiconductor wafer having a plurality of exposed surface electrodes formed on a main surface; a wiring portion for supporting the semiconductor wafer; and a wiring portion for electrically connecting the surface electrodes of the semiconductor wafer. Wafer support substrate having a recess formed on the connection surface: The recess of the wiring portion is positioned to connect the surface electrode between the surface electrode of the semiconductor wafer and the connection surface of the wiring portion of the wafer support substrate. A protruding electrode connected to the wiring portion; and an anisotropic conductive resin arranged around the connection between the protruding electrode and the wiring portion to maintain the connection between the protruding electrode and the wiring portion; the protruding electrode is connected through the wiring The recessed portion is positioned on the connection surface of the wiring portion. The semiconductor device of the present invention, The semiconductor wafer having a plurality of exposed surface electrodes formed on a main surface thereof: a supporting portion for supporting the semiconductor wafer, a wiring portion for electrically connecting the surface electrodes of the semiconductor wafer, and an insulating layer formed around the wiring portion; The height from the installation surface forms a wafer support substrate lower than the above-mentioned insulating layer; the connection surface connecting the wiring portion lower than the above-mentioned insulating layer is interposed between the surface electrode of the semiconductor wafer and the wiring portion of the wafer support substrate. A protruding electrode for connecting the surface electrode and the wiring part between the connection surfaces: and an anisotropic conductive resin arranged around the connection between the protruding electrode and the wiring part and used to maintain the connection between the protruding electrode and the wiring part The above-mentioned protruding electrode is positioned on the above-mentioned connection surface of the above-mentioned wiring section by the above-mentioned insulation layer. < CNS) A4 size (210 x 297 mm) -6- nf tt I nf— I · 1 ^ -eJI II (锖 Please read the notes on the back before filling this page) 4 620 9 5 A7 _____ B7 V. Description of the invention (4) < Please read the precautions on the back before filling in this page.) Also, the semiconductor device of the present invention includes: the above-mentioned semiconductor wafer having a plurality of exposed surface electrodes formed on the main surface; and used to support the above-mentioned semiconductor wafer. A wafer in which the wiring portion of the surface electrode of the semiconductor wafer and the insulating layer formed around the wiring portion have a height lower than the insulating layer from the installation surface of the wiring portion, and a wafer having a recessed portion formed on a connection surface of the wiring portion. Support substrate; the recessed portion of the wiring portion lower than the insulating layer is positioned between the surface electrode of the semiconductor wafer and the connection surface of the wiring portion of the wafer support substrate for connecting the surface electrode and the A protruding electrode in the wiring portion; and an anisotropic conductive resin arranged around the connection between the protruding electrode and the wiring portion to maintain the connection between the protruding electrode and the wiring portion: the protruding electrode passes through the wiring portion The recessed portion and the insulating layer are positioned on the connection surface of the wiring portion. In this case, when the semiconductor wafer is crimped during flip chip bonding, the protruding electrodes mounted on the semiconductor wafer are guided and arranged on the connection surface of the wiring portion through an insulating layer higher than the wiring portion. Moreover, the connection is inserted near the front end of the protruding electrode. The surface recessed portion, therefore, the protruding electrode can be surely positioned on the connection surface by the insulating layer and the recessed portion of the connection surface. As a result of printing by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, it is possible to prevent displacement between the protruding electrode and the wiring portion, and realize the electrical characteristic improvement of the semiconductor device and the bonding reliability of the flip-chip bonding. The method for manufacturing a semiconductor device according to the present invention includes a process of preparing a semiconductor wafer having a plurality of surface electrodes formed on a main surface thereof: preparing a wiring portion including a surface electrode capable of electrically connecting the semiconductor wafer and providing the wiring portion in the wiring portion. Engineering of wafer support substrate with recess formed on the connection surface This paper is applicable to the national standard + national standard (£ ^ 5) 6 4 specifications (210 * 297 mm) 4 6 2 0 9 ί7 Α7 Β7 V. Description of the invention (5 ) (Please read the precautions on the back before filling in this page>: Project of providing protruding electrodes on the surface electrode of the semiconductor wafer; Project of placing anisotropic conductive resin on the wafer support surface of the wafer support substrate: The process of disposing the main surface of the semiconductor wafer and the wafer support surface of the wafer support substrate through the anisotropic conductive resin facing: either or both of the semiconductor wafer or the wafer support substrate are pressurized to make the above The project of the protruding electrode breaking through the anisotropic conductive resin: positioning the protruding electrode by the recessed portion of the wiring portion to locate the above A process for supporting a wafer and a semiconductor wafer and connecting the wiring portion and the protruding electrode: and curing the anisotropic conductive resin, and maintaining the connection between the protruding electrode and the wiring portion by the anisotropic conductive resin to make the semiconductor Wafer flip chip bonding to the above wafer support substrate. The employee of the Intellectual Property Bureau of the Ministry of Economic Affairs, Cooperative Association Print * Jff, and the method for manufacturing a semiconductor device of the present invention includes preparing a semiconductor wafer having a plurality of surface electrodes formed on a main surface. The project of preparing a wafer support substrate having a wiring portion that can electrically connect the surface electrodes of the semiconductor wafer and an insulating layer formed around the wiring portion, and the height from the installation surface of the wiring portion is lower than the insulating layer; A process of providing a protruding electrode on the surface electrode of the semiconductor wafer; a process of disposing an anisotropic conductive resin on a wafer support surface of the wafer support substrate provided with the wiring portion: supporting the main surface of the semiconductor wafer and the wafer support The wafer supporting surface of the substrate via the protruding electrode And anisotropic conductive resin facing configuration process; pressing one or both of the above semiconductor wafer or wafer supporting substrate to make the protruding electrode break through the above anisotropic conductive resin: on the above-mentioned insulating layer. The lower step formed by the above-mentioned wiring section guides and locates the protruding electrodes by the above-mentioned insulating layer, and the positioning of the above-mentioned crystalline paper is again applicable to the Chinese National Standard (CNS) A4 specification (210 * 297 mm) -8 -462095 A7 B7 V. Description of the invention (6) (Please read the precautions on the back before filling this page) The process of supporting the substrate and the semiconductor wafer and connecting the wiring portion and the protruding electrode; and making the anisotropy conductive Resin hardening * The process of maintaining the connection between the protruding electrode and the wiring portion by the anisotropic conductive resin to bond the semiconductor wafer to the wafer support substrate. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and a method for manufacturing a semiconductor device of the present invention includes: preparing a semiconductor wafer having a plurality of surface electrodes formed on a main surface; A process for forming a wiring supporting portion of an electrode and a wafer supporting substrate having a recessed portion formed on a connecting surface of the wiring portion and an insulation layer formed around the wiring portion at a height lower than the insulating layer; The process of providing the protruding electrodes on the surface electrodes of the semiconductor wafer: the process of disposing an anisotropic conductive resin on the wafer supporting surface of the wafer supporting substrate on which the wiring portion is provided; the main surface of the semiconductor wafer and the wafer supporting substrate A process in which the wafer supporting surface is disposed to face through the protruding electrode and the anisotropic conductive resin; pressing one or both of the semiconductor wafer or the wafer supporting substrate so that the protruding electrode breaks through the anisotropic conductive resin Engineering; in the above-mentioned insulation layer and above-mentioned wiring department After the formed step portion is guided and positioned by the insulating layer, the protruding electrode is positioned by the recessed portion of the wiring portion, thereby positioning the wafer supporting substrate and the semiconductor wafer and connecting the wiring portion and the protruding electrode. And a process of hardening the anisotropic conductive resin, and maintaining the connection between the protruding electrode and the wiring portion by the anisotropic conductive resin, so that the semiconductor wafer is flip-chip bonded to the wafer support substrate. This paper size applies to China National Standard (CNS) A4 (210x297 cm) -9- 4620 9 5 A7 B7 V. Description of the invention (7) (Implementation mode of the invention) (Please read the unintentional matter on the back before filling This page "hereinafter, descriptions of the same or similar parts other than necessary in the embodiments are omitted and repeated descriptions are provided. The descriptions in the following embodiments are convenient and divided into a plurality of parts or descriptions of the embodiments when necessary, but unless otherwise specified, Etc. are not unrelated, but one has a relationship with some or all of the other's modified examples, detailed supplementary explanations, etc. In the following embodiment, the number of elements (including the number, number, amount, range, etc.) is mentioned. ), Except that the specific number is explicitly stated and clearly limited in principle, the specific number is not limited, but may be more than the specific number. "The following describes the embodiments of the present invention with reference to the drawings. Components with the same function are assigned the same reference numerals and repeated descriptions are omitted. Embodiment 1 of the present invention is a structural diagram of a semiconductor device (remembered billion cards) shown in FIG. 1, and FIG. 2 is a Figure of flip-chip junction, Figures 3-8 are diagrams of the manufacturing method of semiconductor devices. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * ' < The semiconductor device according to the first embodiment of the present invention shown in FIG. 1 is a semiconductor card in which four memory chips are mounted on a thin card substrate 2 (wafer support substrate) by a flip-chip bonding method to form a memory card 20. In other words, remembering 200 million cards, it is the use of anisotropic conductive resin (ACF, Anisotropic Conductive Film; also known as anisotropic conductive adhesive tape, anisotropic conductive sheet, or anisotropic conductive film, etc.) 1 flip chip is a card product formed by joining a thin card substrate 2. Memory card 20, as shown in Figure 4, is formed by: half of the paper formed on the main surface 1 a. The inverse is applicable to the Chinese national standard (CNSM4 specification (210 X 297 mm)). Printed by a consumer cooperative 20 9 5 A7 ___B7___ 5. Description of the invention (8) A semiconductor wafer 1 that conducts a bulk circuit and is exposed on the main surface 1 a while forming a majority of electrodes lb (surface electrodes) made of aluminum; and supporting semiconductors The wiring portion 2b shown in FIG. 2 and the insulating layer 2c formed around the wafer 1 and having the electrodes 1b electrically connected to the semiconductor wafer 1 are lower than the insulating layer 2c in height from the installation surface 2d. At the same time, a card substrate 2 having a recessed portion 2 is formed on the connection surface 2 e of the wiring portion 2 b; and a recessed portion 2 f of the wiring portion 2 b lower than the insulating layer 2 c is positioned between the electrodes 1 b of the semiconductor wafer 1 The gold projection 4 (projection electrode) for connecting the electrode lb and the wiring portion 2 b to the connection surface 2 e with the wiring portion 2 b of the card substrate 2; and is arranged around the connection portion of the gold projection 4 and the wiring portion 2 b · And keeps the ACF3 composed of the gold protrusion 4 and the wiring portion 2b connected; during the flip-chip bonding, the gold protrusion 4 The connection portion 2 f and the insulating layer 2 c of the wiring surface 2 b of FIG. 2 are positioned and connected to the connection surface 2 e of the green insulation layer 2 c. That is, the memory card 20 of FIG. On the card substrate 2, four semiconductor wafers 1 which are electrically connected through ACF 3 are respectively bonded in a bare chip state. The gold bumps 4 of the bump electrodes in FIG. 2 are obtained by standard bonding techniques (by wire bonding devices). The technique of forming a protruding electrode on the electrode 1b of the semiconductor wafer 1 by using gold wire) bonding the formed electrode 1a on the semiconductor wafer 1 is also called a wire protrusion (however, the above-mentioned protruding electrode is not a protrusion formed by standard bonding technology, Alternatively, it can be formed by electroplating or the like. In addition, in each wiring portion 2 b of the card substrate 2 of Embodiment 1, a recessed portion 2 f in FIG. 2 is formed on a connection surface 2 e with the gold protrusion 4. Degree applies to Chinese National Standard (CNS > A4 specification (210 * 297 cm)-11--ϋ ί— n-n--l ^ i .. I u · I n ϋ-#-r »J« a— n ϋ k— n >. (Please read the notes on the back before filling in this page ”4 620 9 5 A7 _B7 V. Description of Invention (9) (Please read first Read the description on the back and fill in this page again.) An insulating layer 2 c higher than the wiring section 2 b is formed around the wire section 2 b (indicating that the insulating layer 2 c is provided from the installation surface 2 d of the wiring section 2 b. The height is greater than the height of the wiring portion 2 b, and the height relationship between the wiring portion 2 b and the insulation layer 2 c refers to the distance from the installation surface 2 d. Formed from epoxy resin. Therefore, as shown in FIG. 5, the card substrate 2 of the memory card 20 of the first embodiment is provided with a wiring portion 2 b arranged corresponding to each electrode 1 b of the semiconductor wafer 1 and a high insulating layer 2 c is formed around the wiring portion 2 c. In addition, the height relationship between the installation surface 2 d between the wiring portion 2 b and the insulating layer 2 c is shown in FIG. 5, and the height of the connection portion 2 e of the wiring portion 2 b is L, and the insulation layer 2 When the height of c is M and the bottom of the recessed part 2 f of the wiring part 2 b is N, there is L < M'N < L, and N < M's relationship. Hereinafter, a method of forming the wiring portion 2 b of the card substrate 2 will be described. The wiring portion 2 b is formed using a full-addition method. That is, as shown in FIG. 5, a thin film insulating layer with a high layer is formed on the surface of the core substrate 2 a for 2 h, and an insulating layer 2 c with a plating resist film is formed on the upper layer. 〇 After the employee's consumer cooperative seal of the Intellectual Property Bureau of the Ministry of Economic Affairs has been found, a specific pattern (corresponding to the pattern of the wiring section 2 b) is exposed on the insulation layer 2 c, and the above pattern is etched to form the location shown in FIG. 5 (b). Illustrative field 2 j. In the pattern area 2j, the wiring portion 2b is plated (grown). At this time, in the pattern area 2 j formed by etching, the above-mentioned plating layer grows from the inner wall 2 i of the insulating layer 2 c, so the connection surface with the wiring portion 2 b is in accordance with Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) -12- A7 4 620 9 5 __B7_______ V. Description of the invention (1 (5) 2 e near the center is higher than the inner wall 2 i, so the connection surface 2 b of the wiring part 2 e A recess 2 f is formed near the center. The wafer support substrate is formed by a full-addition method, so a fine pattern can be formed. As shown in Embodiment 1, a card substrate 2 for a memory card can be formed as a wafer support substrate. As shown in (b) As shown, a recessed portion 2 f is formed near the center of the connection surface 2 e of the wiring portion 2 b, so that the surrounding insulating layer 2 c can be manufactured as a card substrate 2 of a wafer supporting substrate higher than the wiring portion 2 b. Moreover, the wiring portion 2 b is composed of a nickel layer or a copper layer, and a gold layer is formed on the uppermost connection surface 2 e of the wiring portion 2 b. As shown in FIG. 6, ACF 3 is made of, for example, a thermosetting resin and nickel particles contained therein. It is composed of conductive particles 3 a. The conductive particles 3 a are held on the electrode 1 b of the semiconductor wafer 1. The gold protrusion 4 and the wiring portion 2 b of the card substrate 2 are used for the electrical connection between the two. However, the gold protrusion 4 and the wiring portion 2 b are not directly contacted through the conductive particles 3 a by the above thermosetting resin or other bonding. It is also possible to maintain the contact state between the two materials. In addition, the ACF 3 has a characteristic that the resin is pushed back when pressurized, and most of the conductive particles 3 a are gathered there. Therefore, the gold protrusions 4 and the conductive particles 3 a can be electrically connected through the conductive particles 3 a. Wiring section 2 b. On the memory card 20 of the first embodiment, as shown in FIG. 1, a plurality of connection terminals 2 g (external terminals) are provided in parallel at the end of the surface of the card substrate 2 for electrical connection with external devices. In addition, according to the memory card 2 0 of Embodiment 1 according to FIG. 1 · When the semiconductor wafer 1 is crimped at the time of flip-chip bonding, the wattage of the paper 1 on the electrode 1 b of the semiconductor wafer 1 is subject to the Chinese National Standard (CNS) A4. Specifications (210 * 297 public love) -13- I------ ---— I — C * — — — 1 —-I ^ · IIIIII-i (Please read the precautions on the back before filling this page ) Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 20 9 5 A7 _____B7__ V. Description of the invention (11) Gold bumps 4 'for mounting the protruding electrodes 4' Guided by forming an insulating layer 2 c higher than the wiring portion 2 b, arranged on the connection surface 2 b of the wiring portion 2 b That is, the insulating layer 2 c is used as a guide to guide the gold protrusion 4 to the connection surface 2 el of the wiring portion 2 b. Also, the recess 2 f of the connection surface 2 e is inserted near the front end of the gold protrusion 4 and therefore the insulation layer is used. 2 c and the recess 2 f of the connection surface 2 e can securely locate the gold protrusion 4 on the connection surface 2 e. When the semiconductor wafer 1 is pressed, the thin film insulation layer 2 h on the core substrate 2 a also sinks due to the pressing of the gold protrusion 4, and the step between the connection surface 2 e of the wiring portion 2 b and the insulation layer 2 c is larger, such as The pattern area 2 j shown in FIG. 5 (b) can surely locate the gold protrusion 4 of FIG. 4. Therefore, the displacement between the gold protrusion 4 and the wiring portion 2 b can be prevented, and the electrical characteristics of the memory card 20 (semiconductor device) can be improved and the reliability of the connection of the flip chip bonding can be improved. Since the displacement between the gold protrusion 4 and the wiring portion 2 b can be prevented, a short circuit between the adjacent wiring portion 2 b can also be prevented, and as a result, the yield of the memory card 20 can be improved. Hereinafter, a method for manufacturing a memory card 20 (semiconductor device) according to the first embodiment will be described with reference to a flowchart of FIG. 3. First, the semiconductor wafer 1 p of step s 1 is prepared, that is, the semiconductor wafer 1 of FIG. 4 having a specific memory circuit formed thereon and having a plurality of electrodes 1 b formed on the main surface 1 a. Next, the card substrate 2 of the wafer supporting substrate is prepared in step S2. That is, prepare the electrode 1 b corresponding to the semiconductor wafer 1 and can do it-I ϋ ϋ ϋ III ^ n IJ n II nnn tr n. 1 (please read the note t on the back of it before filling this page) The paper is again applicable to the Chinese National Standard (CNS) A4 specification (210x297 g) * 14-4 6 2 0 ^ 5 Λ „Α (Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (12) Electricity The connected wiring portion 2 b and the insulating layer 2 c formed around it, and the card substrate 2 having a height from the installation surface 2 d of the wiring portion 2 b lower than the insulating layer 2 c. That is, as shown in FIG. 5 (a) As shown in (b), a card substrate 2 having a height lower than that of the insulating layer 2c formed around each wiring portion 2b and having a recess 2f formed near the center of the connection surface 2e is prepared. Then, in step S3 forms gold bumps 4, and gold bumps 4 of bump electrodes are provided on each electrode 1b of semiconductor wafer 1. The gold bumps 4 of Embodiment 1 are wire bumps formed by bonding to electrode 1b of semiconductor wafer 1 by standard bonding techniques. However, it is also possible to form gold protrusions 4 by electroplating techniques other than the standard technique, and then perform AC in step S4. "F 3 Adhesion" That is, as shown in Fig. 6 • ACF3 with anisotropic conductive resin is arranged on the wafer support surface 2k of the card substrate 2. The ACF3 used in Embodiment 1 is a film. Also, according to the actual installation The number and configuration of the semiconductor wafers 1 are ACF3 corresponding to the same number in a one-to-one correspondence. After that, the wafer is mounted at step S5, that is, above the ACF 3 | Make the main surface 1a of the semiconductor wafer 1 and the card substrate 2 The wafer support surface 2k is arranged through the ACF3. That is, the main surface 1a of each semiconductor wafer 1 and the wafer support surface 2k of the card substrate 2 face each other, and four semiconductor wafers are placed on four AC F3s. 1 face down. After that, as shown in Figures 7 (a) and (: b), read the note on the back & Standard (CNS) A4 specification (210 * 297 mm) -15- 6 2 0 9 5 A7 B7 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The main face of the invention description (13) 1 a The back surface 1 c side applies a load to the semiconductor wafer 1, and pushes the gold protrusion 4 into the ACF 3. In AC F 3, it is also possible to apply a load to the card substrate 2 or to apply a load to both the semiconductor wafer 1 and the card substrate 2. Also, continue to apply the load, as shown in FIG. 7, the gold protrusion 4 breaks through the ACF 3, ACF3 is penetrated. Then, a load is applied to the semiconductor wafer 1, and a pattern area 2j formed by a stepped portion formed by the insulating layer 2c of the card substrate 2 and the lower wiring portion 2b is formed (see FIG. 5 (b)). When the gold protrusion 4 is guided by the insulating layer 2c, the gold protrusion 4 is pushed into the pattern area 2j. At this time, due to the load, the thin film insulating layer sinks for 2 h, and the wiring section 2 b also sinks. The depth of the pattern area 2 j of the stepped portion is deeper, so the guide of the gold protrusion 4 on the wiring section 2 b It can be done. According to this, the positioning of the gold protrusion 4 can be performed. In addition, the recess 2f of the gold projection 4 near the front end is disposed (entered) on the connection surface 2e of the wiring portion 2b. As shown in FIGS. 8 (a) and 8 (b), the positioning of the wiring portion 2b and the gold projection 4 can be positioned. Assuredly, as a result, the wiring portion 2b and the gold protrusion 4 can be connected in a state where the card substrate 2 and the semiconductor wafer 1 are correctly positioned. In Embodiment 1, a load is continuously applied to the semiconductor wafer 1, and A C F 3 is heated through the semiconductor wafer 1 to perform flip-chip bonding. That is, in step S6, wafer thermal compression bonding is performed to fix the semiconductor wafer 1 to the card substrate 2. The paper's wattage conforms to the Chinese national standard (CNSM4 specification (210 X 297 male «) -16- J --------- !! · *" κ ϋ ϋ n ^ ttJI art t line (please read first Note on the back page, please fill in this page again) 462095 A7 B7 V. Description of the invention (14) (Please read the page on the back page before filling out this page) At this time, borrow from the back side 1 c side of the semiconductor wafer 1 to be heated An unillustrated pressure block (also called a heating block) applies a specific load to the semiconductor wafer 1 to perform thermal compression bonding of the semiconductor wafer 1. When a specific load is applied to the back surface 1 c of the semiconductor wafer 1 by the pressure block described above The gold protrusion 4 mounted on the semiconductor wafer 1, that is, the thermosetting resin crushing the ACF 3, faces the connection surface 2 e of the wiring portion 2 b of the card substrate 2, and then the electrode 1 b and the wiring portion 2 b of the semiconductor wafer 1 The conductive particles 3a in the ACF3 are held between the gold protrusions 4 and the connection surface 2e of the wiring portion 2b. As a result, the gold protrusions 4 of the semiconductor wafer 1 and the wiring portion 2b of the card substrate 2 are electrically conductive through AC F3. The particles 3a are electrically connected. Furthermore, the semiconductor wafer 1 is heated by the application block applying a specific load state as described above. The thermosetting resin in ACF 3 is hardened, and thus the connection between the electrode 1 b of the semiconductor wafer 1 and the wiring portion 2 b of the card substrate 2 can be maintained by the hardened ACF 3. As a result, the gold protrusion 4 is on the wiring portion of the card substrate 2. The positioning of the connection surface 2 b of 2 b can be surely performed to achieve the flip-chip bonding. This completes the assembly of the memory card 20 of FIG. 1. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Hydrocarbons prints a billion card according to Embodiment 1. In the manufacturing method of 20 (semiconductor device), during the flip-chip bonding, the displacement of the gold protrusion 4 provided on the electrode 1 b of the semiconductor wafer 1 and the wiring portion 2 b of the card substrate 2 can be prevented, so the memory card 2 0 ( Semiconductor devices) can be improved in electrical characteristics and reliability of flip-chip bonding. Moreover, the displacement between the gold protrusion 4 and the wiring portion 2 b can be prevented | Therefore, the Chinese paper standard (CNS) A4 specification (210x297) is applied to the adjacent paper size (Mm) -17 · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 620 9 5 A7 __B7____ _ V. Description of the invention (15) The short circuit between the wiring unit 2 b can also be prevented, and the yield of the memory card 20 can be improved Following, according to Figure 9 The structure of a semiconductor device (FBGA (Fine-Pitch Ball Grid Array)) and the assembly diagram of the FBGA of FIG. 10 illustrate Embodiment 2 of the present invention = FBGA30 of the semiconductor device of Embodiment 2 of FIG. 9 and the memory card of Embodiment 1. 2 0 is similar to the semiconductor wafer 1 assembled by flip-chip bonding. FBGA30 is the same as the card substrate 2 of the wafer support substrate of FIG. 2 described in the first embodiment, and includes a wiring portion 2 b as shown in FIG. 2 and formed thereon. The surrounding insulating layer 2 c supports the BGA substrate 5 of the wafer. The semiconductor wafer 1 is mounted on the B GA substrate 5 by flip chip bonding as shown in FIG. 9. Further, in the FBGA 30, a plurality of solder bumps 6 are provided on the surface opposite to the wafer support surface 5a of the BGA substrate 5 as external terminals. The wiring part 2 b and the insulating layer 2 c shown in FIG. 2 are formed on the BGA substrate 5 in the same manner as in the first embodiment. The wiring part 2 b is higher than the insulating layer 2 c formed around the wiring part 2. The connection surface 2 e is formed with a recessed portion 2 f. ACF3 is arranged around the connection between the gold bump 4 mounted on the electrode 1b of the semiconductor wafer 1 and the wiring portion 2b. The ACF3 is used to maintain the connection between the gold bump 4 and the wiring portion 2b. ACF3 is arranged on the chip support surface 5a of 5 and then, it is thermocompression-bonded via ACF3 to apply the Chinese national standard (CNS> A4 specification (210 X 297 mm)) at this paper size-18- ----- I- ------ i I II II I ^ — null! (Please read the notes on the back before filling in this I) 462095 A7 B7 V. Description of the invention (16) Connecting the semiconductor wafer 1 and BGA substrate 5 »ί 谞 先(Please read the notes on the back and fill in this page again.) “When flip-chip bonding” is the same as in Embodiment 1. The gold bump 4 mounted on the electrode 1 b of the semiconductor wafer 1 is formed by the wiring portion 2 b and the insulating layer 2 c. The stepped portion and the recessed portion 2 f are positioned on the connection surface 2 e of the wiring portion 2 b. Therefore, similarly to the memory card 200 of the first embodiment, the positioning between the semiconductor wafer 1 and the B GA substrate 5 can be surely performed. As a result, FBGA3 0 can obtain the same effect as that of the solder bump 20 of the solder bump embodiment 1. Hereinafter, a manufacturing method of the FBGA30 according to the second embodiment will be described with reference to Figs. 9 and 10. The manufacturing method of F B GA 3 0 is basically only the step S 1-step S 6 in Fig. 3 plus the external terminal installation process of F B GA 3 0. First, as shown in Fig. 10 (a), a semiconductor wafer 1 having a plurality of electrodes 1b formed on a main surface 1a is prepared, and protrusions of each electrode 1b are formed. Here, each electrode 1b of aluminum of the semiconductor wafer 1 is formed with a wire bonding device to form a wire protrusion (also referred to as a standard protrusion) of gold wire. After printing by the Consumer Goods Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in Figure 10 (b) • ACF3 is configured on the wafer support surface 5a of the BGA substrate 5. As shown in Fig. 10 (c), the semiconductor wafer 1 is pressed 1 by the back side 1c to cause the gold protrusion 4 to break through the ACF3, thereby connecting the gold protrusion 4 and the wiring portion 2b. At this time, the paper & degree as shown in Fig. 7 is the same as that of the Billion Card 20 of Embodiment 1. As shown in Figure 7, this paper applies China National Standards (CNS) A4 (210 * 297 mm) -19-Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative 20 9 5 A7 _______B7 V. Description of the invention (17) 'By using an insulating layer 2 c higher than the wiring portion 2 b, guide the gold protrusion 4 to the wiring portion 2 b, and then borrow the connection surface 2 e The recess 2 f positions the gold protrusion 4 on the connection surface 2 e. Accordingly, the gold protrusion 4 can be accurately positioned on the wiring portion 2b. As a result, the semiconductor wafer 1 and the BGA substrate 5 can be accurately positioned. In addition, the ACF 3 is heated and hardened, and the connection between the gold protrusion 4 and the wiring portion 2 b is maintained by the ACF 3. Thereafter, a plurality of solder bumps 6 are formed as external terminals on the surface opposite to the wafer support surface 5a of the BGA substrate 5 in Fig. 10 (d) by a transfer method. According to this, the FBGA 30 of the second embodiment in FIG. 9 can be constituted. The effect obtained by the FBGA30 (semiconductor device) of the second embodiment is the same as that of the memory card 20 of the first embodiment. The present invention has been described in detail based on the embodiments. However, the present invention is not limited to this embodiment, and various changes can be made without departing from the gist thereof. For example, in Embodiments 1 and 2, the recessed portion 2f is formed on the connection surface 2e of the wiring portion 2b of the wafer supporting substrate, but it is only necessary that the connection surface 2e of the wiring portion 2b is formed to be lower than the insulating layer 2c formed around it. The recess 2 f may not be formed on the connection surface 2 e. That is, as long as the wiring portion 2 b is formed lower than the surrounding insulating layer 2 c, the connection surface 2 e of the wiring portion 2 b may be a substantially flat surface. In this case, the conductor material is buried in the recess portion 2 f and Honing the connection surface 2 e is sufficient. Also, as shown in Figures 11 (a), (b), and (c), the card paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -20- — — — — — — — — — — — — — ^ I — — — — — — — 1111111 (Please read the notes on the back before filling out this page) A7 462095 B7_____ V. Description of the invention (18) Sheet substrate 2 (B GA The same applies to the substrate 5). A recessed portion 2 f is formed on the connection surface 2 e of the wiring portion 2 b, and no insulating layer 2 c is formed around the wiring portion 2 b. However, the connection between the gold protrusion 4 and the wiring portion 2 b ACF3 must be arranged around the place, and the connection between the gold protrusion 4 and the wiring portion 2b is maintained by the ACF3. Further, according to the shape of the wiring portion 2b of Fig. 11, the same effect as that of the card substrate 2 of Fig. 5 can be obtained. The semiconductor device of the modification shown in FIG. 12 is, for example, a simulator 40 for a logic simulator module product when a semiconductor body circuit is formed, and four FBGAs 30 shown in FIG. 9 are mounted on the front and back of the module substrate 7 of the main substrate. That is, the FBGA3 0 mounted on the module substrate 7 of FIG. 12 is a BGA substrate 5 having a wiring portion 2 b with a low height surrounded by an insulating layer 2 c. When the BGA substrate 5 is flip-chip bonded It can be assembled in the same structure and method described in the second embodiment. In addition, on the front side (or the back side) of the module substrate 7, components such as a connector 7a and many chip capacitors 7b connected to external devices are actually mounted in addition to F B GA 30. The semiconductor device (module product) of FIG. 13 is the same as the simulator 50 of the module product of FIG. 12 and the simulator 50 is the F BGA 3 0 which is mounted on the module substrate 7 only. One-sided example. The semiconductor device (module products such as the simulators 40 and 50) of Figs. 12 and 13 can obtain the same effect as that of the first embodiment. Also, the semiconductor device of the modified example of FIGS. 14 (a) and (b) applies the Chinese paper standard (CMSM4 specification (21〇χ297297) -21-n -21 n · 1 ϋ H ϋ I * nnn ii. ^-BJI n I nnn I n I (Please read the precautions on the back before filling out this page) Printed by the Consumers 'Cooperatives of the Ministry of Economic Affairs and the Intellectual Property Bureau Printed by the Employees' Cooperatives of the Ministry of Economics and Intellectual Property Bureau 462095 A7 B7 V. Description of the invention (19) It is a multi-chip module 60, which is mounted on the single side of the module substrate 8 (wafer support surface 8a) by the same flip-chip bonding as in Embodiment 1. Most of the semiconductor wafers of different sizes are mounted. At the same time, small electronic components such as chip capacitors 7 b or chip resistors are mounted on the same side by reflow. A large number of solder bumps 6 are mounted on the opposite side of the wafer support surface 8 a as external terminals. The multi-chip module 60 is a semiconductor (chip) such as a CPU (Central Processing Unit), memory, analog / digital mixed load, AND, NAND, EOR, OR buffer, and small electronic components such as chip capacitors 7 b. Components and solder bumps 6 are arranged separately Based on this, when performing flip-chip bonding, most semiconductor wafers 1 can be crimped at one time, and the operability of flip-chip bonding can be improved. Also | Figures 1 and 16 are the semiconductor wafers 1 mounted on the mounting substrate_ 9 (wafer support substrate). As shown in Figs. 15 (a) and (b), a modification related to positioning is provided. A protrusion groove 3b is provided corresponding to the electrode lb of the semiconductor wafer 1, and the protrusion groove 3b is used. Positioning of the semiconductor wafer 1 at the time of flip-chip bonding. That is, the semiconductor wafer 1 of FIG. 16 (a) 1, ACF3 provided with the protrusion groove 3b of FIG. 16 (b), and the ACF3 provided with FIG. 16 (c) are prepared. The mounting substrate 9 of the first identification electrode 9 a, the second identification electrode 9 b, the first target mark 9 c, and the second target mark 9 d recognizes the positions (coordinates) of each of the positions (coordinates) before the ACF3 is mounted on the mounting substrate 9. The positional relationship between the target mark and the identification electrode is derived separately. < CNS) A4 specification (210x 297 mm) -22- I n n n I I 0 n | > ί ϋ I— n Βΐ n I n tl. < Please read the notes on the back before filling this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs Printed by 462095 V. Description of the invention (20), as shown in Figure 16 (d), 'Identify protrusion groove 3b' The ACF 3 is mounted on the mounting substrate 9 in a positional relationship with the first target mark 9 c and the second target mark 9 d. According to this, the specific protrusion groove 3 b can be positioned on the first identification electrode 9 a and the second identification electrode 9 b of the mounting substrate 9 ′, and A C F 3 can be mounted on the mounting substrate 9. After that, as shown in FIGS. 15 (a) and 15 (b), the gold groove 4 of the semiconductor wafer 1 is inserted into the groove 3b for the protrusion of the ACF3, and the semiconductor wafer 1 and the mounting substrate 9 can be surely interposed through the ACF 3. Positioning: In the other embodiment shown in FIG. 17, the positioning method is a method in which the semiconductor package 10 of the BGA type and the external terminals are solder bumps 6 is mounted on the wiring substrate 11. The wiring board 11 provided with the wiring portion 2 b and the insulating layer 2 c described in the first embodiment is prepared. When the semiconductor package 10 is mounted on the wiring board 11 by solder reflow, the recess 2 f of the wiring portion 2 b (see FIG. 2) and A solder bump 6 is positioned around the wiring portion 2 b by forming an insulating layer 2 c higher than the insulating layer 2 c. That is, while the semiconductor wafer 1 is being assembled, it is provided with a BGA-type semiconductor package 10 as a plurality of solder bumps 6 as external terminals; and while supporting the semiconductor package 10, it is provided with electrical connection to the solder bumps 6 of the semiconductor package 10 Wiring board 2 t) and an insulating layer 2 c formed around it, and a wiring board 11 having the above-mentioned recessed part 2 f formed on the connection surface 2 e of the wiring part 2 b; the above-mentioned recessed part 2 of the wiring part 2 b f and insulation layer 2 c The solder bump 6 of the semiconductor package 10 is defined as the wiring part 2 b The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -23-ϋ ϋ I n I '* l · 1 n ϋ · 1 one s, 1 «a— I Kfk n I line {please note the precautions on the back of Mtt before filling this page) ^ 62095 Α7 Β7 V. Description of the invention (21) Connection surface 2 e . (Please read the precautions on the back before filling in this page.) According to this, the protruding electrodes are not limited to the gold protrusions 4 in FIG. 2. Even the solder protrusions 6 can be positioned during reflow mounting. The industrial applicability is as described above. The semiconductor device and its manufacturing method of the present invention are very suitable for flip-chip bonding, and are suitable for flip-chip bonding in B GA packaged memory cards. Especially suitable for simulators or chips. Multi-chip modules with mixed components. (Brief description of the drawing) Fig. 1 (a): A plan view of a memory card structure as an example of a semiconductor device according to the first embodiment of the present invention. Fig. 1 (b) is a side view of a memca structure, which is an example of a semiconductor device according to the first embodiment of the present invention. Fig. 2 is a partially enlarged cross-sectional view showing the structure of a flip-chip joint of the semiconductor device of Fig. 1; Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 3: A flow chart of an example of the assembly sequence of the semiconductor device in Figure 1. Figure 4: A cross-sectional view of the semiconductor wafer structure in the semiconductor package assembly process of Figure 1. Fig. 5: Structural diagram of the wafer support substrate in the semiconductor device assembly process of Fig. 1, (a) is a partial cross-sectional view, and (b) is an enlarged cross-sectional view of a wiring portion. This paper size applies to China National Standard (CNS) A4 (210 X 297 MM) -24- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Hydrocarbons d 620 9 5 __B7_ V. Description of the invention (22) Figure 6: Figure 1 A cross-sectional view of a structural part when anisotropic conductive resin is stuck in a semiconductor device assembly process. Fig. 7: A structural drawing of a wafer when the semiconductor package assembly process of Fig. 1 is carried out, (a) is a partial cross-sectional view, and (b) is an enlarged cross-sectional view of a gold protrusion and a wiring portion. Fig. 8: Ten structural drawings of wafer thermal compression bonding in the semiconductor device assembling process of Fig. 1, (a) is a partial cross-sectional view, and (b) is an enlarged cross-sectional view of a connecting portion. Fig. 9 is a structural diagram of an FBGA, which is an example of a semiconductor device according to a second embodiment of the present invention. (A) is an external perspective view, and (b) is a sectional view. Fig. 10 (a), (b), (c), (d): Sectional views of an example of the structure of an assembly process corresponding to the F B GA of Fig. 9. FIG. 11 is a substrate structure diagram of a modified example of a wafer supporting substrate used in a semiconductor device of Embodiment 1, (a) is a partial cross-sectional view, (b) is an enlarged cross-sectional view of a wiring portion, and (c) is a wafer heat Partial sectional view after crimping. FIG. 12 is a structural view of a module product of a semiconductor device according to another embodiment of the present invention. (A) is a plan view, and (b) is a cross-sectional view taken along line A-A of (a). Fig. 13: Structural sectional view of the modification of the module product of Fig. 12 "
圖14:本發明另一實施形態之半導體裝置之多晶片 模組構造圖| (a)爲平面圖，（b)爲（a)之B — B 線斷面圖。 本紙張尺度適用中囷國家標準（CNS)A4規格（210 * 297公釐）-25- <請先閱讀背面之注意事項再填寫本頁) /4- 訂 4 -線 d 6 20 9 5 經濟部智慧財產局員工消費合作社印製 A7 ____B7_______ 五、發明說明（23 ) 圖15(a) 、 （b):實施形態1之半導體裝置使 用之異方性導電樹脂之變形例構造及其連接方法之部分斷 面圖。 圖 16(a) 、（b) 1 (c) 、（d) 、( e )： 使用圖15之異方性導電樹脂之覆晶接合方法之平面圖。 圖17:本發明另一實施形態之半導體裝置構造之擴 大部分斷面圖。 (符號說明） 1 半_體晶片 2 卡片基板 1 a 主 面 1 b 電 極 2 a 核心 基板 2 b 配 線 部 2 c 絕 緣 層 2 d 設 置 面 2 e 連 接 面 2 f 凹 部 2 h 薄 膜 絕緣層 2 i 內 壁 2 j 圖 型 領域 3 AC F 3 a 導 電 粒子 私紙張瓦度適用中國國家標準（CNS)A4規格（210 * 297公^~~Τ2βΤ -— — — ——--lit — — ^ * I I I I I — I alllll· — — I (諝先閱讀背面之^意事項再填寫本頁> A7 4 620 9 5 五、發明說明（24 ) 4 金突起 5 B G A基板 5 a , 8 a 晶片支持面 6 焊錫突起 7、8 模組基板 -----I--— II---',+- — — (——II « — — — —til — I I ] (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 7 a 連 接 器 7 b 晶 片 電 容 器 9 實裝 基 板 1 0 半 導 體 封 裝 1 1 配 線 基 板 2 0 記 憶 卡 3 0 F B G A 4 0 、5 0 模 擬 6 0 多 晶 片 模 組 本纸張又度適用中國國家標準（CNSM4規格（210 X 297公爱）-27 -Fig. 14: Structure diagram of a multi-chip module of a semiconductor device according to another embodiment of the present invention | (a) is a plan view, (b) is a cross-sectional view taken along line B-B of (a). This paper size applies to China National Standard (CNS) A4 specification (210 * 297 mm) -25- < Please read the notes on the back before filling this page) / 4- Order 4 -line d 6 20 9 5 Economy Printed by A7 ____B7_______ of the Consumer Cooperatives of the Ministry of Intellectual Property Bureau V. Description of the invention (23) Figure 15 (a), (b): Modified structure of anisotropic conductive resin used in the semiconductor device of Embodiment 1 and its connection method Partial sectional view. 16 (a), (b) 1 (c), (d), (e): Plan views of a flip-chip bonding method using the anisotropic conductive resin of FIG. Fig. 17 is an enlarged sectional view of a structure of a semiconductor device according to another embodiment of the present invention. (Symbol description) 1 Half_body wafer 2 Card substrate 1 a Main surface 1 b Electrode 2 a Core substrate 2 b Wiring section 2 c Insulation layer 2 d Setting surface 2 e Connection surface 2 f Recess 2 h Thin film insulation layer 2 i Inside Wall 2 j Pattern area 3 AC F 3 a Conductive particle private paper wattage Applies to Chinese National Standard (CNS) A4 specifications (210 * 297 public ^ ~~ Τ2βΤ-— — — — —lit — — ^ * IIIII — I alllll · — — I (谞 Please read the notice on the back before filling in this page> A7 4 620 9 5 V. Description of the invention (24) 4 Gold bumps 5 BGA substrate 5 a, 8 a Wafer support surface 6 Solder bumps 7, 8 Module substrate ----- I --- II --- ', +-— — (——II «— — — — til — II] (Please read the precautions on the back before filling this page ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 a Connector 7 b Chip capacitor 9 Mounted substrate 1 0 Semiconductor package 1 1 Wiring substrate 2 0 Memory card 3 0 FBGA 4 0, 5 0 Analog 6 0 Multi-chip module This paper is again applicable to Chinese national standards (CN SM4 Specifications (210 X 297 Public Love) -27-