TW202347279A - Display panel - Google Patents

Abstract

A display panel including a substrate, a plurality of pixel structure, a plurality of first multiplexers, a plurality of second multiplexers, a circuit board and a plurality of connection wires is provided. The substrate is provided with a display area, a hole disposed in the display area, a first non-display area located between the hole and the display area, and a second non-display area located on one side of the display area away from the hole. The pixel structures includes a plurality of first pixel structures and a plurality of second pixel structures respectively arranged on two opposite sides of the hole along a first direction. The first multiplexers disposed in the first non-display area are electrically connected to the first pixel structures. The second multiplexers disposed in the second non-display area are electrically connected to the second pixel structures. The circuit board is electrically connected to the first multiplexers via the connection wires disposed in the first non-display area.

Description

display panel

The present invention relates to a display panel, and in particular, to a display panel with holes.

With the development of display technology, in addition to improving display quality, it has also opened up diversified applications of display panels. Designing display panels that can be applied to different usage scenarios has become a development norm for relevant manufacturers. In recent years, smart watches, sports bracelets, or other wearable electronic devices have better demonstrated the infinite possibilities of display panels in daily life. Therefore, in addition to the high-standard requirements for environmental resistance of display panels mounted on such electronic devices, taste-related appearance design has become an important part of product development. In order to achieve different appearance designs, free form cutting technology for display panels has gradually become a necessary technology for relevant manufacturers.

At the beginning of product design, in order to optimize the matching relationship between the display panel and other components, openings corresponding to the shapes of other components can be designed at the edge or inside the display area. For example, a display panel used in a smart watch needs to have a hole surrounded by a display area so that the hands of the watch movement can pass through the display panel. However, in order to ensure the packaging yield, the drive circuit traces adjacent to the holes need to be designed to avoid the packaging area. In this way, the displayable area of the display panel is bound to be reduced. Therefore, how to increase the range of the displayable area and improve the design margin of its appearance while ensuring the packaging yield of the display panel is the development focus of relevant manufacturers.

The present invention provides a display panel in which the non-display area at the edge of the hole in the display area has a smaller arrangement space.

The display panel of the present invention includes a substrate, a plurality of pixel structures, a plurality of first multiplexers, a plurality of second multiplexers, a circuit board and a plurality of connecting traces. The substrate is provided with a display area, a hole provided in the display area, a first non-display area located between the hole and the display area, and a second non-display area located on a side of the display area away from the hole. These pixel structures are arranged in the display area and include a plurality of first pixel structures and a plurality of second pixel structures. These first pixel structures are arranged on one side of the hole along the first direction, and these second pixel structures are arranged on the other side of the hole along the first direction. The first pixel structures and the second pixel structures overlap the first non-display area along the first direction. The first multiplexers are disposed in the first non-display area and are electrically connected to the first pixel structures. The second multiplexers are disposed in the second non-display area and are electrically connected to the second pixel structures. The circuit board is electrically coupled to the second non-display area and electrically connected to the first multiplexers and the second multiplexers. These connection traces are arranged in the first non-display area and electrically connect the first multiplexers and the circuit board.

Based on the above, in the display panel according to an embodiment of the present invention, a hole is provided in the display area, and a non-display area is provided between the hole and the display area. A plurality of pixel structures located on one side of the hole are electrically connected to a circuit board located on the other side of the hole via a plurality of connecting traces provided in the non-display area. A plurality of multiplexers connecting these pixel structures and these connection lines are provided in the non-display area on one side of the hole. The setting of these multiplexers can effectively reduce the number of connection wiring configurations and reduce the configuration space required in the non-display area.

As used herein, "about," "approximately," "substantially," or "substantially" includes the stated value and an average within an acceptable range of deviations from a particular value as determined by one of ordinary skill in the art, taking into account that Discuss the measurement and the specific amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±15%, ±10%, ±5%, for example. Furthermore, the terms "approximately", "approximately", "substantially" or "substantially" used in this article can be used to select a more acceptable deviation range or standard deviation based on the measurement properties, cutting properties or other properties, and can Not one standard deviation applies to all properties.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections. Furthermore, "electrical connection" can be the presence of other components between the two components.

Additionally, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation illustrated in the figures. For example, if the device in one of the figures is turned over, elements described as "lower" than other elements would then be oriented "above" the other elements. Thus, the exemplary term "lower" may include both "lower" and "upper" orientations, depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "upper" or "lower" may include both upper and lower orientations.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and descriptions to refer to the same or similar parts.

FIG. 1 is a schematic top view of a display panel according to an embodiment of the present invention. FIG. 2 is an enlarged schematic diagram of a partial area of the display panel of FIG. 1 . Referring to FIGS. 1 and 2 , the display panel 10 includes a substrate 100 . The substrate 100 is provided with a display area DA, a hole 100h disposed in the display area DA, a first non-display area NDA1 located between the hole 100h and the display area DA, and a second non-display area NDA1 located on the side of the display area DA away from the hole 100h. Display area NDA2.

In this embodiment, the outer contour of the substrate 100 and the inner contour defining the hole 100h are both circular, for example, but are not limited to this. In other embodiments, at least one of the outer contour and the inner contour of the substrate may also be square. The material of the substrate 100 includes glass, quartz, organic polymer, or other suitable transparent materials.

In this embodiment, the display area DA, the first non-display area NDA1 and the second non-display area NDA2 are each arranged around the hole 100h, and the display area DA is located between the first non-display area NDA1 and the second non-display area NDA2 , but not limited to this. A packaging pattern 210 is provided in the first non-display area NDA1 closer to the hole 100h, and another packaging pattern 220 is provided in a location farther away from the hole 100h in the second non-display area NDA2.

For example, the display panel 10 may further include another substrate (not shown) and a display medium layer (not shown) disposed overlapping the substrate 100 . The packaging patterns 210 and 220 each connect the substrate 100 and the other substrate to form a sealed space. There is a display medium layer in this sealed space. The display medium layer is, for example, a liquid crystal layer or a light emitting diode layer.

In this embodiment, the material of the sealing pattern 210 and the sealing pattern 220 is, for example, glass frit, and the material of the glass frit may include manganese oxide (MnOx), zinc oxide (ZnO), and magnesium oxide (MgO). However, the present invention is not limited thereto. In other embodiments, the materials of the encapsulation pattern 210 and the encapsulation pattern 220 may also include acrylic resin, epoxy resin, photo-sensitive ) polymer material, or other suitable sealing materials.

In order to drive the display medium layer to achieve the image display effect, the display panel 10 further includes a plurality of pixel structures PX, a plurality of data lines DL and a plurality of scan lines GL arranged in the display area DA. These data lines DL intersect these scan lines GL, and divide the display area DA into multiple pixel areas. These pixel areas are respectively provided with multiple pixel structures PX. In this embodiment, the plurality of scan lines GL can be arranged along the direction D1 and extend in the direction D2, the plurality of data lines DL can be arranged along the direction D2 and extend in the direction D1, and the direction D1 can be selectively vertical. in direction D2, but not limited to this. Based on conductivity considerations, the data lines DL and scan lines GL are generally made of metal materials, such as aluminum, copper, molybdenum, chromium, palladium, or the above alloys, or the above stacked layers.

For example, the pixel structure PX may include an active element (not shown) and a pixel electrode (not shown) that are electrically connected to each other, where the active element is also electrically connected to a data line DL and a scan line GL. When the active device is turned on, the pixel electrode electrically connected to it can receive the driving signal (such as voltage or current) from the circuit board 300 through the data line DL, so that the dielectric layer can be displayed. By individually controlling these pixel structures PX, different parts of the display medium layer can be enabled to the same or different degrees to produce different light intensity or phase delay modulation, thereby achieving the purpose of displaying images. It should be noted that the components of the pixel structure PX (or pixel circuit) and their arrangement may vary depending on the type of display medium layer, and are not limited by the present invention.

In this embodiment, the circuit board 300 is electrically connected in the second non-display area NDA2. In detail, a plurality of bonding pads BP are provided in the second non-display area NDA2, and these bonding pads BP can be arranged in a region closer to the edge of the substrate in the second non-display area NDA2 along the direction D2. The circuit board 300 may be provided with a driver chip 350 and a plurality of signal channels CH. Each signal channel CH electrically connected to the driver chip 350 may be connected to a corresponding bonding pad BP through solder (not shown), but not with This is the limit.

The plurality of pixel structures PX include a plurality of first pixel structures PX1 and a plurality of second pixel structures PX2. These first pixel structures PX1 are disposed on one side of the hole 100h along the direction D1. These second pixel structures PX2 are disposed on the other side of the hole 100h along the direction D1, and are located between the hole 100h (or the first non-display area NDA1) and the second non-display area NDA2. It is particularly noted that these first pixel structures PX1 and second pixel structures PX2 overlap the first non-display area NDA1 along the direction D1. Therefore, the plurality of data lines DL electrically connecting the plurality of first pixel structures PX1 or the plurality of second pixel structures PX2 cannot extend from one side of the first non-display area NDA1 along the direction D1 to the first non-display area. NDA1 is along the other side of direction D1. That is to say, any first pixel structure PX1 and any second pixel structure PX2 arranged along the direction D1 are electrically independent of each other.

In this embodiment, in order to electrically connect these first pixel structures PX1 to the circuit board 300 located in the second non-display area NDA2, the first non-display area NDA1 of the display panel 10 is also provided with a plurality of connection traces. WR1 and multiple first multiplexers 151. These first multiplexers 151 are disposed between the holes 100h and the plurality of first pixel structures PX1. A plurality of first pixel structures PX1 arranged along the direction D1 may be electrically connected to a corresponding first multiplexer 151 via the connected data line DL.

For example, in this embodiment, each first multiplexer 151 can be electrically connected to a connecting wire WR1 and three data lines DL connecting a plurality of first pixel structures PX1, and each connecting wire WR1 Two first multiplexers 151 can be electrically connected. That is to say, the number correspondence relationship between the connection traces WR1 provided in the first non-display area NDA1 and the data lines DL provided in the display area DA and electrically connected to the first pixel structure PX1 is one-to-six. However, Not limited to this. Through the arrangement of the first multiplexer 151, the number of configurations of the connection wires WR1 can be effectively reduced, which helps to reduce the configuration space required for the first non-display area NDA1. In other words, the width of the inner frame of the display panel 10 can be effectively reduced, thereby increasing its screen-to-body ratio.

It is particularly noted that in this embodiment, the plurality of connection traces WR1 provided in the first non-display area NDA1 do not overlap with the packaging pattern 210 in the direction perpendicular to the surface of the substrate 100 . Accordingly, it can be avoided that the connection trace WR1 is peeled off due to high temperature during the packaging process, causing packaging failure, which helps to improve the packaging yield and reliability of the display panel 10 .

Similarly, in order to electrically connect the plurality of second pixel structures PX2 to the circuit board 300 located in the second non-display area NDA2, the second non-display area NDA2 of the display panel 10 is also provided with a plurality of connection traces WR2 and A plurality of second multiplexers 152. A plurality of second pixel structures PX2 are located between the holes 100h and the second multiplexers 152 . A plurality of second pixel structures PX2 arranged along the direction D1 may be electrically connected to a corresponding second multiplexer 152 via the connected data line DL.

For example, in this embodiment, each second multiplexer 152 can be electrically connected to one connecting wire WR2 and three data lines DL connected to the plurality of second pixel structures PX2, and each connecting wire WR2 Two second multiplexers 152 can be electrically connected. That is to say, the number correspondence relationship between the connection wires WR2 provided in the second non-display area NDA2 and the data lines DL provided in the display area DA and electrically connected to the second pixel structure PX2 is one-to-six. However, Not limited to this. Through the arrangement of the second multiplexer 152, the number of configurations of the connection wires WR2 can be effectively reduced, which helps to reduce the configuration space required for the second non-display area NDA2. In other words, the width of the outer frame of the display panel 10 can be effectively reduced, thereby increasing its screen-to-body ratio.

Based on the consideration of electrical conductivity, the material of the connecting trace WR1 and the connecting trace WR2 is generally a metal material, such as aluminum, copper, molybdenum, chromium, palladium, or the above alloy, or the above stacked layer.

In this embodiment, the plurality of first multiplexers 151 are electrically connected to a portion of the signal channels CH of the circuit board 300 via a plurality of connection traces WR1, and the plurality of second multiplexers 152 are connected via a plurality of connection traces WR2. It is electrically connected to another part of the signal channel CH of the circuit board 300 . Among them, a plurality of connection traces WR1 provided in the first non-display area NDA1 also extend to the second non-display area NDA2 through part of the second pixel structure PX2 to electrically connect to the circuit board 300 .

For example, in this embodiment, the connection traces WR1 do not overlap the second pixel structures PX2 in a direction perpendicular to the surface of the substrate 100 . Therefore, the arrangement pitch of the plurality of second pixel structures PX2 along the direction D2 is different from the arrangement pitch of the plurality of first pixel structures PX1 along the direction D2. In detail, the plurality of first pixel structures PX1 are respectively arranged along the direction D1 into a plurality of pixel rows PXC1, and these pixel rows PXC1 are arranged along the direction D2. The plurality of second pixel structures PX2 are respectively arranged into a plurality of pixel rows (such as pixel rows PX2a, pixel rows PXC2b, pixel rows PXC2c, pixel rows PXC2d and pixel rows PXC2e) along the direction D1, and these pixel rows are arranged along the direction D2 arrangement.

In this embodiment, the pixel row PXC2a and the pixel row PXC2b have an arrangement pitch P2a along the direction D2, and any two adjacent pixel rows PXC1 have an arrangement pitch P1 along the direction D2, and the arrangement pitch P1 is different from the arrangement pitch. from P2a. In addition, a connecting wire WR1 is provided between the pixel row PXC2b and the pixel row PXC2c located between the first non-display area NDA1 and the second non-display area NDA2. Therefore, the pixel row PXC2b and the pixel row PXC2c have an arrangement pitch P2b along the direction D2, and this arrangement pitch P2b is different from the arrangement pitch P2a between the pixel row PXC2a and the pixel row PXC2b and the arrangement pitch between the plurality of pixel rows PXC1 Distance from P1.

On the other hand, two connecting wires WR1 are provided between the pixel row PXC2d and the pixel row PXC2e. Therefore, the pixel row PXC2d and the pixel row PXC2e have an arrangement pitch P2c along the direction D2, and this arrangement pitch P2c is different from the arrangement pitch P2a between the pixel row PXC2a and the pixel row PXC2b, and the arrangement pitch P2c between the pixel row PXC2b and the pixel row PXC2c. The arrangement pitch P2b and the arrangement pitch P1 between the plurality of pixel rows PXC1.

However, the present invention is not limited to this. According to other embodiments, the connection trace WR1 may overlap the plurality of second pixel structures PX2 in a direction perpendicular to the surface of the substrate 100 . Therefore, the arrangement pitch of the plurality of first pixel structures PX1 along the direction D2 may be equal to the arrangement pitch of the plurality of second pixel structures PX2 along the direction D2.

FIG. 3 is a schematic top view of a display panel according to another embodiment of the present invention. Please refer to FIG. 3 . The difference between the display panel 10A of this embodiment and the display panel 10 of FIG. 2 is that the number of connection wires is different. In this embodiment, the number of connection traces of the display panel 10A in either the first non-display area NDA1 or the second non-display area NDA2 is half of the number of connection traces in FIG. 2 . For example, the number of connection traces WR1-A in the first non-display area NDA1 of the display panel 10A is reduced from four as shown in FIG. 2 to two, and the number of connection traces WR2-A in the second non-display area NDA2 is reduced to two. The six items shown in Figure 2 are reduced to three.

In order to further reduce the number of connection traces, the number of multiplexers electrically connected by a single connection trace is four. In other words, the number corresponding relationship between the connection traces WR1-A provided in the first non-display area NDA1 and the data lines DL provided in the display area DA and electrically connected to the first pixel structure PX1 is one pair of twelve relationship. Similarly, the number corresponding relationship between the connection traces WR2-A provided in the second non-display area NDA2 and the data lines DL provided in the display area DA and electrically connected to the second pixel structure PX2 is one pair of twelve relation. Accordingly, the required configuration space of the first non-display area NDA1 and the second non-display area NDA2 can be further reduced, which helps to increase the screen-to-body ratio of the display panel 10A.

FIG. 4 is a schematic top view of a display panel according to another embodiment of the present invention. Please refer to FIG. 4 . The difference between the display panel 10B of this embodiment and the display panel 10 of FIG. 1 is that the configuration of the holes is different. Different from the hole 100h of the display panel 10 in Figure 1 which is a closed hole, the hole 100h" of the display panel 10B of this embodiment is an open hole. For example, the hole 100h" of the substrate 100A has one side of it along the direction D1 The display area DA" is disconnected. That is to say, the display area DA", the first non-display area NDA1" and the second non-display area NDA2" of this embodiment are not arranged around the hole 100h".

Specifically, in this embodiment, the first non-display area NDA1" is connected with the second non-display area NDA2" and surrounds the display area DA". Therefore, the packaging pattern provided in the first non-display area NDA1" 210A is connected to the packaging pattern 220A provided in the second non-display area NDA2" and surrounds the display area DA".

Since the arrangement of the multiplexers and connecting wires in this embodiment is similar to that of the display panel 10 in FIG. 2 , please refer to the relevant paragraphs and corresponding drawings of the foregoing embodiments for detailed description, and will not be described again here.

To sum up, in the display panel according to an embodiment of the present invention, a hole is provided in the display area, and a non-display area is provided between the hole and the display area. A plurality of pixel structures located on one side of the hole are electrically connected to a circuit board located on the other side of the hole via a plurality of connecting traces provided in the non-display area. A plurality of multiplexers connecting these pixel structures and these connection lines are provided in the non-display area on one side of the hole. The setting of these multiplexers can effectively reduce the number of connection wiring configurations and reduce the configuration space required in the non-display area.

10, 10A, 10B: display panel 100, 100A: substrate 100h, 100h”: holes 151, 152: Multiplexer 210, 220, 210A, 220A: Package pattern 300:Circuit board 350: Driver chip BP: bonding pad CH: signal channel DA, DA”: display area D1, D2: direction DL: data line GL: scan line NDA1, NDA1”: first non-display area NDA2, NDA2”: the second non-display area P1, P2a, P2b, P2c: arrangement pitch PX, PX1, PX2: pixel structure PXC1, PXC2a, PXC2b, PXC2c, PXC2d, PXC2e: pixel row WR1, WR2, WR1-A, WR2-A: connection wiring

FIG. 1 is a schematic top view of a display panel according to an embodiment of the present invention. FIG. 2 is an enlarged schematic diagram of a partial area of the display panel of FIG. 1 . FIG. 3 is a schematic top view of a display panel according to another embodiment of the present invention. FIG. 4 is a schematic top view of a display panel according to another embodiment of the present invention.

10:Display panel

100:Substrate

100h: hole

151, 152: Multiplexer

210, 220: Package pattern

300:Circuit board

350: Driver chip

BP: bonding pad

CH: signal channel

DA: display area

D1, D2: direction

DL: data line

GL: scan line

NDA1: first non-display area

NDA2: Second non-display area

P1, P2a, P2b, P2c: arrangement pitch

PX, PX1, PX2: pixel structure

PXC1, PXC2a, PXC2b, PXC2c, PXC2d, PXC2e: pixel row

WR1, WR2: connection wiring

Claims (10)

A display panel including: A substrate is provided with a display area, a hole provided in the display area, a first non-display area between the hole and the display area, and a second non-display area on the side of the display area away from the hole. non-display area; A plurality of pixel structures are disposed in the display area and include a plurality of first pixel structures and a plurality of second pixel structures. The first pixel structures are disposed in a direction of the hole along a first direction. side, the second pixel structures are disposed on the other side of the hole along the first direction, and the first pixel structures and the second pixel structures overlap the first pixel structure along the first direction. non-display area; A plurality of first multiplexers are disposed in the first non-display area and are electrically connected to the first pixel structures; A plurality of second multiplexers are disposed in the second non-display area and are electrically connected to the second pixel structures; A circuit board electrically coupled to the second non-display area and electrically connected to the first multiplexers and the second multiplexers; and A plurality of connection traces are arranged in the first non-display area and electrically connect the first multiplexers and the circuit board. The display panel of claim 1, wherein the first pixel structures are respectively arranged into a plurality of first pixel rows along the first direction, and the second pixel structures are arranged into a plurality of first pixel rows along the first direction. A plurality of second pixel rows, the arrangement pitch of the first pixel rows along a second direction is different from the arrangement pitch of the second pixel rows along the second direction, and the second direction intersects with the first pixel row. One direction. The display panel as claimed in claim 1, wherein the circuit board has a driver chip and a plurality of signal channels, and a part of the signal channels are electrically connected to the second multiplexers and the driver chip. The other part is electrically connected to the first multiplexers and the driver chip. The display panel of claim 1 further includes a packaging pattern disposed in the first non-display area and surrounding the hole. The display panel of claim 4, wherein the connection traces do not overlap the packaging pattern. The display panel of claim 1, wherein the first multiplexers are located between the hole and the first pixel structures, and the second pixel structures are located between the hole and the second between multiplexers. The display panel of claim 1, wherein the connection traces extend to the second non-display area through part of the second pixel structures. The display panel of claim 7, wherein the connection traces do not overlap the second pixel structures. The display panel of claim 7, wherein the second pixel structures are arranged into a plurality of pixel rows along a first direction, and the pixel rows are arranged in the first non-display area along a second direction. Between the second non-display area and the second non-display area, the pixel rows include a first pixel row, a second pixel row and a third pixel row adjacent to each other, and the distance between the first pixel row and the second pixel row is A first arrangement pitch is different from a second arrangement pitch between the second pixel row and the third pixel row. The display panel of claim 9, wherein the pixel rows further include a fourth pixel row and a fifth pixel row adjacent to each other, and a third arrangement between the fourth pixel row and the fifth pixel row The pitch is different from the first arrangement pitch and the second arrangement pitch.

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